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https://github.com/openhwgroup/cvw
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Added UART output file buildroot_uart.out for Linux test 'buildroot'.
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@ -7,4 +7,4 @@ export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=100"
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#export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000"
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#export OTHERFLAGS="+TRACE2LOG_ENABLE=1 +TRACE2LOG_AFTER=10500000"
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#export OTHERFLAGS=""
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#export OTHERFLAGS=""
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vsim -do "do wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0"
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vsim -c -do "do wally-linux-imperas.do buildroot buildroot $::env(RISCV) 0 0 0"
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@ -236,7 +236,7 @@ module testbench;
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logic ResetCntRst;
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logic ResetCntRst;
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logic CopyRAM;
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logic CopyRAM;
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string signame, memfilename, bootmemfilename, pathname;
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string signame, memfilename, bootmemfilename, uartoutfilename, pathname;
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integer begin_signature_addr, end_signature_addr, signature_size;
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integer begin_signature_addr, end_signature_addr, signature_size;
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assign ResetThreshold = 3'd5;
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assign ResetThreshold = 3'd5;
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@ -299,6 +299,7 @@ module testbench;
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// Find the test vector files and populate the PC to function label converter
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// Find the test vector files and populate the PC to function label converter
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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logic [P.XLEN-1:0] testadr;
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logic [P.XLEN-1:0] testadr;
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integer memFile;
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assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
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assign begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
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assign end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
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assign end_signature_addr = ProgramAddrLabelArray["sig_end_canary"];
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assign signature_size = end_signature_addr - begin_signature_addr;
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assign signature_size = end_signature_addr - begin_signature_addr;
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@ -308,6 +309,10 @@ module testbench;
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else if(TEST == "buildroot") begin
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else if(TEST == "buildroot") begin
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memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
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memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
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bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
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bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
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uartoutfilename = {"logs/",TEST,"_uart.out"};
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// Initialize uart output file
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memFile = $fopen(uartoutfilename, "w"); // Clear existing values in uartFile
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$fclose(memFile);
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end
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end
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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if (riscofTest) begin
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if (riscofTest) begin
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@ -389,7 +394,6 @@ module testbench;
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integer StartIndex;
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integer StartIndex;
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integer EndIndex;
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integer EndIndex;
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integer BaseIndex;
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integer BaseIndex;
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integer memFile;
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integer readResult;
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integer readResult;
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if (P.SDC_SUPPORTED) begin
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if (P.SDC_SUPPORTED) begin
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always @(posedge clk) begin
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always @(posedge clk) begin
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@ -547,6 +551,16 @@ module testbench;
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.clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
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.clk(clk), .ProgramAddrMapFile(ProgramAddrMapFile), .ProgramLabelMapFile(ProgramLabelMapFile));
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end
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end
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// Write UART output to file for tests
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always @(posedge clk) begin
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if (TEST == "buildroot") begin
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if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin
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memFile = $fopen(uartoutfilename, "ab");
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$fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din);
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$fclose(memFile);
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end
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end
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end
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// Termination condition
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// Termination condition
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// terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed
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// terminate on a specific ECALL after li x3,1 for old Imperas tests, *** remove this when old imperas tests are removed
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