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Merge pull request #304 from ross144/main
Fixes bug 203 and linux/ImperasDV mismatch at 571M instructions
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535a01cce8
@ -69,7 +69,8 @@ module hptw import cvw::*; #(parameter cvw_t P) (
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L1_ADR, L1_RD,
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L1_ADR, L1_RD,
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L2_ADR, L2_RD,
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L2_ADR, L2_RD,
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L3_ADR, L3_RD,
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L3_ADR, L3_RD,
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LEAF, IDLE, UPDATE_PTE} statetype;
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LEAF, IDLE, UPDATE_PTE,
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FAULT} statetype;
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logic DTLBWalk; // register TLBs translation miss requests
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logic DTLBWalk; // register TLBs translation miss requests
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logic [P.PPN_BITS-1:0] BasePageTablePPN;
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logic [P.PPN_BITS-1:0] BasePageTablePPN;
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@ -258,38 +259,44 @@ module hptw import cvw::*; #(parameter cvw_t P) (
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flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState);
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flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState);
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always_comb
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always_comb
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case (WalkerState)
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case (WalkerState)
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IDLE: if (TLBMiss & ~DCacheStallM & ~HPTWAccessFaultDelay) NextWalkerState = InitialWalkerState;
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IDLE: if (TLBMiss & ~DCacheStallM) NextWalkerState = InitialWalkerState;
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else NextWalkerState = IDLE;
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else NextWalkerState = IDLE;
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L3_ADR: NextWalkerState = L3_RD; // first access in SV48
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L3_ADR: NextWalkerState = L3_RD; // first access in SV48
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L3_RD: if (DCacheStallM) NextWalkerState = L3_RD;
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L3_RD: if (DCacheStallM) NextWalkerState = L3_RD;
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else if(LSUAccessFaultM) NextWalkerState = IDLE;
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else if(LSUAccessFaultM) NextWalkerState = FAULT;
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else NextWalkerState = L2_ADR;
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else NextWalkerState = L2_ADR;
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L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // first access in SV39
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L2_ADR: if (InitialWalkerState == L2_ADR | ValidNonLeafPTE) NextWalkerState = L2_RD; // first access in SV39
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else NextWalkerState = LEAF;
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else NextWalkerState = LEAF;
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L2_RD: if (DCacheStallM) NextWalkerState = L2_RD;
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L2_RD: if (DCacheStallM) NextWalkerState = L2_RD;
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else if(LSUAccessFaultM) NextWalkerState = IDLE;
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else if(LSUAccessFaultM) NextWalkerState = FAULT;
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else NextWalkerState = L1_ADR;
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else NextWalkerState = L1_ADR;
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L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32
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L1_ADR: if (InitialWalkerState == L1_ADR | ValidNonLeafPTE) NextWalkerState = L1_RD; // first access in SV32
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else NextWalkerState = LEAF;
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else NextWalkerState = LEAF;
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L1_RD: if (DCacheStallM) NextWalkerState = L1_RD;
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L1_RD: if (DCacheStallM) NextWalkerState = L1_RD;
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else if(LSUAccessFaultM) NextWalkerState = IDLE;
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else if(LSUAccessFaultM) NextWalkerState = FAULT;
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else NextWalkerState = L0_ADR;
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else NextWalkerState = L0_ADR;
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L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD;
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L0_ADR: if (ValidNonLeafPTE) NextWalkerState = L0_RD;
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else NextWalkerState = LEAF;
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else NextWalkerState = LEAF;
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L0_RD: if (DCacheStallM) NextWalkerState = L0_RD;
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L0_RD: if (DCacheStallM) NextWalkerState = L0_RD;
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else if(LSUAccessFaultM) NextWalkerState = IDLE;
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else if(LSUAccessFaultM) NextWalkerState = FAULT;
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else NextWalkerState = LEAF;
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else NextWalkerState = LEAF;
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LEAF: if (P.SVADU_SUPPORTED & HPTWUpdateDA) NextWalkerState = UPDATE_PTE;
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LEAF: if (P.SVADU_SUPPORTED & HPTWUpdateDA) NextWalkerState = UPDATE_PTE;
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else NextWalkerState = IDLE;
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else NextWalkerState = IDLE;
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UPDATE_PTE: if(DCacheStallM) NextWalkerState = UPDATE_PTE;
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UPDATE_PTE: if(DCacheStallM) NextWalkerState = UPDATE_PTE;
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else NextWalkerState = LEAF;
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else NextWalkerState = LEAF;
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FAULT: NextWalkerState = IDLE;
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default: NextWalkerState = IDLE; // should never be reached
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default: NextWalkerState = IDLE; // should never be reached
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endcase // case (WalkerState)
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endcase // case (WalkerState)
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assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMiss) | (LSUAccessFaultM); // RT : 05 April 2023 if hptw request has pmp/a fault suppress bus access.
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assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMiss) | (LSUAccessFaultM); // RT : 05 April 2023 if hptw request has pmp/a fault suppress bus access.
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assign SelHPTW = WalkerState != IDLE;
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assign SelHPTW = WalkerState != IDLE;
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// RT 30 May 2023: When there is an access fault caused by the hptw itself, the fsm jumps to FAULT, removes
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// stall and asserts one of HPTWLoadAccessFault, HPTWStoreAmoAccessFault or HPTWInstrAccessFaultDelay.
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// The FSM directly transistions to IDLE to ready for the next operation when the delayed version will not be high.
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assign HPTWAccessFaultDelay = HPTWLoadAccessFaultDelay | HPTWStoreAmoAccessFaultDelay | HPTWInstrAccessFaultDelay;
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assign HPTWAccessFaultDelay = HPTWLoadAccessFaultDelay | HPTWStoreAmoAccessFaultDelay | HPTWInstrAccessFaultDelay;
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assign HPTWStall = (WalkerState != IDLE) | (WalkerState == IDLE & TLBMiss & ~(HPTWAccessFaultDelay));
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assign HPTWStall = (WalkerState != IDLE & WalkerState != FAULT) | (WalkerState == IDLE & TLBMiss);
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assign ITLBMissOrUpdateDAF = ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF);
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assign ITLBMissOrUpdateDAF = ITLBMissF | (P.SVADU_SUPPORTED & InstrUpdateDAF);
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assign DTLBMissOrUpdateDAM = DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM);
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assign DTLBMissOrUpdateDAM = DTLBMissM | (P.SVADU_SUPPORTED & DataUpdateDAM);
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