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Merge pull request #1000 from AnonymousVikram/fetch_buffer_vk

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Distributed And-Or MUX
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Jordan Carlin 2024-10-10 13:26:27 -07:00 committed by GitHub
commit 532969fec3
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2 changed files with 40 additions and 27 deletions
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65
src/ifu/fetchbuffer.sv
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@ -29,43 +29,56 @@
module fetchbuffer import cvw::*; #(parameter cvw_t P) (
input logic clk, reset,
input logic StallD, FlushD,
input logic [31:0] writeData,
output logic [31:0] readData,
input logic [31:0] WriteData,
output logic [31:0] ReadData,
output logic FetchBufferStallF
);
localparam [31:0] nop = 32'h00000013;
logic [31:0] readf0, readf1, readf2, readMuxed;
logic [2:0] readPtr, writePtr;
logic empty, full;
logic [31:0] Readf0, Readf1, Readf2, ReadFetchBuffer;
logic [2:0] ReadPtr, WritePtr;
logic Empty, Full;
assign empty = |(readPtr & writePtr); // Bitwise and the read&write ptr, and or the bits of the result together
assign full = |({writePtr[1:0], writePtr[2]} & readPtr); // Same as above but left rotate writePtr to "add 1"
assign FetchBufferStallF = full;
assign Empty = |(ReadPtr & WritePtr); // Bitwise and the read&write ptr, and or the bits of the result together
assign Full = |({WritePtr[1:0], WritePtr[2]} & ReadPtr); // Same as above but left rotate WritePtr to "add 1"
assign FetchBufferStallF = Full;
// will go in a generate block once this is parameterized
flopenr #(32) f0 (.clk, .reset(reset | FlushD), .en(writePtr[0]), .d(writeData), .q(readf0));
flopenr #(32) f1 (.clk, .reset(reset | FlushD), .en(writePtr[1]), .d(writeData), .q(readf1));
flopenr #(32) f2 (.clk, .reset(reset | FlushD), .en(writePtr[2]), .d(writeData), .q(readf2));
flopenr #(32) f0 (.clk, .reset(reset | FlushD), .en(WritePtr[0]), .d(WriteData), .q(Readf0));
flopenr #(32) f1 (.clk, .reset(reset | FlushD), .en(WritePtr[1]), .d(WriteData), .q(Readf1));
flopenr #(32) f2 (.clk, .reset(reset | FlushD), .en(WritePtr[2]), .d(WriteData), .q(Readf2));
always_comb begin : readMuxes
// Mux read data from the three registers
case (readPtr)
3'b001: readMuxed = readf0;
3'b010: readMuxed = readf1;
3'b100: readMuxed = readf2;
default: readMuxed = nop; // just in case?
endcase
// issue nop when appropriate
readData = empty ? nop : readMuxed;
end
// always_comb begin : readMuxes
// // Mux read data from the three registers
// case (ReadPtr)
// 3'b001: ReadFetchBuffer = Readf0;
// 3'b010: ReadFetchBuffer = Readf1;
// 3'b100: ReadFetchBuffer = Readf2;
// default: ReadFetchBuffer = nop; // just in case?
// endcase
// // issue nop when appropriate
// ReadData = Empty ? nop : ReadFetchBuffer;
// end
// Fetch buffer entries anded with read ptr for AO Muxing
logic [31:0] DaoArr [2:0];
// ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Make parameterizable
assign DaoArr[0] = ReadPtr[0] ? Readf0 : '0;
assign DaoArr[1] = ReadPtr[1] ? Readf1 : '0;
assign DaoArr[2] = ReadPtr[2] ? Readf2 : '0;
or_rows #(3, 32) ReadFBAOMux(.a(DaoArr), .y(ReadFetchBuffer));
// ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Make parameterizable
assign ReadData = Empty ? nop : ReadFetchBuffer;
always_ff @(posedge clk) begin : shiftRegister
if (reset) begin
writePtr <= 3'b001;
readPtr <= 3'b001;
WritePtr <= 3'b001;
ReadPtr <= 3'b001;
end else begin
writePtr <= ~full ? {writePtr[1:0], writePtr[2]} : writePtr;
readPtr <= ~(StallD | empty) ? {readPtr[1:0], readPtr[2]} : readPtr;
WritePtr <= ~Full ? {WritePtr[1:0], WritePtr[2]} : WritePtr;
ReadPtr <= ~(StallD | Empty) ? {ReadPtr[1:0], ReadPtr[2]} : ReadPtr;
end
end
endmodule

2
src/ifu/ifu.sv
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@ -305,7 +305,7 @@ module ifu import cvw::*; #(parameter cvw_t P) (
// flopenl #(32) AlignedInstrRawDFlop(clk, reset | FlushD, ~StallD, PostSpillInstrRawF, nop, InstrRawD);
// TODO: Test this?!?!?!
fetchbuffer #(P) fetchbuff(.clk, .reset, .StallD, .FlushD, .writeData(PostSpillInstrRawF), .readData(InstrRawD), .FetchBufferStallF); // Figure out what TODO with StallF
fetchbuffer #(P) fetchbuff(.clk, .reset, .StallD, .FlushD, .WriteData(PostSpillInstrRawF), .ReadData(InstrRawD), .FetchBufferStallF); // Figure out what TODO with StallF
////////////////////////////////////////////////////////////////////////////////////////////////
// PCNextF logic