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https://github.com/openhwgroup/cvw
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Merge pull request #901 from JacobPease/main
Turned off RVVI by default.
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commit
5299eef6a6
@ -89,8 +89,8 @@ report_clock_interaction -file re
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write_verilog -force -mode funcsim sim/syn-funcsim.v
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write_verilog -force -mode funcsim sim/syn-funcsim.v
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if {$board=="ArtyA7"} {
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if {$board=="ArtyA7"} {
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#source ../constraints/small-debug.xdc
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source ../constraints/small-debug.xdc
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source ../constraints/small-debug-rvvi.xdc
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#source ../constraints/small-debug-rvvi.xdc
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} else {
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} else {
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source ../constraints/vcu-small-debug.xdc
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source ../constraints/vcu-small-debug.xdc
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}
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}
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@ -28,7 +28,7 @@
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import cvw::*;
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import cvw::*;
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module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 1)
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module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
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(input default_100mhz_clk,
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(input default_100mhz_clk,
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(* mark_debug = "true" *) input resetn,
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(* mark_debug = "true" *) input resetn,
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input south_reset,
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input south_reset,
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