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Merge pull request #901 from JacobPease/main

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Turned off RVVI by default.
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Rose Thompson 2024-08-08 13:53:10 -05:00 committed by GitHub
commit 5299eef6a6
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2 changed files with 3 additions and 3 deletions
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4
fpga/generator/wally.tcl
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@ -89,8 +89,8 @@ report_clock_interaction -file re
write_verilog -force -mode funcsim sim/syn-funcsim.v
if {$board=="ArtyA7"} {
#source ../constraints/small-debug.xdc
source ../constraints/small-debug-rvvi.xdc
source ../constraints/small-debug.xdc
#source ../constraints/small-debug-rvvi.xdc
} else {
source ../constraints/vcu-small-debug.xdc
}

2
fpga/src/fpgaTopArtyA7.sv
View File

@ -28,7 +28,7 @@
import cvw::*;
module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 1)
module fpgaTop #(parameter logic RVVI_SYNTH_SUPPORTED = 0)
(input default_100mhz_clk,
(* mark_debug = "true" *) input resetn,
input south_reset,