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Adjusted DTIM to always be 512B independent of XLEN

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David Harris 2023-02-19 16:14:38 -08:00
parent 00d54cfe6c
commit 5287c54278
1 changed files with 7 additions and 3 deletions
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10
src/lsu/dtim.sv
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@ -42,12 +42,16 @@ module dtim(
logic we; logic we;
localparam ADDR_WDITH = $clog2(`DTIM_RANGE/8); localparam LLENBYTES = `LLEN/8;
localparam OFFSET = $clog2(`LLEN/8); // verilator lint_off WIDTH
localparam DEPTH = `DTIM_RANGE/LLENBYTES;
// verilator lint_on WIDTH
localparam ADDR_WDITH = $clog2(DEPTH);
localparam OFFSET = $clog2(LLENBYTES);
assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap. assign we = MemRWM[0] & ~FlushW; // have to ignore write if Trap.
ram1p1rwbe #(.DEPTH(`DTIM_RANGE/8), .WIDTH(`LLEN)) ram1p1rwbe #(.DEPTH(DEPTH), .WIDTH(`LLEN))
ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM)); ram(.clk, .ce, .we, .bwe(ByteMaskM), .addr(DTIMAdr[ADDR_WDITH+OFFSET-1:OFFSET]), .dout(ReadDataWordM), .din(WriteDataM));
endmodule endmodule