From 525c7120b45aaeb3ab0a7f49f9ffc97dec2569c6 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 29 Dec 2021 21:26:15 -0600 Subject: [PATCH] Rename of dcache interface signals. --- wally-pipelined/src/cache/dcache.sv | 12 ++++------ wally-pipelined/src/cache/dcachefsm.sv | 20 ++++++++-------- wally-pipelined/src/lsu/lsu.sv | 32 ++++++++------------------ 3 files changed, 25 insertions(+), 39 deletions(-) diff --git a/wally-pipelined/src/cache/dcache.sv b/wally-pipelined/src/cache/dcache.sv index 92b468cef..827dcb1b5 100644 --- a/wally-pipelined/src/cache/dcache.sv +++ b/wally-pipelined/src/cache/dcache.sv @@ -31,12 +31,10 @@ module dcache input logic CPUBusy, // cpu side - input logic [1:0] MemRWM, - input logic [2:0] Funct3M, - input logic [6:0] Funct7M, - input logic [1:0] AtomicM, + input logic [1:0] LsuRWM, + input logic [1:0] LsuAtomicM, input logic FlushDCacheM, - input logic [11:0] MemAdrE, // virtual address, but we only use the lower 12 bits. + input logic [11:0] LsuAdrE, // virtual address, but we only use the lower 12 bits. input logic [`PA_BITS-1:0] LsuPAdrM, // physical address input logic [`XLEN-1:0] FinalWriteDataM, @@ -122,7 +120,7 @@ module dcache // Read Path CPU (IEU) side mux3 #(INDEXLEN) - AdrSelMux(.d0(MemAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), + AdrSelMux(.d0(LsuAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d1(LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), .d2(FlushAdr), .s(SelAdrM), @@ -249,7 +247,7 @@ module dcache // controller dcachefsm dcachefsm(.clk, .reset, .DCacheFetchLine, .DCacheWriteLine, .DCacheBusAck, - .MemRWM, .AtomicM, .CPUBusy, .CacheableM, .IgnoreRequest, + .LsuRWM, .LsuAtomicM, .CPUBusy, .CacheableM, .IgnoreRequest, .CacheHit, .VictimDirty, .DCacheStall, .DCacheCommittedM, .DCacheMiss, .DCacheAccess, .SelAdrM, .SetValid, .ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnableM, diff --git a/wally-pipelined/src/cache/dcachefsm.sv b/wally-pipelined/src/cache/dcachefsm.sv index 418a1ad20..7be9fd677 100644 --- a/wally-pipelined/src/cache/dcachefsm.sv +++ b/wally-pipelined/src/cache/dcachefsm.sv @@ -29,8 +29,8 @@ module dcachefsm (input logic clk, input logic reset, // inputs from IEU - input logic [1:0] MemRWM, - input logic [1:0] AtomicM, + input logic [1:0] LsuRWM, + input logic [1:0] LsuAtomicM, input logic FlushDCacheM, // hazard inputs input logic CPUBusy, @@ -94,7 +94,7 @@ module dcachefsm (* mark_debug = "true" *) statetype CurrState, NextState; - assign AnyCPUReqM = |MemRWM | (|AtomicM); + assign AnyCPUReqM = |LsuRWM | (|LsuAtomicM); // outputs for the performance counters. assign DCacheAccess = AnyCPUReqM & CacheableM & CurrState == STATE_READY; @@ -156,7 +156,7 @@ module dcachefsm end // amo hit - else if(AtomicM[1] & (&MemRWM) & CacheableM & CacheHit) begin + else if(LsuAtomicM[1] & (&LsuRWM) & CacheableM & CacheHit) begin SelAdrM = 2'b01; DCacheStall = 1'b0; @@ -172,7 +172,7 @@ module dcachefsm end end // read hit valid cached - else if(MemRWM[1] & CacheableM & CacheHit) begin + else if(LsuRWM[1] & CacheableM & CacheHit) begin DCacheStall = 1'b0; LRUWriteEn = 1'b1; @@ -185,7 +185,7 @@ module dcachefsm end end // write hit valid cached - else if (MemRWM[0] & CacheableM & CacheHit) begin + else if (LsuRWM[0] & CacheableM & CacheHit) begin SelAdrM = 2'b01; DCacheStall = 1'b0; SRAMWordWriteEnableM = 1'b1; @@ -201,7 +201,7 @@ module dcachefsm end end // read or write miss valid cached - else if((|MemRWM) & CacheableM & ~CacheHit) begin + else if((|LsuRWM) & CacheableM & ~CacheHit) begin NextState = STATE_MISS_FETCH_WDV; DCacheStall = 1'b1; DCacheFetchLine = 1'b1; @@ -244,11 +244,11 @@ module dcachefsm STATE_MISS_READ_WORD: begin SelAdrM = 2'b01; DCacheStall = 1'b1; - if (MemRWM[0] & ~AtomicM[1]) begin // handles stores and amo write. + if (LsuRWM[0] & ~LsuAtomicM[1]) begin // handles stores and amo write. NextState = STATE_MISS_WRITE_WORD; end else begin NextState = STATE_MISS_READ_WORD_DELAY; - // delay state is required as the read signal MemRWM[1] is still high when we + // delay state is required as the read signal LsuRWM[1] is still high when we // return to the ready state because the cache is stalling the cpu. end end @@ -258,7 +258,7 @@ module dcachefsm SRAMWordWriteEnableM = 1'b0; SetDirty = 1'b0; LRUWriteEn = 1'b0; - if(&MemRWM & AtomicM[1]) begin // amo write + if(&LsuRWM & LsuAtomicM[1]) begin // amo write SelAdrM = 2'b01; if(CPUBusy) begin NextState = STATE_CPU_BUSY_FINISH_AMO; diff --git a/wally-pipelined/src/lsu/lsu.sv b/wally-pipelined/src/lsu/lsu.sv index f0de651cc..e5c9d66cd 100644 --- a/wally-pipelined/src/lsu/lsu.sv +++ b/wally-pipelined/src/lsu/lsu.sv @@ -100,7 +100,7 @@ module lsu logic [2:0] LsuFunct3M; logic [1:0] LsuAtomicM; logic [`PA_BITS-1:0] PreLsuPAdrM, LocalLsuBusAdr; - logic [11:0] LsuAdrE, DCacheAdrE; + logic [11:0] PreLsuAdrE, LsuAdrE; logic CPUBusy; logic MemReadM; logic DCacheStall; @@ -148,7 +148,7 @@ module lsu mux2 #(2) rwmux(MemRWM, {HPTWRead, 1'b0}, SelHPTW, PreLsuRWM); mux2 #(3) sizemux(Funct3M, HPTWSize, SelHPTW, LsuFunct3M); mux2 #(2) atomicmux(AtomicM, 2'b00, SelHPTW, LsuAtomicM); - mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, LsuAdrE); + mux2 #(12) adremux(IEUAdrE[11:0], HPTWAdr[11:0], SelHPTW, PreLsuAdrE); mux2 #(`PA_BITS) lsupadrmux(IEUAdrExtM[`PA_BITS-1:0], HPTWAdr, SelHPTW, PreLsuPAdrM); // always block interrupts when using the hardware page table walker. @@ -163,13 +163,13 @@ module lsu assign DTLBStorePageFaultM = DTLBPageFaultM & PreLsuRWM[0]; // When replaying CPU memory request after PTW select the IEUAdrM for correct address. - assign DCacheAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : LsuAdrE; + assign LsuAdrE = SelReplayCPURequest ? IEUAdrM[11:0] : PreLsuAdrE; end // if (`MEM_VIRTMEM) else begin assign InterlockStall = 1'b0; - assign DCacheAdrE = LsuAdrE; + assign LsuAdrE = PreLsuAdrE; assign SelHPTW = 1'b0; assign IgnoreRequest = 1'b0; @@ -181,7 +181,7 @@ module lsu assign PreLsuRWM = MemRWM; assign LsuFunct3M = Funct3M; assign LsuAtomicM = AtomicM; - assign LsuAdrE = IEUAdrE[11:0]; + assign PreLsuAdrE = IEUAdrE[11:0]; assign PreLsuPAdrM = IEUAdrExtM; assign CPUBusy = StallW; @@ -304,26 +304,14 @@ module lsu logic DCacheBusAck; logic SelUncachedAdr; - dcache dcache(.clk, .reset, .CPUBusy, - .MemRWM(LsuRWM), - .Funct3M(LsuFunct3M), - .Funct7M, .FlushDCacheM, - .AtomicM(LsuAtomicM), - .MemAdrE(DCacheAdrE), - .LsuPAdrM, + .LsuRWM, .FlushDCacheM, .LsuAtomicM, .LsuAdrE, .LsuPAdrM, .FinalWriteDataM, .ReadDataWordM, .DCacheStall, - .DCacheMiss, .DCacheAccess, .IgnoreRequest, - .CacheableM(CacheableM), - .DCacheCommittedM, - .DCacheBusAdr, - .ReadDataBlockSetsM, - .DCacheMemWriteData, - .DCacheFetchLine, - .DCacheWriteLine, - .DCacheBusAck - ); + .DCacheMiss, .DCacheAccess, + .IgnoreRequest, .CacheableM, .DCacheCommittedM, + .DCacheBusAdr, .ReadDataBlockSetsM, .DCacheMemWriteData, + .DCacheFetchLine, .DCacheWriteLine,.DCacheBusAck);