Gated MDU to save power; doesn't seem to have affected simulation time

src/ieu/controller.sv

@@ -59,6 +59,7 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   output logic [2:0]  ZBBSelectE,              // ZBB mux select signal in Execute stage
   output logic [2:0]  BALUControlE,            // ALU Control signals for B instructions in Execute Stage
   output logic        BMUActiveE,              // Bit manipulation instruction being executed
+  output logic        MDUActiveE,              // Mul/Div instruction being executed
 
   // Memory stage control signals
   input  logic        StallM, FlushM,          // Stall, flush Memory stage
@@ -319,6 +320,7 @@ module controller import cvw::*;  #(parameter cvw_t P) (
   // Other execute stage controller signals
   assign MemReadE = MemRWE[1];
   assign SCE = (ResultSrcE == 3'b100);
+  assign MDUActiveE = (ResultSrcE == 3'b011);
   assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
   assign IntDivE = MDUE & Funct3E[2]; // Integer division operation
   

src/ieu/ieu.sv

@@ -42,6 +42,7 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
   output logic [2:0]        Funct3E,                         // Funct3 instruction field
   output logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE,  // ALU src inputs before the mux choosing between them and PCE to put in srcA/B
   output logic [4:0]        RdE,                             // Destination register
+  output logic              MDUActiveE,                      // Mul/Div instruction being executed
   // Memory stage signals
   input  logic              SquashSCW,                       // Squash store conditional, from LSU
   output logic [1:0]        MemRWM,                          // Read/write control goes to LSU
@@ -100,8 +101,8 @@ module ieu import cvw::*;  #(parameter cvw_t P) (
     .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
     .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, 
     .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, 
-    .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .StallM, .FlushM, .MemRWM,
+    .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE,
-    .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
+    .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
     .RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM,
     .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD);
 

src/mdu/mdu.sv

@@ -33,6 +33,7 @@ module mdu import cvw::*;  #(parameter cvw_t P) (
   input  logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // inputs A and B from IEU forwarding mux output
   input  logic [2:0]        Funct3E, Funct3M,               // type of MDU operation
   input  logic              IntDivE, W64E,                  // Integer division/remainder, and W-type instrutions
+  input  logic              MDUActiveE,                     // Mul/Div instruction being executed
   output logic [P.XLEN-1:0] MDUResultW,                     // multiply/divide result
   output logic              DivBusyE                        // busy signal to stall pipeline in Execute stage
 );
@@ -43,6 +44,12 @@ module mdu import cvw::*;  #(parameter cvw_t P) (
   logic [P.XLEN-1:0]        MDUResultM;                     // result after W truncation
   logic                     W64M;                           // W-type instruction
 
+  logic [P.XLEN-1:0]        AMDU, BMDU;                     // Gated inputs to MDU
+
+  // gate data inputs to MDU to only operate when MDU is active.
+  assign AMDU = ForwardedSrcAE & {P.XLEN{MDUActiveE}};
+  assign BMDU = ForwardedSrcBE & {P.XLEN{MDUActiveE}};
+
   // Multiplier
   mul #(P.XLEN) mul(.clk, .reset, .StallM, .FlushM, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .ProdM);
 

src/wally/wallypipelinedcore.sv

@@ -77,6 +77,7 @@ module wallypipelinedcore import cvw::*;  #(parameter cvw_t P) (
   logic                          DivBusyE;
   logic                          LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
   logic                          SquashSCW;
+  logic                          MDUActiveE;                      // Mul/Div instruction being executed
 
   // floating point unit signals
   logic [2:0]                    FRM_REGW;
@@ -190,7 +191,7 @@ module wallypipelinedcore import cvw::*;  #(parameter cvw_t P) (
      .InstrD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD,
      // Execute Stage interface
      .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
-     .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, 
+     .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE,
      // Memory stage interface
      .SquashSCW,  // from LSU
      .MemRWM,     // read/write control goes to LSU
@@ -306,7 +307,7 @@ module wallypipelinedcore import cvw::*;  #(parameter cvw_t P) (
   if (P.M_SUPPORTED | P.ZMMUL_SUPPORTED) begin:mdu
     mdu #(P) mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
       .ForwardedSrcAE, .ForwardedSrcBE, 
-      .Funct3E, .Funct3M, .IntDivE, .W64E,
+      .Funct3E, .Funct3M, .IntDivE, .W64E, .MDUActiveE,
       .MDUResultW, .DivBusyE); 
   end else begin // no M instructions supported
     assign MDUResultW = 0;