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Modified RAM for single-cycle latency

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This commit is contained in:
David Harris 2022-06-08 02:06:00 +00:00
parent 3c8eafc8ee
commit 5240bd1c90
2 changed files with 34 additions and 42 deletions
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68
pipelined/src/uncore/ram.sv
View File

@ -49,22 +49,24 @@ module ram #(parameter BASE=0, RANGE = 65535) (
// 3. implement burst. // 3. implement burst.
// 4. remove the configurable latency. // 4. remove the configurable latency.
logic [`XLEN/8-1:0] ByteMaskM; logic [`XLEN/8-1:0] ByteMask;
logic [31:0] HWADDR, A; logic [31:0] HADDRD, RamAddr;
logic prevHREADYRam, risingHREADYRam; //logic prevHREADYRam, risingHREADYRam;
logic initTrans; logic initTrans;
logic memwrite; logic memwrite, memwriteD;
logic [3:0] busycount; logic nextHREADYRam;
//logic [3:0] busycount;
swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HWADDR[2:0]), .ByteMask(ByteMaskM)); swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HADDRD[2:0]), .ByteMask(ByteMask));
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00); assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00); // *** add burst support, or disable on busy
assign memwrite = initTrans & HWRITE;
// *** this seems like a weird way to use reset // *** this seems like a weird way to use reset
flopenr #(1) memwritereg(HCLK, 1'b0, initTrans | ~HRESETn, HSELRam & HWRITE, memwrite); flopen #(1) memwritereg(HCLK, initTrans | ~HRESETn, memwrite, memwriteD); // probably drop ~HRESETn in all this
flopenr #(32) haddrreg(HCLK, 1'b0, initTrans | ~HRESETn, HADDR, A); flopen #(32) haddrreg(HCLK, initTrans | ~HRESETn, HADDR, HADDRD);
// busy FSM to extend READY signal /* // busy FSM to extend READY signal
always @(posedge HCLK, negedge HRESETn) always @(posedge HCLK, negedge HRESETn)
if (~HRESETn) begin if (~HRESETn) begin
busycount <= 0; busycount <= 0;
@ -80,48 +82,38 @@ module ram #(parameter BASE=0, RANGE = 65535) (
busycount <= busycount + 1; busycount <= busycount + 1;
end end
end end
end end */
assign nextHREADYRam = ~(memwriteD & ~memwrite);
flopr #(1) readyreg(HCLK, ~HRESETn, nextHREADYRam, HREADYRam);
// assign HREADYRam = ~(memwriteD & ~memwrite);
assign HRESPRam = 0; // OK assign HRESPRam = 0; // OK
localparam ADDR_WDITH = $clog2(RANGE/8); localparam ADDR_WIDTH = $clog2(RANGE/8);
localparam OFFSET = $clog2(`XLEN/8); localparam OFFSET = $clog2(`XLEN/8);
// Rising HREADY edge detector /* // Rising HREADY edge detector
// Indicates when ram is finishing up // Indicates when ram is finishing up
// Needed because HREADY may go high for other reasons, // Needed because HREADY may go high for other reasons,
// and we only want to write data when finishing up. // and we only want to write data when finishing up.
flopenr #(1) prevhreadyRamreg(HCLK,~HRESETn, 1'b1, HREADYRam,prevHREADYRam); flopenr #(1) prevhreadyRamreg(HCLK,~HRESETn, 1'b1, HREADYRam,prevHREADYRam);
assign risingHREADYRam = HREADYRam & ~prevHREADYRam; assign risingHREADYRam = HREADYRam & ~prevHREADYRam;*/
always @(posedge HCLK)
HWADDR <= #1 A;
/*
bram2p1r1w #(`XLEN/8, 8, ADDR_WDITH, `FPGA) bram2p1r1w #(`XLEN/8, 8, ADDR_WDITH, `FPGA)
memory(.clk(HCLK), .reA(1'b1), memory(.clk(HCLK), .reA(1'b1),
.addrA(A[ADDR_WDITH+OFFSET-1:OFFSET]), .doutA(HREADRam), .addrA(A[ADDR_WDITH+OFFSET-1:OFFSET]), .doutA(HREADRam),
.weB(memwrite & risingHREADYRam), .bweB(ByteMaskM), .weB(memwrite & risingHREADYRam), .bweB(ByteMaskM),
.addrB(HWADDR[ADDR_WDITH+OFFSET-1:OFFSET]), .dinB(HWDATA)); .addrB(HWADDR[ADDR_WDITH+OFFSET-1:OFFSET]), .dinB(HWDATA)); */
/*
bram1p1r1w #(`XLEN/8, 8, ADDR_WDITH)
memory(.clk(HCLK), .we(memwrite), .bwe(ByteMaskM), . addr(A***), .dout(HREADRam), .din(HWDATA));
#(
//--------------------------------------------------------------------------
parameter NUM_COL = 8,
parameter COL_WIDTH = 8,
parameter ADDR_WIDTH = 10,
// Addr Width in bits : 2 *ADDR_WIDTH = RAM Depth
parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits
//----------------------------------------------------------------------
) (
input logic clk,
input logic ena,
input logic [NUM_COL-1:0] we,
input logic [ADDR_WIDTH-1:0] addr,
output logic [DATA_WIDTH-1:0] dout,
input logic [DATA_WIDTH-1:0] din
);*/
// On writes, use address delayed by one cycle to sync with HWDATA
mux2 #(32) adrmux(HADDR, HADDRD, memwriteD, RamAddr);
// single-ported RAM
bram1p1rw #(`XLEN/8, 8, ADDR_WIDTH)
memory(.clk(HCLK), .we(memwriteD), .bwe(ByteMask), .addr(RamAddr[ADDR_WIDTH+OFFSET-1:OFFSET]), .dout(HREADRam), .din(HWDATA));
endmodule endmodule

4
pipelined/src/uncore/uncore.sv
View File

@ -92,7 +92,7 @@ module uncore (
// generate // generate
// on-chip RAM // on-chip RAM
if (`RAM_SUPPORTED) begin : ram if (`RAM_SUPPORTED) begin : ram
ram #( ram_orig #(
.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( .BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.HCLK, .HRESETn, .HCLK, .HRESETn,
.HSELRam, .HADDR, .HSELRam, .HADDR,
@ -102,7 +102,7 @@ module uncore (
end end
if (`BOOTROM_SUPPORTED) begin : bootrom if (`BOOTROM_SUPPORTED) begin : bootrom
ram #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE)) ram_orig #(.BASE(`BOOTROM_BASE), .RANGE(`BOOTROM_RANGE))
bootrom( bootrom(
.HCLK, .HRESETn, .HCLK, .HRESETn,
.HSELRam(HSELBootRom), .HADDR, .HSELRam(HSELBootRom), .HADDR,