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Lint cleanup

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This commit is contained in:
David Harris 2021-10-23 09:06:21 -07:00
parent bf3eb7b814
commit 5235e61d9e
3 changed files with 5 additions and 5 deletions
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4
wally-pipelined/src/cache/cachereplacementpolicy.sv vendored
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@ -43,10 +43,11 @@ module cachereplacementpolicy
logic [NUMWAYS-2:0] BlockReplacementBits; logic [NUMWAYS-2:0] BlockReplacementBits;
logic [NUMWAYS-2:0] NewReplacement; logic [NUMWAYS-2:0] NewReplacement;
/* verilator lint_off BLKLOOPINIT */
always_ff @(posedge clk, posedge reset) begin always_ff @(posedge clk, posedge reset) begin
if (reset) begin if (reset) begin
for(int index = 0; index < NUMLINES; index++) for(int index = 0; index < NUMLINES; index++)
ReplacementBits[index] = '0; ReplacementBits[index] <= '0;
end else begin end else begin
BlockReplacementBits <= ReplacementBits[RAdr]; BlockReplacementBits <= ReplacementBits[RAdr];
if (LRUWriteEn) begin if (LRUWriteEn) begin
@ -54,6 +55,7 @@ module cachereplacementpolicy
end end
end end
end end
/* verilator lint_on BLKLOOPINIT */
genvar index; genvar index;

2
wally-pipelined/src/fpu/fma.sv
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@ -804,7 +804,6 @@ module fmaflags(
output logic Invalid, Overflow, Underflow, // flags used to select the result output logic Invalid, Overflow, Underflow, // flags used to select the result
output logic [4:0] FMAFlgM // FMA flags output logic [4:0] FMAFlgM // FMA flags
); );
logic [`NE+1:0] MaxExp; // maximum value of the exponent
logic SigNaN; // is an input a signaling NaN logic SigNaN; // is an input a signaling NaN
logic UnderflowFlag, Inexact; // flags logic UnderflowFlag, Inexact; // flags
@ -819,7 +818,6 @@ module fmaflags(
// 2) Inf - Inf (unless x or y is NaN) // 2) Inf - Inf (unless x or y is NaN)
// 3) 0 * Inf // 3) 0 * Inf
// assign MaxExp = FmtM ? {`NE{1'b1}} : {8{1'b1}};
assign SigNaN = XSNaNM | YSNaNM | ZSNaNM; assign SigNaN = XSNaNM | YSNaNM | ZSNaNM;
assign Invalid = SigNaN | ((XInfM || YInfM) & ZInfM & (PSgnM ^ ZSgnEffM) & ~XNaNM & ~YNaNM) | (XZeroM & YInfM) | (YZeroM & XInfM); assign Invalid = SigNaN | ((XInfM || YInfM) & ZInfM & (PSgnM ^ ZSgnEffM) & ~XNaNM & ~YNaNM) | (XZeroM & YInfM) | (YZeroM & XInfM);

4
wally-pipelined/src/mmu/tlbcontrol.sv
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@ -89,7 +89,7 @@ module tlbcontrol #(parameter ITLB = 0) (
// Check whether the access is allowed, page faulting if not. // Check whether the access is allowed, page faulting if not.
generate generate
if (ITLB == 1) begin if (ITLB == 1) begin // Instruction TLB fault checking
logic ImproperPrivilege; logic ImproperPrivilege;
// User mode may only execute user mode pages, and supervisor mode may // User mode may only execute user mode pages, and supervisor mode may
@ -99,7 +99,7 @@ module tlbcontrol #(parameter ITLB = 0) (
// fault for software handling if access bit is off // fault for software handling if access bit is off
assign DAPageFault = ~PTE_A; assign DAPageFault = ~PTE_A;
assign TLBPageFault = Translate && TLBHit && (ImproperPrivilege || ~PTE_X || DAPageFault || UpperBitsUnequalPageFault); assign TLBPageFault = Translate && TLBHit && (ImproperPrivilege || ~PTE_X || DAPageFault || UpperBitsUnequalPageFault);
end else begin end else begin // Data TLB fault checking
logic ImproperPrivilege, InvalidRead, InvalidWrite; logic ImproperPrivilege, InvalidRead, InvalidWrite;
// User mode may only load/store from user mode pages, and supervisor mode // User mode may only load/store from user mode pages, and supervisor mode