From 5218865a7f0cf87cbd8fb180c290b020b9b4a78d Mon Sep 17 00:00:00 2001 From: slmnemo Date: Tue, 26 Jul 2022 09:14:40 -0700 Subject: [PATCH] Committing changes made to UART test --- .../rv32i_m/privilege/src/WALLY-TEST-LIB-32.h | 1 + .../rv32i_m/privilege/src/WALLY-uart-01.S | 77 ++++++++++++++++--- 2 files changed, 68 insertions(+), 10 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h index e69b54f9d..db123f078 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-TEST-LIB-32.h @@ -1061,6 +1061,7 @@ uart_lsr_intr_loop: lb t3, 0(t2) andi t3, t3, 0x7 bne t3, t4, uart_lsr_intr_loop +uart_save_iir_status: sw t3, 0(t1) addi t1, t1, 4 addi a6, a6, 4 diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S index cf430cb48..603542fde 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-uart-01.S @@ -119,16 +119,16 @@ test_cases: # =========== Transmit-related interrupts =========== -.4byte UART_IER, 0x07, write08_test # enable data available, buffer empty, and line status interrupts -.4byte UART_IIR, 0x02, read08_test # buffer should be empty, causing interrupt -.4byte UART_THR, 0x00, write08_test # write zeroes to transmitter -.4byte 0x0, 0x0401, uart_data_wait # IIR should have data ready interrupt -.4byte UART_THR, 0x01, write08_test # write 1 to transmitter buffer -.4byte UART_IIR, 0x04, read08_test # data interrupt should still be high -.4byte 0x0, 0x06, uart_lsr_intr_wait # wait for transmission to complete, IIR should throw error due to overrun error. -.4byte UART_LSR, 0x63, read08_test # read overrun error from LSR -.4byte UART_IIR, 0x04, read08_test # check that LSR interrupt was cleared -.4byte UART_RBR, 0x01, read08_test # read previous value from UART +.4byte UART_IER, 0x07, write08_test # enable data available, buffer empty, and line status interrupts +.4byte UART_IIR, 0x02, read08_test # buffer should be empty, causing interrupt +.4byte UART_THR, 0x00, write08_test # write zeroes to transmitter +.4byte 0x0, 0x0401, uart_data_wait # IIR should have data ready interrupt +.4byte UART_THR, 0x01, write08_test # write 1 to transmitter buffer +.4byte UART_IIR, 0x04, read08_test # data interrupt should still be high +.4byte 0x0, 0x06, uart_lsr_intr_wait # wait for transmission to complete, IIR should throw error due to overrun error. +.4byte UART_LSR, 0x63, read08_test # read overrun error from LSR +.4byte UART_IIR, 0x04, read08_test # check that LSR interrupt was cleared +.4byte UART_RBR, 0x01, read08_test # read previous value from UART # =========== MODEM interrupts =========== @@ -183,5 +183,62 @@ test_cases: .4byte UART_FCR, 0xC1, read08_test # Check that FCR clears bits 1 and 2 when written to 1 .4byte UART_LSR, 0x60, read08_test # No data ready, FIFO cleared by writing to FCR +# =========== FIFO receiver/overrun =========== + +.4byte UART_FCR, 0x01, write08_test # Set FIFO trigger threshold to 1 and enable FIFO mode +.4byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger level +.4byte UART_THR, 0x00, write08_test # Write 0 to transmit register +.4byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.4byte UART_FCR, 0x41, write08_test # Set FIFO trigger threshold to 4 +.4byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger threshold +.4byte UART_THR, 0x01, write08_test # Write 1 to transmit register +.4byte UART_THR, 0x02, write08_test # Write 2 to transmit register +.4byte 0x0, 0xC101, uart_data_wait # FIFO has not reached trigger threshold +.4byte UART_THR, 0x03, write08_test # Write 3 to transmit register +.4byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.4byte UART_FCR, 0x81, write08_test # Set FIFO trigger threshold to 8 +.4byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger threshold +.4byte UART_THR, 0x04, write08_test # Write 4 to transmit register +.4byte UART_THR, 0x05, write08_test # Write 5 to transmit register +.4byte UART_THR, 0x06, write08_test # Write 6 to transmit register +.4byte 0x0, 0xC101, uart_data_wait # FIFO has not reached trigger threshold +.4byte UART_THR, 0x07, write08_test # Write 7 to transmit register +.4byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.4byte UART_FCR, 0xC1, write08_test # Set FIFO trigger threshold to 14 +.4byte UART_IIR, 0xC1, read08_test # FIFO has not reached trigger threshold +.4byte UART_THR, 0x08, write08_test # Write 8 to transmit register +.4byte UART_THR, 0x09, write08_test # Write 9 to transmit register +.4byte UART_THR, 0x0A, write08_test # Write 10 to transmit register +.4byte UART_THR, 0x0B, write08_test # Write 11 to transmit register +.4byte UART_THR, 0x0C, write08_test # Write 12 to transmit register +.4byte 0x0, 0xC101, uart_data_wait # FIFO has not reached trigger threshold +.4byte UART_THR, 0x0D, write08_test # Write 13 to transmit register +.4byte 0x0, 0xC401, uart_data_wait # Interrupt due to trigger threshold reached +.4byte UART_THR, 0x0E, write08_test # Write 14 to transmit register +.4byte UART_THR, 0x0F, write08_test # Write 15 to transmit register +.4byte 0x0, 0xC401, uart_data_wait +.4byte UART_LSR, 0x61, read08_test # FIFO contains data, no overrun error +.4byte UART_THR, 0x10, write08_test # Write 16 to transmit register, filling RX shift register +.4byte UART_THR, 0x11, write08_test # Write 17 to transmit register, destroying contents held in shift register +.4byte 0x0, 0x06, uart_lsr_intr_wait # Wait for LSR interrupt ID +.4byte UART_LSR, 0x63, read08_test # Read overrun error from LSR +.4byte UART_RBR, 0x00, read08_test # Read 0 from FIFO +.4byte UART_RBR, 0x01, read08_test # Read 1 from FIFO +.4byte UART_THR, 0x12, write08_test # Write 18 to transmit register, showing space in FIFO +.4byte 0x0, 0x0401, uart_data_wait +.4byte UART_RBR, 0x02, read08_test # Read 2 from FIFO +.4byte UART_RBR, 0x03, read08_test # Read 3 from FIFO +.4byte UART_RBR, 0x04, read08_test # Read 4 from FIFO +.4byte UART_RBR, 0x05, read08_test # Read 5 from FIFO +.4byte UART_RBR, 0x06, read08_test # Read 6 from FIFO +.4byte UART_RBR, 0x07, read08_test # Read 7 from FIFO +.4byte UART_RBR, 0x08, read08_test # Read 8 from FIFO +.4byte UART_RBR, 0x09, read08_test # Read 9 from FIFO +.4byte UART_RBR, 0x0A, read08_test # Read 10 from FIFO +.4byte UART_RBR, 0x0B, read08_test # Read 11 from FIFO +.4byte UART_RBR, 0x0C, read08_test # Read 12 from FIFO +.4byte UART_RBR, 0x0D, read08_test # Read 13 from FIFO +.4byte UART_RBR, 0x0E, read08_test # Read 14 from FIFO +.4byte UART_RBR, 0x0F, read08_test # Read 15 from FIFO .4byte 0x0, 0x0, terminate_test \ No newline at end of file