fix up PLIC and UART checkpointing

linux/testvector-generation/parsePlicState.py

@@ -21,20 +21,26 @@ def tokenize(string):
             token = token + char
     return tokens
 
+def stripZeroes(num):
+    num = num.strip('0')
+    if num=='':
+        return '0'
+    else:
+        return num
+
 #############
 # Main Code #
 #############
 print("Begin parsing PLIC state.")
 
 # Parse Args
-if len(sys.argv) != 3:
+if len(sys.argv) != 2:
-    sys.exit('Error parsePlicState.py expects 2 args: <raw GDB state dump> <output state file>')
+    sys.exit('Error parsePlicState.py expects 1 arg: <path_to_checkpoint_dir>')
-rawPlicStateFile=sys.argv[1]
+outDir = sys.argv[1]+'/'
-outPlicStateFile=sys.argv[2]
+rawPlicStateFile = outDir+'plicStateGDB.txt'
 if not os.path.exists(rawPlicStateFile):
     sys.exit('Error input file '+rawPlicStateFile+'not found')
 
-# Main Loop
 with open(rawPlicStateFile, 'r') as rawPlicStateFile:
     plicIntPriorityArray=[]
     # 0x0C000004 thru 0x0C000010
@@ -76,12 +82,14 @@ with open(rawPlicStateFile, 'r') as rawPlicStateFile:
     # 0x0C200000
     plicIntPriorityThreshold = tokenize(rawPlicStateFile.readline())[1:]
 
-with open(outPlicStateFile, 'w') as outPlicStateFile:
+with open(outDir+'checkpoint-PLIC_INT_PRIORITY', 'w') as outFile:
     for word in plicIntPriorityArray:
-        outPlicStateFile.write(word[2:]+'\n')
+        outFile.write(stripZeroes(word[2:])+'\n')
+with open(outDir+'checkpoint-PLIC_INT_ENABLE', 'w') as outFile:
     for word in plicIntEnable:
-        outPlicStateFile.write(word[2:]+'\n')
+        outFile.write(stripZeroes(word[2:]))
+with open(outDir+'checkpoint-PLIC_THRESHOLD', 'w') as outFile:
     for word in plicIntPriorityThreshold:
-        outPlicStateFile.write(word[2:]+'\n')
+        outFile.write(stripZeroes(word[2:])+'\n')
 
 print("Finished parsing PLIC state!")

linux/testvector-generation/parseUartState.py

@@ -27,27 +27,24 @@ def tokenize(string):
 print("Begin parsing UART state.")
 
 # Parse Args
-if len(sys.argv) != 3:
+if len(sys.argv) != 2:
-    sys.exit('Error parseUartState.py expects 2 args: <raw GDB state dump> <output state file>')
+    sys.exit('Error parseUartState.py expects 1 arg: <path_to_checkpoint_dir>')
-rawUartStateFile=sys.argv[1]
+outDir = sys.argv[1]+'/'
-outUartStateFile=sys.argv[2]
+rawUartStateFile = outDir+'uartStateGDB.txt'
 if not os.path.exists(rawUartStateFile):
     sys.exit('Error input file '+rawUartStateFile+'not found')
 
-# Main Loop
 with open(rawUartStateFile, 'r') as rawUartStateFile:
-    with open(outUartStateFile, 'w') as outUartStateFile:
+    uartBytes = []
-        uartBytes = tokenize(rawUartStateFile.readline())[1:]
+    for i in range(0,8):
-        # Stores
+        uartBytes += tokenize(rawUartStateFile.readline())[1:]
-        # 0: RBR / Divisor Latch Low
+with open(outDir+'checkpoint-UART_IER', 'w') as outFile:
-        # 1: IER / Divisor Latch High
+    outFile.write(uartBytes[1][2:])
-        # 2: IIR
+with open(outDir+'checkpoint-UART_LCR', 'w') as outFile:
-        # 3: LCR
+    outFile.write(uartBytes[3][2:])
-        # 4: MCR
+with open(outDir+'checkpoint-UART_MCR', 'w') as outFile:
-        # 5: LSR
+    outFile.write(uartBytes[4][2:])
-        # 6: MSR
+with open(outDir+'checkpoint-UART_SCR', 'w') as outFile:
-        # 7: SCR
+    outFile.write(uartBytes[7][2:])
-        for uartByte in uartBytes:
-            outUartStateFile.write(uartByte[2:]+'\n')
 
 print("Finished parsing UART state!")

pipelined/testbench/testbench-linux.sv

@@ -214,6 +214,15 @@ module testbench;
   `define STATUS_UIE  `CSR_BASE.csrsr.STATUS_UIE
   `define PRIV        dut.core.priv.priv.privmodereg.q
   `define INSTRET     dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[2]
+  `define UART        dut.uncore.uart.uart.u
+  `define UART_IER    `UART.IER
+  `define UART_LCR    `UART.LCR
+  `define UART_MCR    `UART.MCR
+  `define UART_SCR    `UART.SCR
+  `define PLIC        dut.uncore.plic.plic
+  `define PLIC_INT_PRIORITY `PLIC.intPriority
+  `define PLIC_INT_ENABLE   `PLIC.intEn
+  `define PLIC_THRESHOLD    `PLIC.intThreshold
   // Common Macros
   `define checkCSR(CSR) \
     begin \
@@ -301,6 +310,23 @@ module testbench;
   `INIT_CHECKPOINT_VAL(SATP,       [`XLEN-1:0]);
   `INIT_CHECKPOINT_VAL(PRIV,       [1:0]);
   `MAKE_CHECKPOINT_INIT_SIGNAL(MSTATUS, [`XLEN-1:0],0,0);
+  // Many UART registers are difficult to initialize because under the hood
+  // they are not simple registers. Instead some are generated by interesting
+  // combinational blocks such that they depend upon a variety of different
+  // underlying flops. See for example how RBR might be the actual RXBR
+  // register, but it could also just as well be 0 or the tail of the fifo
+  // array.
+  //`INIT_CHECKPOINT_VAL(UART_RBR,   [7:0]);
+  `INIT_CHECKPOINT_VAL(UART_IER,   [7:0]);
+  //`INIT_CHECKPOINT_VAL(UART_IIR,   [7:0]);
+  `INIT_CHECKPOINT_VAL(UART_LCR,   [7:0]);
+  `INIT_CHECKPOINT_VAL(UART_MCR,   [4:0]);
+  //`INIT_CHECKPOINT_VAL(UART_LSR,   [7:0]);
+  //`INIT_CHECKPOINT_VAL(UART_MSR,   [7:0]);
+  `INIT_CHECKPOINT_VAL(UART_SCR,   [7:0]);
+  `INIT_CHECKPOINT_SIMPLE_ARRAY(PLIC_INT_PRIORITY, [2:0],`PLIC_NUM_SRC,1);
+  `INIT_CHECKPOINT_VAL(PLIC_INT_ENABLE, [`PLIC_NUM_SRC:1]);
+  `INIT_CHECKPOINT_VAL(PLIC_THRESHOLD, [2:0]);
 
   integer memFile;
   integer readResult;