Merge branch 'main' of https://github.com/openhwgroup/cvw into rvvi32

config/derivlist.txt

@@ -444,6 +444,7 @@ DCACHE_SUPPORTED    0
 VIRTMEM_SUPPORTED    0
 ZICBOM_SUPPORTED    0
 ZICBOZ_SUPPORTED    0
+ZICCLSM_SUPPORTED    0
 SVPBMT_SUPPORTED    0
 SVNAPOT_SUPPORTED   0
 ZAAMO_SUPPORTED     0
@@ -455,6 +456,7 @@ DCACHE_SUPPORTED    0
 VIRTMEM_SUPPORTED    0
 ZICBOM_SUPPORTED    0
 ZICBOZ_SUPPORTED    0
+ZICCLSM_SUPPORTED    0
 SVPBMT_SUPPORTED    0
 SVNAPOT_SUPPORTED   0
 ZAAMO_SUPPORTED     0

config/rv32gc/coverage.svh

@@ -5,6 +5,9 @@
 // This file is needed in the config subdirectory for each config supporting coverage.
 // It defines which extensions are enabled for that config.
 
+// Define XLEN, used in covergroups
+`define XLEN32 1
+
 // Unprivileged extensions
 `include "RV32I_coverage.svh"
 `include "RV32M_coverage.svh"

config/rv64gc/coverage.svh

@@ -5,6 +5,9 @@
 // This file is needed in the config subdirectory for each config supporting coverage.
 // It defines which extensions are enabled for that config.
 
+// Define XLEN, used in covergroups
+`define XLEN64 1
+
 // Unprivileged extensions
 `include "RV64I_coverage.svh"
 `include "RV64M_coverage.svh"

fpga/constraints/big-debug-spi.xdc

@@ -179,9 +179,9 @@ set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
 connect_debug_port u_ila_0/probe30 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/TransmitRegLoaded}]]
 
 create_debug_port u_ila_0 probe
-set_property port_width 1 [get_debug_ports u_ila_0/probe31]
+set_property port_width 4 [get_debug_ports u_ila_0/probe31]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
-connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/controller/PhaseOneOffset}]]
+connect_debug_port u_ila_0/probe31 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[3]} ]]
 
 create_debug_port u_ila_0 probe
 set_property port_width 1 [get_debug_ports u_ila_0/probe32]
@@ -254,10 +254,6 @@ set_property port_width 4 [get_debug_ports u_ila_0/probe45]
 set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
 connect_debug_port u_ila_0/probe45 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/wptr[3]} ]]
 
-create_debug_port u_ila_0 probe
-set_property port_width 4 [get_debug_ports u_ila_0/probe46]
-set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
-connect_debug_port u_ila_0/probe46 [get_nets [list {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[0]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[1]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[2]} {wallypipelinedsoc/uncoregen.uncore/sdc.sdc/rxFIFO/rptrnext[3]} ]]
 
 
 

src/fpu/fcmp.sv

@@ -75,6 +75,7 @@ module fcmp import cvw::*;  #(parameter cvw_t P) (
         3'b0?1: if (P.ZFA_SUPPORTED) 
                   CmpNV = Zfa ? EitherSNaN : EitherNaN; // fltq,fleq / flt,fle perform CompareQuietLess / CompareSignalingLess differing on when to set invalid
                 else CmpNV = EitherNaN;                 // flt, fle
+        3'b100: CmpNV = 1'b0;
         default: CmpNV = 1'bx;
     endcase
   end 

src/fpu/fround.sv

@@ -146,7 +146,8 @@ module fround import cvw::*;  #(parameter cvw_t P) (
   packoutput #(P) packoutput(W, Fmt, FRound); // pack and NaN-box based on selected format.
 
   // Flags
-  assign FRoundNV = XSNaN;                               // invalid if input is signaling NaN
+  assign FRoundNV = XSNaN;                                       // invalid if input is signaling NaN
-  assign FRoundNX = ZfaFRoundNX & ~EgeNf & (Rp | Tp);    // Inexact if Round or Sticky bit set for FRoundNX instruction
+  assign FRoundNX = ZfaFRoundNX & ~EgeNf & (Rp | Tp) & ~XNaN;    // Inexact if Round or Sticky bit set for FRoundNX instruction
+                                                                 // Note: NX must not be raised if input is invalid
 
 endmodule

testbench/common/wallyTracer.sv

@@ -355,7 +355,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   // Initially connecting the writeback stage signals, but may need to use M stage
   // and gate on ~FlushW.
 
-  assign valid  = InstrValidW & ~StallW & ~reset;
+  assign valid  = ((InstrValidW | TrapW) & ~StallW) & ~reset;
   assign rvvi.clk = clk;
   assign rvvi.valid[0][0]    = valid;
   assign rvvi.order[0][0]    = CSRArray[12'hB02];  // TODO: IMPERAS Should be event order
@@ -692,12 +692,13 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi);
   end
   
   always_ff @(posedge clk) begin
-  if(rvvi.valid[0][0]) begin
+	if(valid) begin
-    if(`STD_LOG) begin
+      if(`STD_LOG) begin
-      $fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName);
+        $fwrite(file, "%016x, %08x, %s\t\t", rvvi.pc_rdata[0][0], rvvi.insn[0][0], instrWName);
-      for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
+        for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin
-        if(rvvi.x_wb[0][0][index2]) begin
+          if(rvvi.x_wb[0][0][index2]) begin
-          $fwrite(file, "rf[%02d] = %016x ", index2, rvvi.x_wdata[0][0][index2]);
+            $fwrite(file, "rf[%02d] = %016x ", index2, rvvi.x_wdata[0][0][index2]);
+          end
         end
       end
       for(index2 = 0; index2 < `NUM_REGS; index2 += 1) begin

tests/coverage/WALLY-init-lib.h

@@ -28,12 +28,6 @@
 // The PMP tests are sensitive to the exact addresses in this code, so unfortunately
 // modifying anything breaks those tests.
 
-// Provides simple firmware services through ecall.  Place argument in a0 and issue ecall:
-//  0: change to user mode
-//  1: change to supervisor mode
-//  3: change to machine mode
-//  4: terminate program
-
 .section .text.init
 .global rvtest_entry_point
 
@@ -134,18 +128,6 @@ write_tohost:
 self_loop:
     j self_loop         # wait
     
-// utility routines
-
-# put a 1 in msb of a0 (position XLEN-1); works for both RV32 and RV64
-setmsb:
-    li a0, 0x80000000   # 1 in bit 31
-    slli a1, a0, 1      # check if register is wider than 31 bits
-    beqz a1, setmsbdone # yes, a0 has 1 in bit 31
-    slli a0, a0, 16     # no: shift a0 to have 1 inn bit 63
-    slli a0, a0, 16     # use two shifts of 16 bits each to be compatible with compiling either RV32 or 64
-setmsbdone:
-    ret                 # return to calller
-
 .section .tohost 
 tohost:                 # write to HTIF
     .dword 0
@@ -157,9 +139,6 @@ begin_signature:
     .fill 6*(XLEN/32),4,0xdeadbeef    # 
 end_signature:
 
-scratch:
-    .fill 4,4,0x0
-
 # Initialize stack with room for 512 bytes
 .bss
     .space 512