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ALU cleanup
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@ -69,7 +69,7 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
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assign LTU = ~Carry;
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// Select appropriate ALU Result
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always_comb begin
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always_comb
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case (ALUSelect)
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3'b000: FullResult = Sum; // add or sub (including address generation)
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3'b001: FullResult = Shift; // sll, sra, or srl
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@ -80,7 +80,6 @@ module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) (
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3'b110: FullResult = A | CondMaskInvB; // or, orn, bset
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3'b111: FullResult = A & CondMaskInvB; // and, bclr
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endcase
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end
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// Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits
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if (WIDTH == 64) assign PreALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult;
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