From 51adf6cba991defdc84dc1610efb80a8ba169196 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 24 Aug 2022 12:35:15 -0500 Subject: [PATCH] Modified the lsu/ifu memory configurations. --- pipelined/config/buildroot/wally-config.vh | 8 +++-- pipelined/config/fpga/wally-config.vh | 8 +++-- pipelined/config/rv32e/wally-config.vh | 8 +++-- pipelined/config/rv32gc/wally-config.vh | 7 ++-- pipelined/config/rv32i/wally-config.vh | 8 +++-- pipelined/config/rv32ic/wally-config.vh | 11 +++--- pipelined/config/rv64BP/wally-config.vh | 7 ++-- pipelined/config/rv64fp/wally-config.vh | 8 +++-- pipelined/config/rv64fpquad/wally-config.vh | 8 +++-- pipelined/config/rv64gc/wally-config.vh | 8 +++-- pipelined/config/rv64i/wally-config.vh | 8 +++-- pipelined/config/rv64ic/wally-config.vh | 12 ++++--- pipelined/config/shared/wally-constants.vh | 5 --- pipelined/src/ieu/controller.sv | 2 +- pipelined/src/ifu/ifu.sv | 17 +++++---- pipelined/src/lsu/lsu.sv | 15 ++++---- pipelined/testbench/testbench.sv | 38 ++++++++++----------- 17 files changed, 106 insertions(+), 72 deletions(-) diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index 383cab5b1..5e5524a28 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -47,10 +47,14 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define DMEM `MEM_CACHE -`define IMEM `MEM_CACHE + +// LSU microarchitectural Features +`define DMEM 0 +`define IROM 0 `define DBUS 1 `define IBUS 1 +`define DCACHE 1 +`define ICACHE 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 1 diff --git a/pipelined/config/fpga/wally-config.vh b/pipelined/config/fpga/wally-config.vh index 2d349c8d9..88d8f5590 100644 --- a/pipelined/config/fpga/wally-config.vh +++ b/pipelined/config/fpga/wally-config.vh @@ -49,10 +49,14 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define DMEM `MEM_CACHE -`define IMEM `MEM_CACHE + +// LSU microarchitectural Features +`define DMEM 0 +`define IROM 0 `define DBUS 1 `define IBUS 1 +`define DCACHE 1 +`define ICACHE 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 1 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 4160957b6..8316c8492 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -49,11 +49,13 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -// *** replace with MEM_BUS -`define DMEM `MEM_NONE -`define IMEM `MEM_NONE +// LSU microarchitectural Features +`define DMEM 0 +`define IROM 0 `define DBUS 1 `define IBUS 1 +`define DCACHE 0 +`define ICACHE 0 `define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 0 `define BIGENDIAN_SUPPORTED 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index f15f15a33..975be6567 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -48,10 +48,13 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define DMEM `MEM_CACHE -`define IMEM `MEM_CACHE +// LSU microarchitectural Features +`define DMEM 0 +`define IROM 0 `define DBUS 1 `define IBUS 1 +`define DCACHE 1 +`define ICACHE 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 1 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 001157a13..2f294c343 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -49,11 +49,13 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -// *** replace with MEM_BUS -`define DMEM `MEM_CACHE -`define IMEM `MEM_CACHE +// LSU microarchitectural Features +`define DMEM 0 +`define IROM 0 `define DBUS 1 `define IBUS 1 +`define DCACHE 1 +`define ICACHE 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 0 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 4fcffd73c..f25d4f9b8 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -48,10 +48,13 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define DMEM `MEM_TIM -`define IMEM `MEM_TIM -`define DBUS 0 -`define IBUS 0 +// LSU microarchitectural Features +`define DMEM 0 +`define IROM 0 +`define DBUS 1 +`define IBUS 1 +`define DCACHE 1 +`define ICACHE 1 `define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 0 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index 53ca026ce..bfedfd33e 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -50,10 +50,13 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define DMEM `MEM_CACHE -`define IMEM `MEM_CACHE +// LSU microarchitectural Features +`define DMEM 0 +`define IROM 0 `define DBUS 1 `define IBUS 1 +`define DCACHE 1 +`define ICACHE 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 0 diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index bf0831d14..5afe6e03e 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -50,10 +50,14 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define DMEM `MEM_CACHE -`define IMEM `MEM_CACHE + +// LSU microarchitectural Features +`define DMEM 0 +`define IROM 0 `define DBUS 1 `define IBUS 1 +`define DCACHE 1 +`define ICACHE 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 1 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index eb8b02662..315f8d072 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -49,10 +49,14 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define DMEM `MEM_CACHE -`define IMEM `MEM_CACHE + +// LSU microarchitectural Features +`define DMEM 0 +`define IROM 0 `define DBUS 1 `define IBUS 1 +`define DCACHE 1 +`define ICACHE 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 1 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 9c9e3376b..0054bef76 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -49,10 +49,14 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define DMEM `MEM_CACHE -`define IMEM `MEM_CACHE + +// LSU microarchitectural Features +`define DMEM 0 +`define IROM 0 `define DBUS 1 `define IBUS 1 +`define DCACHE 1 +`define ICACHE 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 1 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index 99c70cd68..80ae57185 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -49,10 +49,14 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define DMEM `MEM_CACHE -`define IMEM `MEM_CACHE + +// LSU microarchitectural Features +`define DMEM 0 +`define IROM 0 `define DBUS 1 `define IBUS 1 +`define DCACHE 1 +`define ICACHE 1 `define VIRTMEM_SUPPORTED 1 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 0 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index a31a555a5..80521ac7b 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -49,10 +49,14 @@ `define UARCH_PIPELINED 1 `define UARCH_SUPERSCALR 0 `define UARCH_SINGLECYCLE 0 -`define DMEM `MEM_TIM -`define IMEM `MEM_TIM -`define DBUS 0 -`define IBUS 0 + +// LSU microarchitectural Features +`define DMEM 1 +`define IROM 1 +`define DBUS 1 +`define IBUS 1 +`define DCACHE 0 +`define ICACHE 0 `define VIRTMEM_SUPPORTED 0 `define VECTORED_INTERRUPTS_SUPPORTED 1 `define BIGENDIAN_SUPPORTED 0 diff --git a/pipelined/config/shared/wally-constants.vh b/pipelined/config/shared/wally-constants.vh index 4bae2c1b6..c38bc1ed7 100644 --- a/pipelined/config/shared/wally-constants.vh +++ b/pipelined/config/shared/wally-constants.vh @@ -49,8 +49,3 @@ `define SV32 1 `define SV39 8 `define SV48 9 - -`define MEM_NONE 1 -`define MEM_TIM 2 -`define MEM_CACHE 3 - diff --git a/pipelined/src/ieu/controller.sv b/pipelined/src/ieu/controller.sv index cd2246759..d0b1e5fc2 100644 --- a/pipelined/src/ieu/controller.sv +++ b/pipelined/src/ieu/controller.sv @@ -193,7 +193,7 @@ module controller( // Fences // Ordinary fence is presently a nop // FENCE.I flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented - if (`ZIFENCEI_SUPPORTED & (`IMEM == `MEM_CACHE)) begin:fencei + if (`ZIFENCEI_SUPPORTED & `ICACHE) begin:fencei logic FenceID; assign FenceID = FenceD & (Funct3D == 3'b001); // is it a FENCE.I instruction? assign InvalidateICacheD = FenceID; diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv index e699bc576..2eba5a0c3 100644 --- a/pipelined/src/ifu/ifu.sv +++ b/pipelined/src/ifu/ifu.sv @@ -84,7 +84,6 @@ module ifu ( output logic ICacheAccess, output logic ICacheMiss ); - localparam CACHE_ENABLED = `IMEM == `MEM_CACHE; (* mark_debug = "true" *) logic [`XLEN-1:0] PCCorrectE, UnalignedPCNextF, PCNextF; logic BranchMisalignedFaultE; logic PrivilegedChangePCM; @@ -126,7 +125,7 @@ module ifu ( if(`C_SUPPORTED) begin : SpillSupport - spillsupport #(CACHE_ENABLED) spillsupport(.clk, .reset, .StallF, .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF, + spillsupport #(`ICACHE) spillsupport(.clk, .reset, .StallF, .PCF, .PCPlusUpperF, .PCNextF, .InstrRawF, .InstrDAPageFaultF, .IFUCacheBusStallF, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF); end else begin : NoSpillSupport @@ -185,7 +184,7 @@ module ifu ( logic [`XLEN-1:0] AllInstrRawF; assign InstrRawF = AllInstrRawF[31:0]; - if (`IMEM == `MEM_TIM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM + if (`IROM) begin : irom // *** fix up dtim taking PA_BITS rather than XLEN, *** IEUAdr is a bad name. Probably use a ROM rather than DTIM dtim irom(.clk, .reset, .CPUBusy, .LSURWM(2'b10), .IEUAdrM({{(`XLEN-32){1'b0}}, PCPF[31:0]}), .IEUAdrE(PCNextFSpill), .TrapM(1'b0), .WriteDataM(), .ByteMaskM('0), .ReadDataWordM({{(`XLEN-32){1'b0}}, FinalInstrRawF}), .BusStall, .LSUBusWrite(), .LSUBusRead(IFUBusRead), @@ -194,15 +193,15 @@ module ifu ( end if (`IBUS) begin : bus - localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `ICACHE_LINELENINBITS/`XLEN : 1; - localparam integer LINELEN = (CACHE_ENABLED) ? `ICACHE_LINELENINBITS : `XLEN; - localparam integer LOGBWPL = (`DMEM == `MEM_CACHE) ? $clog2(WORDSPERLINE) : 1; + localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1; + localparam integer LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN; + localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1; logic [LINELEN-1:0] ILSUBusBuffer; logic [`PA_BITS-1:0] ICacheBusAdr; logic ICacheBusAck; logic SelUncachedAdr; - busdp #(WORDSPERLINE, LINELEN, LOGBWPL, CACHE_ENABLED) + busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `ICACHE) busdp(.clk, .reset, .LSUBusHRDATA(IFUBusHRDATA), .LSUBusAck(IFUBusAck), .LSUBusInit(IFUBusInit), .LSUBusWrite(), .SelLSUBusWord(), .LSUBusRead(IFUBusRead), .LSUBusSize(), .LSUBurstType(IFUBurstType), .LSUTransType(IFUTransType), .LSUTransComplete(IFUTransComplete), @@ -219,7 +218,7 @@ module ifu ( .s(SelUncachedAdr), .y(AllInstrRawF[31:0])); - if(CACHE_ENABLED) begin : icache + if(`ICACHE) begin : icache cache #(.LINELEN(`ICACHE_LINELENINBITS), .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS), .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0)) @@ -259,7 +258,7 @@ module ifu ( assign PrivilegedChangePCM = RetM | TrapM; mux2 #(`XLEN) pcmux1(.d0(PCNext0F), .d1(PCCorrectE), .s(BPPredWrongE), .y(PCNext1F)); - if(CACHE_ENABLED) + if(`ICACHE) mux2 #(`XLEN) pcmux2(.d0(PCNext1F), .d1(PCBPWrongInvalidate), .s(InvalidateICacheM), .y(PCNext2F)); else assign PCNext2F = PCNext1F; diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv index 5c1eb2270..f0710e06c 100644 --- a/pipelined/src/lsu/lsu.sv +++ b/pipelined/src/lsu/lsu.sv @@ -198,8 +198,8 @@ module lsu ( // The LSU allows both a DTIM and bus with cache. However, the PMA decoding presently // use the same RAM_BASE addresss for both the DTIM and any RAM in the Uncore. - - if (`DMEM == `MEM_TIM) begin : dtim + + if (`DMEM) begin : dtim // *** directly instantiate RAM or ROM here. Instantiate SRAM1P1RW. // Merge SimpleRAM and SRAM1p1rw into one that is good for synthesis and RAM libraries and flops dtim dtim(.clk, .reset, .CPUBusy, .LSURWM, .IEUAdrM, .IEUAdrE, .TrapM, .WriteDataM(LSUWriteDataM), //*** fix the dtim FinalWriteData @@ -208,10 +208,9 @@ module lsu ( .DCacheMiss, .DCacheAccess); end if (`DBUS) begin : bus - localparam CACHE_ENABLED = `DMEM == `MEM_CACHE; - localparam integer WORDSPERLINE = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS/`XLEN : 1; - localparam integer LINELEN = (CACHE_ENABLED) ? `DCACHE_LINELENINBITS : `XLEN; - localparam integer LOGBWPL = (CACHE_ENABLED) ? $clog2(WORDSPERLINE) : 1; + localparam integer WORDSPERLINE = `DCACHE ? `DCACHE_LINELENINBITS/`XLEN : 1; + localparam integer LINELEN = `DCACHE ? `DCACHE_LINELENINBITS : `XLEN; + localparam integer LOGBWPL = `DCACHE ? $clog2(WORDSPERLINE) : 1; logic [LINELEN-1:0] DLSUBusBuffer; logic [`PA_BITS-1:0] DCacheBusAdr; logic DCacheWriteLine; @@ -219,7 +218,7 @@ module lsu ( logic DCacheBusAck; logic [LOGBWPL-1:0] WordCount; - busdp #(WORDSPERLINE, LINELEN, LOGBWPL, CACHE_ENABLED) busdp( + busdp #(WORDSPERLINE, LINELEN, LOGBWPL, `DCACHE) busdp( .clk, .reset, .LSUBusHRDATA, .LSUBusAck, .LSUBusInit, .LSUBusWrite, .LSUBusRead, .LSUBusSize, .LSUBurstType, .LSUTransType, .LSUTransComplete, .WordCount, .SelLSUBusWord, @@ -232,7 +231,7 @@ module lsu ( .s(SelUncachedAdr), .y(ReadDataWordMuxM)); mux2 #(`XLEN) LsuBushwdataMux(.d0(ReadDataWordM[`XLEN-1:0]), .d1(LSUWriteDataM[`XLEN-1:0]), .s(SelUncachedAdr), .y(LSUBusHWDATA)); - if(CACHE_ENABLED) begin : dcache + if(`DCACHE) begin : dcache cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`XLEN), .DCACHE(1)) dcache( .clk, .reset, .CPUBusy, .SelLSUBusWord, .RW(LSURWM), .Atomic(LSUAtomicM), diff --git a/pipelined/testbench/testbench.sv b/pipelined/testbench/testbench.sv index 5df212b52..8390eefcd 100644 --- a/pipelined/testbench/testbench.sv +++ b/pipelined/testbench/testbench.sv @@ -198,9 +198,9 @@ logic [3:0] dummy; else pathname = tvpaths[1]; */ if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; else memfilename = {pathname, tests[test], ".elf.memfile"}; - if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM); + if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM); else $readmemh(memfilename, dut.uncore.ram.ram.memory.RAM); - if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM); + if (`DMEM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM); if (riscofTest) begin ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"}; @@ -291,7 +291,7 @@ logic [3:0] dummy; /* verilator lint_off INFINITELOOP */ while (signature[i] !== 'bx) begin logic [`XLEN-1:0] sig; - if (`DMEM == `MEM_TIM) sig = dut.core.lsu.dtim.dtim.ram.memory.RAM[testadrNoBase+i]; + if (`DMEM) sig = dut.core.lsu.dtim.dtim.ram.memory.RAM[testadrNoBase+i]; else sig = dut.uncore.ram.ram.memory.RAM[testadrNoBase+i]; //$display("signature[%h] = %h sig = %h", i, signature[i], sig); if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin @@ -324,9 +324,9 @@ logic [3:0] dummy; if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"}; else memfilename = {pathname, tests[test], ".elf.memfile"}; //$readmemh(memfilename, dut.uncore.ram.ram.memory.RAM); - if (`IMEM == `MEM_TIM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM); + if (`IROM) $readmemh(memfilename, dut.core.ifu.irom.irom.ram.memory.RAM); else $readmemh(memfilename, dut.uncore.ram.ram.memory.RAM); - if (`DMEM == `MEM_TIM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM); + if (`DMEM) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.memory.RAM); if (riscofTest) begin ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"}; @@ -398,19 +398,19 @@ module riscvassertions; assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)"); assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)"); assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)"); - assert (`DMEM == `MEM_CACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); + assert (`DCACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN"); assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported"); - assert (`FLEN<=`XLEN | `DMEM == `MEM_CACHE) else $error("Wally does not support FLEN > XLEN unleses data cache is supported"); - assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (`DMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`DCACHE_LINELENINBITS >= 128 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); + assert (`FLEN<=`XLEN | `DCACHE) else $error("Wally does not support FLEN > XLEN unleses data cache is supported"); + assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled"); assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size"); - assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (`IMEM != `MEM_CACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); - assert (`ICACHE_LINELENINBITS >= 32 | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); + assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)"); + assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled"); assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size"); - assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (`DMEM != `MEM_CACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); - assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (`IMEM != `MEM_CACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2"); - assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (`IMEM != `MEM_CACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2"); + assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2"); + assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2"); assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2"); assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2"); assert (`RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if RAM_RANGE is less than 56'h07FFFFFF"); @@ -418,11 +418,11 @@ module riscvassertions; assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported"); assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported"); // assert (`MEM_DCACHE == 0 | `MEM_DTIM == 0) else $error("Can't simultaneously have a data cache and TIM"); - assert (`DMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); - assert (`IMEM == `MEM_CACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); + assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache"); + assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache"); //assert (`DMEM == `MEM_CACHE | `DBUS ==0) else $error("Dcache rquires DBUS."); //assert (`IMEM == `MEM_CACHE | `IBUS ==0) else $error("Icache rquires IBUS."); - assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (`DMEM != `MEM_CACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); + assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1"); assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words"); end @@ -443,7 +443,7 @@ module DCacheFlushFSM logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)]; - if(`DMEM == `MEM_CACHE) begin + if(`DCACHE) begin localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;