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Merge branch 'openhwgroup:main' into main

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naichewa 2024-11-08 11:07:29 -08:00 committed by GitHub
commit 515e05ed75
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11 changed files with 25 additions and 78 deletions
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12
config/rv32gc/coverage.svh
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@ -10,13 +10,6 @@
`include "RV32M_coverage.svh" `include "RV32M_coverage.svh"
`include "RV32F_coverage.svh" `include "RV32F_coverage.svh"
`include "RV32D_coverage.svh" `include "RV32D_coverage.svh"
`include "RV32Zba_coverage.svh"
`include "RV32Zbb_coverage.svh"
`include "RV32Zbc_coverage.svh"
`include "RV32Zbs_coverage.svh"
`include "RV32Zbkb_coverage.svh"
`include "RV32Zbkc_coverage.svh"
`include "RV32Zbkx_coverage.svh"
`include "RV32ZfaF_coverage.svh" `include "RV32ZfaF_coverage.svh"
`include "RV32ZfaD_coverage.svh" `include "RV32ZfaD_coverage.svh"
`include "RV32ZfaZfh_coverage.svh" `include "RV32ZfaZfh_coverage.svh"
@ -29,11 +22,6 @@
`include "RV32ZcbZbb_coverage.svh" `include "RV32ZcbZbb_coverage.svh"
`include "RV32Zcf_coverage.svh" `include "RV32Zcf_coverage.svh"
`include "RV32Zcd_coverage.svh" `include "RV32Zcd_coverage.svh"
`include "RV32Zaamo_coverage.svh"
`include "RV32Zalrsc_coverage.svh"
`include "RV32Zknd_coverage.svh"
`include "RV32Zkne_coverage.svh"
`include "RV32Zknh_coverage.svh"
// Privileged extensions // Privileged extensions
`include "ZicsrM_coverage.svh" `include "ZicsrM_coverage.svh"

1
config/rv32gc/imperas.ic
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@ -71,6 +71,7 @@
--override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions --override no_pseudo_inst=T # For code coverage, don't produce pseudoinstructions
--override show_c_prefix=T # Show "c." with compressed instructions
# mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag # mcause and scause only have 4 lsbs of code and 1 msb of interrupt flag
#--override cpu/ecode_mask=0x8000000F # for RV32 #--override cpu/ecode_mask=0x8000000F # for RV32

23
config/rv64gc/coverage.svh
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@ -10,16 +10,9 @@
`include "RV64M_coverage.svh" `include "RV64M_coverage.svh"
`include "RV64F_coverage.svh" `include "RV64F_coverage.svh"
`include "RV64D_coverage.svh" `include "RV64D_coverage.svh"
`include "RV64Zba_coverage.svh"
`include "RV64Zbb_coverage.svh"
`include "RV64Zbc_coverage.svh"
`include "RV64Zbs_coverage.svh"
`include "RV64Zbkb_coverage.svh"
`include "RV64Zbkc_coverage.svh"
`include "RV64Zbkx_coverage.svh"
`include "RV64ZfaF_coverage.svh" `include "RV64ZfaF_coverage.svh"
`include "RV32ZfaD_coverage.svh" `include "RV64ZfaD_coverage.svh"
`include "RV32ZfaZfh_coverage.svh" `include "RV64ZfaZfh_coverage.svh"
`include "RV64ZfhD_coverage.svh" `include "RV64ZfhD_coverage.svh"
`include "RV64Zfh_coverage.svh" `include "RV64Zfh_coverage.svh"
`include "RV64Zicond_coverage.svh" `include "RV64Zicond_coverage.svh"
@ -29,18 +22,6 @@
`include "RV64ZcbZbb_coverage.svh" `include "RV64ZcbZbb_coverage.svh"
`include "RV64ZcbZba_coverage.svh" `include "RV64ZcbZba_coverage.svh"
`include "RV64Zcd_coverage.svh" `include "RV64Zcd_coverage.svh"
`include "RV64Zaamo_coverage.svh"
`include "RV64Zalrsc_coverage.svh"
`include "RV64Zknd_coverage.svh"
`include "RV64Zkne_coverage.svh"
`include "RV64Zknh_coverage.svh"
// Privileged extensions // Privileged extensions
`include "RV64VM_coverage.svh" `include "RV64VM_coverage.svh"

3
config/rv64gc/imperas.ic
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@ -70,6 +70,9 @@
# For code coverage, don't produce pseudoinstructions # For code coverage, don't produce pseudoinstructions
--override no_pseudo_inst=T --override no_pseudo_inst=T
# Show "c." with compressed instructions
--override show_c_prefix=T
# nonratified mnosie register not implemented # nonratified mnosie register not implemented
--override cpu/mnoise_undefined=T --override cpu/mnoise_undefined=T

4
src/fpu/postproc/postprocess.sv
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@ -46,14 +46,14 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
input logic [P.NE+1:0] FmaSe, // the sum's exponent input logic [P.NE+1:0] FmaSe, // the sum's exponent
input logic [P.FMALEN-1:0] FmaSm, // the positive sum input logic [P.FMALEN-1:0] FmaSm, // the positive sum
input logic FmaASticky, // sticky bit that is calculated during alignment input logic FmaASticky, // sticky bit that is calculated during alignment
input logic [$clog2(P.FMALEN+1)-1:0] FmaSCnt, // the normalization shift count input logic [$clog2(P.FMALEN+1)-1:0] FmaSCnt, // the normalization shift count
//divide signals //divide signals
input logic DivSticky, // divider sticky bit input logic DivSticky, // divider sticky bit
input logic [P.NE+1:0] DivUe, // divsqrt exponent input logic [P.NE+1:0] DivUe, // divsqrt exponent
input logic [P.DIVb:0] DivUm, // divsqrt significand input logic [P.DIVb:0] DivUm, // divsqrt significand
// conversion signals // conversion signals
input logic CvtCs, // the result's sign input logic CvtCs, // the result's sign
input logic [P.NE:0] CvtCe, // the calculated expoent input logic [P.NE:0] CvtCe, // the calculated exponent
input logic CvtResSubnormUf, // the convert result is subnormal or underflows input logic CvtResSubnormUf, // the convert result is subnormal or underflows
input logic [P.LOGCVTLEN-1:0] CvtShiftAmt, // how much to shift by input logic [P.LOGCVTLEN-1:0] CvtShiftAmt, // how much to shift by
input logic ToInt, // is fp->int (since it's writting to the integer register) input logic ToInt, // is fp->int (since it's writting to the integer register)

2
tests/coverage/Makefile
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@ -28,7 +28,7 @@ all: $(OBJDUMPS) $(MEMFILES)
# Assemble into object files # Assemble into object files
%.$(OBJEXT): %.$(AEXT) %.$(OBJEXT): %.$(AEXT)
riscv64-unknown-elf-as -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $< riscv64-unknown-elf-as -g -o $@ -march=rv64gqc_zcb_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh_svinval -mabi=lp64 $<
# Preprocess assembly files # Preprocess assembly files
%.$(AEXT): %.$(SRCEXT) WALLY-init-lib.h %.$(AEXT): %.$(SRCEXT) WALLY-init-lib.h

3
tests/coverage/csrwrites.S
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@ -38,6 +38,9 @@ main:
csrrw t1, menvcfg, t0 csrrw t1, menvcfg, t0
csrrw t2, senvcfg, t0 csrrw t2, senvcfg, t0
# Test writing to TIME CSR
csrw time, zero
# testing FIOM with different privilege modes # testing FIOM with different privilege modes
# setting environment config (to both 1 and 0) in each privilege mode # setting environment config (to both 1 and 0) in each privilege mode
csrsi menvcfg, 1 csrsi menvcfg, 1

18
tests/coverage/fround.S
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@ -1,18 +0,0 @@
// fround.s
#include "WALLY-init-lib.h"
# run-elf.bash find this in project description
main:
bseti t0, zero, 14 # turn on FPU
csrs mstatus, t0
# test fround behavior on NaN
li t0, 0x7FC00001
fmv.w.x ft0, t0
fround.s ft1, ft0
j done
.align 10
data_start:

1
tests/coverage/ieu.S
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@ -81,6 +81,7 @@ main:
.word 0xFF00302F // illegal Atomic instruction .word 0xFF00302F // illegal Atomic instruction
.word 0xFF00402F // illegal Atomic instruction .word 0xFF00402F // illegal Atomic instruction
.word 0x00000873 // illegal CSR instruction .word 0x00000873 // illegal CSR instruction
.word 0x31bf1f93 // illegal aes64ksli1 instruction
# Illegal CMO instructions because envcfg is 0 and system is in user Mode # Illegal CMO instructions because envcfg is 0 and system is in user Mode
li a0, 0 li a0, 0

34
tests/coverage/ifu.S
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@ -43,35 +43,23 @@ main:
.hword 0x9C41 // line 134 Illegal compressed instruction .hword 0x9C41 // line 134 Illegal compressed instruction
# Zcb coverage tests # Zcb coverage tests
# could restore assembly language versions when GCC supports Zcb
mv s0, sp mv s0, sp
#c.lbu s1, 0(s0) // exercise c.lbu c.lbu s1, 0(s0) // exercise c.lbu
.hword 0x8004 // c.lbu s1, 0(s0) c.lh s1, 0(s0) // exercise c.lh
#c.lh s1, 0(s0) // exercise c.lh c.lhu s1, 0(s0) // exercise c.lhu
.hword 0x8444 // c.lh s1, 0(s0) c.sb s1, 0(s0) // exercise c.sb
#c.lhu s1, 0(s0) // exercise c.lhu c.sh s1, 0(s0) // exercise c.sh
.hword 0x8404 // c.lhu s1, 0(s0)
#c.sb s1, 0(s0) // exercise c.sb
.hword 0x8804 // c.sb s1, 0(s0)
#c.sh s1, 0(s0) // exercise c.sh
.hword 0x8C04 // c.sh s1, 0(s0)
.hword 0x8C44 // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction .hword 0x8C44 // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction
.hword 0x9C00 // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction .hword 0x9C00 // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction
li s0, 0xFF li s0, 0xFF
# c.zext.b s0 // exercise c.zext.b c.zext.b s0 // exercise c.zext.b
.hword 0x9C61 // c.zext.b s0 c.sext.b s0 // exercise c.sext.b
# c.sext.b s0 // exercise c.sext.b c.zext.h s0 // exercise c.zext.h
.hword 0x9C65 // c.sext.b s0 c.sext.h s0 // exercise c.sext.h
# c.zext.h s0 // exercise c.zext.h c.zext.w s0 // exercise c.zext.w
.hword 0x9C69 // c.zext.h s0 c.not s0 // exercise c.not
# c.sext.h s0 // exercise c.sext.h
.hword 0x9C6D // c.sext.h s0
# c.zext.w s0 // exercise c.zext.w
.hword 0x9C71 // c.zext.w s0
# c.not s0 // exercise c.not
.hword 0x9C75 // c.not s0
.hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else .hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else

2
tests/coverage/priv.S
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@ -304,7 +304,7 @@ sretdone:
li a0, 3 li a0, 3
ecall ecall
# exercise sfence.inval.ir instruction # exercise sfence.inval.ir instruction
.word 0x18100073 sfence.inval.ir
# exercise sret with rs1 not 0 # exercise sret with rs1 not 0
.word 0x102F8073 .word 0x102F8073