From 97ded2cdd96e8e09083a6995cf29cc72dad02b4c Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Thu, 23 Jun 2022 22:59:43 +0000 Subject: [PATCH 1/3] div debug - accounted for 1 bit normalization in exponent calculation --- pipelined/regression/wave-fpu.do | 1 + pipelined/src/fpu/postprocess.sv | 5 +++-- pipelined/src/fpu/round.sv | 4 ++-- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/pipelined/regression/wave-fpu.do b/pipelined/regression/wave-fpu.do index 60835ef67..a58400cca 100644 --- a/pipelined/regression/wave-fpu.do +++ b/pipelined/regression/wave-fpu.do @@ -23,5 +23,6 @@ add wave -group {Divide} -noupdate /testbenchfp/srtradix4/qsel4/* add wave -group {Divide} -noupdate /testbenchfp/srtradix4/otfc4/* add wave -group {Divide} -noupdate /testbenchfp/srtradix4/preproc/* add wave -group {Divide} -noupdate /testbenchfp/srtradix4/divcounter/* +add wave -group {Divide} -noupdate /testbenchfp/srtradix4/expcalc/* add wave -group {Testbench} -noupdate /testbenchfp/* add wave -group {Testbench} -noupdate /testbenchfp/readvectors/* diff --git a/pipelined/src/fpu/postprocess.sv b/pipelined/src/fpu/postprocess.sv index 9138f9dfd..d970fdbce 100644 --- a/pipelined/src/fpu/postprocess.sv +++ b/pipelined/src/fpu/postprocess.sv @@ -94,6 +94,7 @@ module postprocess( logic IntToFp; // is the opperation an int->fp conversion? logic ToInt; // is the opperation an fp->int conversion? logic [`NE+1:0] RoundExp; + logic [`NE:0] CorrDivExp; logic [1:0] NegResMSBS; logic CvtOp; logic FmaOp; @@ -138,7 +139,7 @@ module postprocess( .XZeroM, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn); fmashiftcalc fmashiftcalc(.SumM, .ZExpM, .ProdExpM, .FmaNormCntM, .FmtM, .KillProdM, .ConvNormSumExp, .ZDenormM, .SumZero, .PreResultDenorm, .FmaShiftAmt, .FmaShiftIn); - divshiftcalc divshiftcalc(.Quot, .DivShiftAmt); + divshiftcalc divshiftcalc(.Quot, .DivCalcExpM, .CorrDivExp, .DivShiftAmt); always_comb case(PostProcSelM) @@ -175,7 +176,7 @@ module postprocess( // round to infinity // round to nearest max magnitude - round round(.OutFmt, .FrmM, .Sticky, .AddendStickyM, .ZZeroM, .Plus1, .PostProcSelM, .CvtCalcExpM, .DivCalcExpM, + round round(.OutFmt, .FrmM, .Sticky, .AddendStickyM, .ZZeroM, .Plus1, .PostProcSelM, .CvtCalcExpM, .CorrDivExp, .InvZM, .RoundSgn, .SumExp, .FmaOp, .CvtOp, .CvtResDenormUfM, .CorrShifted, .ToInt, .CvtResUf, .DivOp, .UfPlus1, .FullResExp, .ResFrac, .ResExp, .Round, .RoundAdd, .UfLSBRes, .RoundExp); diff --git a/pipelined/src/fpu/round.sv b/pipelined/src/fpu/round.sv index 1fd471e9d..73395caed 100644 --- a/pipelined/src/fpu/round.sv +++ b/pipelined/src/fpu/round.sv @@ -24,7 +24,7 @@ module round( input logic [`NE+1:0] SumExp, // exponent of the normalized sum input logic RoundSgn, // the result's sign input logic [`NE:0] CvtCalcExpM, // the calculated expoent - input logic [`NE:0] DivCalcExpM, // the calculated expoent + input logic [`NE:0] CorrDivExp, // the calculated expoent output logic UfPlus1, // do you add or subtract on from the result output logic [`NE+1:0] FullResExp, // ResExp with bits to determine sign and overflow output logic [`NF-1:0] ResFrac, // Result fraction @@ -305,7 +305,7 @@ module round( case(PostProcSelM) 2'b10: RoundExp = SumExp; // fma 2'b00: RoundExp = {CvtCalcExpM[`NE], CvtCalcExpM}&{`NE+2{~CvtResDenormUfM|CvtResUf}}; // cvt - 2'b01: RoundExp = {DivCalcExpM[`NE], DivCalcExpM[`NE:0]}; // divide + 2'b01: RoundExp = {CorrDivExp[`NE], CorrDivExp[`NE:0]}; // divide default: RoundExp = 0; endcase From 86cdbd90e67176690fb39dcbc2bc1b8b08ad494f Mon Sep 17 00:00:00 2001 From: Katherine Parry Date: Thu, 23 Jun 2022 23:01:30 +0000 Subject: [PATCH 2/3] forgot a file --- pipelined/src/fpu/divshiftcalc.sv | 15 +++++++++++++++ 1 file changed, 15 insertions(+) create mode 100644 pipelined/src/fpu/divshiftcalc.sv diff --git a/pipelined/src/fpu/divshiftcalc.sv b/pipelined/src/fpu/divshiftcalc.sv new file mode 100644 index 000000000..57022e5ae --- /dev/null +++ b/pipelined/src/fpu/divshiftcalc.sv @@ -0,0 +1,15 @@ +`include "wally-config.vh" + +module divshiftcalc( + input logic [`DIVLEN+2:0] Quot, + input logic [`NE:0] DivCalcExpM, + output logic [$clog2(`NORMSHIFTSZ)-1:0] DivShiftAmt, + output logic [`NE:0] CorrDivExp +); + + assign DivShiftAmt = {{$clog2(`NORMSHIFTSZ)-1{1'b0}}, ~Quot[`DIVLEN+2]}; + // the quotent is in the range [.5,2) + // if the quotent < 1 and not denormal then subtract 1 to account for the normalization shift + assign CorrDivExp = DivCalcExpM - {(`NE)'(0), ~Quot[`DIVLEN+2]}; + +endmodule From dc5f80a3ca7c35e1a772c9c833571ce25c278e32 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Jun 2022 23:16:43 +0000 Subject: [PATCH 3/3] Default value of Drive in Makefile --- synthDC/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/synthDC/Makefile b/synthDC/Makefile index 193153cac..3de666659 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -15,6 +15,7 @@ export MAXCORES ?= 4 # MAXOPT turns on flattening, boundary optimization, and retiming # The output netlist is hard to interpret, but significantly better PPA export MAXOPT ?= 0 +export DRIVE ?= FLOP time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD)