mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Stripped out all signature checking.
Removed multiple tests loop. Only runs 1 test now.
This commit is contained in:
Ross Thompson
parent
8ee80c5d54
commit
5112ffcbc9
@ -30,7 +30,6 @@
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////////////////////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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`include "wally-config.vh"
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`include "tests.vh"
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module testbench;
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module testbench;
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@ -40,17 +39,12 @@ module testbench;
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logic clk;
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logic clk;
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logic reset_ext, reset;
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logic reset_ext, reset;
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parameter SIGNATURESIZE = 5000000;
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int test, i, errors, totalerrors;
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logic [31:0] sig32[0:SIGNATURESIZE];
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logic [`XLEN-1:0] signature[0:SIGNATURESIZE];
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logic [`XLEN-1:0] testadr, testadrNoBase;
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logic [`XLEN-1:0] testadr, testadrNoBase;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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logic [31:0] InstrW;
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string tests[];
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logic [3:0] dummy;
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logic [3:0] dummy;
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logic [`AHBW-1:0] HRDATAEXT;
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic HREADYEXT, HRESPEXT;
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@ -68,77 +62,9 @@ logic [3:0] dummy;
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string ProgramAddrMapFile, ProgramLabelMapFile;
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string ProgramAddrMapFile, ProgramLabelMapFile;
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integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
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integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 };
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logic DCacheFlushDone, DCacheFlushStart;
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logic DCacheFlushDone, DCacheFlushStart;
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logic riscofTest;
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string testName;
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string memfilename, pathname, adrstr;
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flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
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flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW);
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// check assertions for a legal configuration
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riscvassertions riscvassertions();
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// pick tests based on modes supported
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initial begin
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$display("TEST is %s", TEST);
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//tests = '{};
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if (`XLEN == 64) begin // RV64
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case (TEST)
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"arch64i": tests = arch64i;
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"arch64priv": tests = arch64priv;
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"arch64c": if (`C_SUPPORTED)
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if (`ZICSR_SUPPORTED) tests = {arch64c, arch64cpriv};
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else tests = {arch64c};
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"arch64m": if (`M_SUPPORTED) tests = arch64m;
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"arch64f": if (`F_SUPPORTED) tests = arch64f;
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"arch64d": if (`D_SUPPORTED) tests = arch64d;
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"imperas64i": tests = imperas64i;
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"imperas64f": if (`F_SUPPORTED) tests = imperas64f;
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"imperas64d": if (`D_SUPPORTED) tests = imperas64d;
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"imperas64m": if (`M_SUPPORTED) tests = imperas64m;
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"wally64a": if (`A_SUPPORTED) tests = wally64a;
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"imperas64c": if (`C_SUPPORTED) tests = imperas64c;
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else tests = imperas64iNOc;
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"custom": tests = custom;
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"wally64i": tests = wally64i;
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"wally64priv": tests = wally64priv;
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"wally64periph": tests = wally64periph;
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"coremark": tests = coremark;
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"fpga": tests = fpga;
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"ahb" : tests = ahb;
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endcase
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end else begin // RV32
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case (TEST)
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"arch32i": tests = arch32i;
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"arch32priv": tests = arch32priv;
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"arch32c": if (`C_SUPPORTED)
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if (`ZICSR_SUPPORTED) tests = {arch32c, arch32cpriv};
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else tests = {arch32c};
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"arch32m": if (`M_SUPPORTED) tests = arch32m;
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"arch32f": if (`F_SUPPORTED) tests = arch32f;
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"arch32d": if (`D_SUPPORTED) tests = arch32d;
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"imperas32i": tests = imperas32i;
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"imperas32f": if (`F_SUPPORTED) tests = imperas32f;
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"imperas32m": if (`M_SUPPORTED) tests = imperas32m;
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"wally32a": if (`A_SUPPORTED) tests = wally32a;
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"imperas32c": if (`C_SUPPORTED) tests = imperas32c;
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else tests = imperas32iNOc;
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"wally32i": tests = wally32i;
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"wally32e": tests = wally32e;
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"wally32priv": tests = wally32priv;
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"wally32periph": tests = wally32periph;
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"embench": tests = embench;
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"coremark": tests = coremark;
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endcase
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end
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if (tests.size() == 0) begin
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$display("TEST %s not supported in this configuration", TEST);
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$stop;
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end
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end
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string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile;
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integer outputFilePointer;
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logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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logic UARTSin, UARTSout;
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logic UARTSin, UARTSout;
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@ -158,6 +84,41 @@ logic [3:0] dummy;
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integer ResetCount, ResetThreshold;
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integer ResetCount, ResetThreshold;
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logic InReset;
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logic InReset;
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// Imperas look here.
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initial
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begin
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ResetCount = 0;
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ResetThreshold = 2;
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InReset = 1;
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testadr = 0;
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testadrNoBase = 0;
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testName = "rv64i_m/I/src/add-01.S";
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pathname = "../../tests/riscof/work/riscv-arch-test/";
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memfilename = {pathname, testName, "/ref/ref.elf.memfile"};
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if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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else $error("Imperas test bench requires BUS.");
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ProgramAddrMapFile = {pathname, testName, "/ref/ref.elf.objdump.addr"};
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ProgramLabelMapFile = {pathname, testName, "/ref/ref.elf.objdump.lab"};
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// declare memory labels that interest us, the updateProgramAddrLabelArray task will find the addr of each label and fill the array
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// to expand, add more elements to this array and initialize them to zero (also initilaize them to zero at the start of the next test)
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updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
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$display("Read memfile %s", memfilename);
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end
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rvviTrace rvviTrace();
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flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW);
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flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW);
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// check assertions for a legal configuration
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riscvassertions riscvassertions();
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// instantiate device to be tested
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// instantiate device to be tested
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assign GPIOPinsIn = 0;
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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assign UARTSin = 1;
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@ -200,65 +161,6 @@ logic [3:0] dummy;
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InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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// initialize tests
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// initialize tests
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localparam integer MemStartAddr = 0;
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localparam integer MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32);
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initial
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begin
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ResetCount = 0;
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ResetThreshold = 2;
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InReset = 1;
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test = 1;
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totalerrors = 0;
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testadr = 0;
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testadrNoBase = 0;
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// riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests and tests[0] == "2" refers to WallyRiscvArchTests
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riscofTest = tests[0] == "1" | tests[0] == "2";
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// fill memory with defined values to reduce Xs in simulation
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// Quick note the memory will need to be initialized. The C library does not
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// guarantee the initialized reads. For example a strcmp can read 6 byte
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// strings, but uses a load double to read them in. If the last 2 bytes are
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// not initialized the compare results in an 'x' which propagates through
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// the design.
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if (TEST == "coremark")
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for (i=MemStartAddr; i<MemEndAddr; i = i+1)
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dut.uncore.uncore.ram.ram.memory.RAM[i] = 64'h0;
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// read test vectors into memory
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pathname = tvpaths[tests[0].atoi()];
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/* if (tests[0] == `IMPERASTEST)
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pathname = tvpaths[0];
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else pathname = tvpaths[1]; */
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if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
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else memfilename = {pathname, tests[test], ".elf.memfile"};
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if (`FPGA) begin
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string romfilename, sdcfilename;
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romfilename = {"../../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
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sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
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$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
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$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
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// force sdc timers
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force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
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end else begin
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if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
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else if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
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if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
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end
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if (riscofTest) begin
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ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
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ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
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end else begin
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ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
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ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
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end
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// declare memory labels that interest us, the updateProgramAddrLabelArray task will find the addr of each label and fill the array
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// to expand, add more elements to this array and initialize them to zero (also initilaize them to zero at the start of the next test)
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if(!`FPGA) begin
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updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
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$display("Read memfile %s", memfilename);
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end
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end
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// generate clock to sequence tests
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// generate clock to sequence tests
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always
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always
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@ -267,9 +169,6 @@ logic [3:0] dummy;
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// if ($time % 100000 == 0) $display("Time is %0t", $time);
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// if ($time % 100000 == 0) $display("Time is %0t", $time);
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end
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end
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logic [`XLEN-1:0] debugmemoryadr;
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// assign debugmemoryadr = dut.uncore.uncore.ram.ram.memory.RAM[5140];
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// check results
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// check results
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assign reset_ext = InReset;
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assign reset_ext = InReset;
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@ -284,126 +183,13 @@ logic [3:0] dummy;
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ResetCount = 0;
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ResetCount = 0;
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end
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end
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end else begin
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end else begin
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if (TEST == "coremark")
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if(DCacheFlushStart) begin
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if (dut.core.priv.priv.EcallFaultM) begin
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$stop;
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$display("Benchmark: coremark is done.");
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end
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$stop;
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end
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// Termination condition (i.e. we finished running current test)
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if (DCacheFlushDone) begin
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integer begin_signature_addr;
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InReset = 1;
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begin_signature_addr = ProgramAddrLabelArray["begin_signature"];
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if (!begin_signature_addr)
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$display("begin_signature addr not found in %s", ProgramLabelMapFile);
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testadr = ($unsigned(begin_signature_addr))/(`XLEN/8);
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testadrNoBase = (begin_signature_addr - `UNCORE_RAM_BASE)/(`XLEN/8);
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#600; // give time for instructions in pipeline to finish
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if (TEST == "embench") begin
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// Writes contents of begin_signature to .sim.output file
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// this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score
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// also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking
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$display("Embench Benchmark: %s is done.", tests[test]);
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if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"};
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else outputfile = {pathname, tests[test], ".sim.output"};
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outputFilePointer = $fopen(outputfile);
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i = 0;
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while ($unsigned(i) < $unsigned(5'd5)) begin
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$fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]);
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i = i + 1;
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end
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$fclose(outputFilePointer);
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$display("Embench Benchmark: created output file: %s", outputfile);
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end else begin
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// for tests with no self checking mechanism, read .signature.output file and compare to check for errors
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// clear signature to prevent contamination from previous tests
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for(i=0; i<SIGNATURESIZE; i=i+1) begin
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sig32[i] = 'bx;
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end
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if (riscofTest) signame = {pathname, tests[test], "/ref/Reference-sail_c_simulator.signature"};
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else signame = {pathname, tests[test], ".signature.output"};
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// read signature, reformat in 64 bits if necessary
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$readmemh(signame, sig32);
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i = 0;
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while (i < SIGNATURESIZE) begin
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if (`XLEN == 32) begin
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signature[i] = sig32[i];
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i = i+1;
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end else begin
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signature[i/2] = {sig32[i+1], sig32[i]};
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i = i + 2;
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end
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if (i >= 4 & sig32[i-4] === 'bx) begin
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if (i == 4) begin
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i = SIGNATURESIZE+1; // flag empty file
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$display(" Error: empty test file");
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end else i = SIGNATURESIZE; // skip over the rest of the x's for efficiency
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end
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end
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// Check errors
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errors = (i == SIGNATURESIZE+1); // error if file is empty
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i = 0;
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/* verilator lint_off INFINITELOOP */
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while (signature[i] !== 'bx) begin
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logic [`XLEN-1:0] sig;
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if (`DTIM_SUPPORTED) sig = dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
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else if (`UNCORE_RAM_SUPPORTED) sig = dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
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//$display("signature[%h] = %h sig = %h", i, signature[i], sig);
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if (signature[i] !== sig & (signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h",
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tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]);
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$stop;//***debug
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end
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i = i + 1;
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end
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/* verilator lint_on INFINITELOOP */
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if (errors == 0) begin
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$display("%s succeeded. Brilliant!!!", tests[test]);
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end
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else begin
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$display("%s failed with %d errors. :(", tests[test], errors);
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totalerrors = totalerrors+1;
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end
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end
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// move onto the next test, check to see if we're done
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test = test + 1;
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if (test == tests.size()) begin
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if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
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else $display("FAIL: %d test programs had errors", totalerrors);
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$stop;
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end
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else begin
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InitializingMemories = 1;
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|
||||||
// If there are still additional tests to run, read in information for the next test
|
|
||||||
//pathname = tvpaths[tests[0]];
|
|
||||||
if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
|
|
||||||
else memfilename = {pathname, tests[test], ".elf.memfile"};
|
|
||||||
//$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
|
|
||||||
if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
|
|
||||||
else if (`UNCORE_RAM_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
|
|
||||||
if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
|
|
||||||
|
|
||||||
if (riscofTest) begin
|
|
||||||
ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
|
|
||||||
ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
|
|
||||||
end else begin
|
|
||||||
ProgramAddrMapFile = {pathname, tests[test], ".elf.objdump.addr"};
|
|
||||||
ProgramLabelMapFile = {pathname, tests[test], ".elf.objdump.lab"};
|
|
||||||
end
|
|
||||||
ProgramAddrLabelArray = '{ "begin_signature" : 0, "tohost" : 0 };
|
|
||||||
if(!`FPGA) begin
|
|
||||||
updateProgramAddrLabelArray(ProgramAddrMapFile, ProgramLabelMapFile, ProgramAddrLabelArray);
|
|
||||||
$display("Read memfile %s", memfilename);
|
|
||||||
end
|
|
||||||
end
|
|
||||||
end // if (DCacheFlushDone)
|
|
||||||
end
|
end
|
||||||
end // always @ (negedge clk)
|
end // always @ (negedge clk)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
// track the current function or global label
|
// track the current function or global label
|
||||||
if (DEBUG == 1) begin : FunctionName
|
if (DEBUG == 1) begin : FunctionName
|
||||||
FunctionName FunctionName(.reset(reset),
|
FunctionName FunctionName(.reset(reset),
|
||||||
@ -469,7 +255,6 @@ logic [3:0] dummy;
|
|||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
rvviTrace rvviTrace();
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
|
|
||||||
@ -653,55 +438,3 @@ task automatic updateProgramAddrLabelArray;
|
|||||||
$fclose(ProgramAddrMapFP);
|
$fclose(ProgramAddrMapFP);
|
||||||
endtask
|
endtask
|
||||||
|
|
||||||
`define NUM_REGS 32
|
|
||||||
`define NUM_CSRS 4096
|
|
||||||
|
|
||||||
module rvviTrace();
|
|
||||||
|
|
||||||
// wally specific signals
|
|
||||||
logic reset;
|
|
||||||
|
|
||||||
logic [`XLEN-1:0] PCM, PCW;
|
|
||||||
logic [`XLEN-1:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW;
|
|
||||||
logic InstrValidM, InstrValidW;
|
|
||||||
logic StallE, StallM, StallW;
|
|
||||||
logic FlushE, FlushM, FlushW;
|
|
||||||
|
|
||||||
// tracer signals
|
|
||||||
logic clk;
|
|
||||||
logic valid;
|
|
||||||
logic [`XLEN-1:0] insn;
|
|
||||||
logic [`XLEN-1:0 ] pc_rdata;
|
|
||||||
|
|
||||||
assign clk = testbench.dut.clk;
|
|
||||||
assign InstrValidM = testbench.dut.core.ieu.InstrValidM;
|
|
||||||
assign InstrRawD = testbench.dut.core.ifu.InstrRawD;
|
|
||||||
assign PCM = testbench.dut.core.ifu.PCM;
|
|
||||||
assign reset = testbench.reset;
|
|
||||||
assign StallE = testbench.dut.core.StallE;
|
|
||||||
assign StallM = testbench.dut.core.StallM;
|
|
||||||
assign StallW = testbench.dut.core.StallW;
|
|
||||||
assign FlushE = testbench.dut.core.FlushE;
|
|
||||||
assign FlushM = testbench.dut.core.FlushM;
|
|
||||||
assign FlushW = testbench.dut.core.FlushW;
|
|
||||||
|
|
||||||
// pipeline to writeback stage
|
|
||||||
flopenrc #(`XLEN) InstrRawEReg (clk, reset, FlushE, ~StallE, InstrRawD, InstrRawE);
|
|
||||||
flopenrc #(`XLEN) InstrRawMReg (clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);
|
|
||||||
flopenrc #(`XLEN) InstrRawWReg (clk, reset, FlushW, ~StallW, InstrRawM, InstrRawW);
|
|
||||||
flopenrc #(`XLEN) PCWReg (clk, reset, FlushW, ~StallW, PCM, PCW);
|
|
||||||
flopenrc #(1) InstrValidMReg (clk, reset, FlushW, ~StallW, InstrValidM, InstrValidW);
|
|
||||||
|
|
||||||
assign valid = InstrValidW & ~StallW & ~FlushW;
|
|
||||||
assign insn = InstrRawW;
|
|
||||||
assign pc_rdata = PCW;
|
|
||||||
|
|
||||||
always_ff @(posedge clk) begin
|
|
||||||
if(valid) begin
|
|
||||||
$display("PC = %x, insn = %x", pc_rdata, insn);
|
|
||||||
end
|
|
||||||
end
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user