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added working general trap tests to regression

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This commit is contained in:
Kip Macsai-Goren 2022-04-20 06:46:11 +00:00
parent 1f7a95637a
commit 510021af65
8 changed files with 489 additions and 461 deletions
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2
pipelined/testbench/tests.vh
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@ -1472,6 +1472,8 @@ string imperas32f[] = '{
// "rv64i_m/privilege/WALLY-scratch-01", "0040a0", // "rv64i_m/privilege/WALLY-scratch-01", "0040a0",
// "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0", // "rv64i_m/privilege/WALLY-sscratch-s-01", "0040a0",
"rv64i_m/privilege/WALLY-trap-01", "0050a0", "rv64i_m/privilege/WALLY-trap-01", "0050a0",
"rv64i_m/privilege/WALLY-trap-s-01", "0050a0",
"rv64i_m/privilege/WALLY-trap-u-01", "0050a0",
"rv64i_m/privilege/WALLY-MIE-01", "0050a0", "rv64i_m/privilege/WALLY-MIE-01", "0050a0",
"rv64i_m/privilege/WALLY-mtvec-01", "0050a0", "rv64i_m/privilege/WALLY-mtvec-01", "0050a0",
"rv64i_m/privilege/WALLY-stvec-01", "0050a0", "rv64i_m/privilege/WALLY-stvec-01", "0050a0",

2
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/Makefrag
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@ -66,6 +66,8 @@ target_tests_nosim = \
WALLY-PIE-stack-s-01 \ WALLY-PIE-stack-s-01 \
WALLY-trap-sret-01 \ WALLY-trap-sret-01 \
WALLY-trap-01 \ WALLY-trap-01 \
WALLY-trap-s-01 \
WALLY-trap-u-01 \
# Have all 0's in references! # Have all 0's in references!
#WALLY-MEPC \ #WALLY-MEPC \
#WALLY-SEPC \ #WALLY-SEPC \

8
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-01.reference_output
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@ -1014,3 +1014,11 @@ deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef

422
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output
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@ -1,219 +1,209 @@
deadbeef 00000aaa # readback value from writing mie to enable interrupts
deadbeef 00000000
deadbeef 0000000b # Test 5.3.1.4: mcause from ecall going from M mode to S mode
deadbeef 00000000
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 00000000
deadbeef 800003d2 # stval of faulting instruction adress (0x800003d3)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000003 # scause from Breakpoint
deadbeef 00000000
deadbeef 80000404 # stval of breakpoint instruction adress (0x80000404)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000004 # scause from load address misaligned
deadbeef 00000000
deadbeef 8000040d # stval of misaligned address (0x8000040d)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000005 # scause from load access
deadbeef 00000000
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000006 # scause from store misaligned
deadbeef 00000000
deadbeef 80000429 # stval of address with misaligned store instr (0x80000429)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000007 # scause from store access
deadbeef 00000000
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000009 # scause from S mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec01 # value to indicate successful vectoring on s soft interrupt
deadbeef 00000000
deadbeef 00000001 # scause value from s soft interrupt
deadbeef 80000000
deadbeef 00000000 # stval for ssoft interrupt (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec03 # value to indicate successful vectoring on m soft interrupt
deadbeef 00000000
deadbeef 00000003 # scause value from m soft interrupt
deadbeef 80000000
deadbeef 00000000 # stval for msoft interrupt (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec07 # value to indicate successful vectoring on m time interrupt
deadbeef 00000000
deadbeef 00000007 # scause value from m time interrupt
deadbeef 80000000
deadbeef 00000000 # stval for mtime interrupt (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 00000000
deadbeef 00000009 # scause value from s ext interrupt
deadbeef 80000000
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec0b # value to indicate successful vectoring on m ext interrupt
deadbeef 00000000
deadbeef 0000000b # scause value from m ext interrupt
deadbeef 80000000
deadbeef 00000000 # stval for mext interrupt (0x0)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000009 # scause from S mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
deadbeef ffffffff
deadbeef 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
deadbeef 00000000
deadbeef 0000000b # scause from M mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 00000000
deadbeef 800003d2 # stval of faulting instruction adress (0x800003d3)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000003 # scause from Breakpoint
deadbeef 00000000
deadbeef 80000404 # stval of breakpoint instruction adress (0x80000404)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000004 # scause from load address misaligned
deadbeef 00000000
deadbeef 8000040d # stval of misaligned address (0x8000040d)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000005 # scause from load access
deadbeef 00000000
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000006 # scause from store misaligned
deadbeef 00000000
deadbeef 80000429 # stval of address with misaligned store instr (0x80000429)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000007 # scause from store access
deadbeef 00000000
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000009 # scause from S mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 0007ec01 # value to indicate successful vectoring on s soft interrupt
deadbeef 00000000
deadbeef 00000001 # scause value from s soft interrupt
deadbeef 80000000
deadbeef 00000000 # stval for ssoft interrupt (0x0)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 00000000
deadbeef 00000009 # scause value from s ext interrupt
deadbeef 80000000
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000009 # scause from S mode ecall from test termination
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000120 # masked out sstatus.SPP = 1, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

356
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-u-01.reference_output
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@ -1,181 +1,181 @@
deadbeef 00000aaa # readback value from writing mie to enable interrupts
deadbeef 00000000
deadbeef 0000000b # Test 5.3.1.4: mcause from ecall going from M mode to U mode
deadbeef 00000000
deadbeef 00000000 # mtval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 00000000
deadbeef 800003d2 # stval of faulting instruction adress (0x800003d3)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000003 # scause from Breakpoint
deadbeef 00000000
deadbeef 80000404 # stval of breakpoint instruction adress (0x80000404)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000004 # scause from load address misaligned
deadbeef 00000000
deadbeef 8000040d # stval of misaligned address (0x8000040d)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000005 # scause from load access
deadbeef 00000000
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000006 # scause from store misaligned
deadbeef 00000000
deadbeef 80000429 # stval of address with misaligned store instr (0x80000429)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000007 # scause from store access
deadbeef 00000000
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec03 # value to indicate successful vectoring on m soft interrupt
deadbeef 00000000
deadbeef 00000003 # scause value from m soft interrupt
deadbeef 80000000
deadbeef 00000000 # stval for msoft interrupt (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec07 # value to indicate successful vectoring on m time interrupt
deadbeef 00000000
deadbeef 00000007 # scause value from m time interrupt
deadbeef 80000000
deadbeef 00000000 # stval for mtime interrupt (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 00000000
deadbeef 00000009 # scause value from s ext interrupt
deadbeef 80000000
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 0007ec0b # value to indicate successful vectoring on m ext interrupt
deadbeef 00000000
deadbeef 0000000b # scause value from m ext interrupt
deadbeef 80000000
deadbeef 00000000 # stval for mext interrupt (0x0)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000000 # masked out mstatus.mpp = 0, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef fffff7ff # medeleg after attempted write of all 1's (only some bits are writeable)
deadbeef ffffffff
deadbeef 00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
deadbeef 00000000
deadbeef 0000000b # scause from M mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00001800 # masked out mstatus.MPP = 11, mstatus.MPIE = 0, and mstatus.MIE = 0
deadbeef 00000000
deadbeef 00000000 # scause from instruction addr misaligned fault
deadbeef 00000000
deadbeef 800003d2 # stval of faulting instruction adress (0x800003d3)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000001 # scause from an instruction access fault
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction address (0x0)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000002 # scause from an Illegal instruction
deadbeef 00000000
deadbeef 00000000 # stval of faulting instruction (0x0)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000003 # scause from Breakpoint
deadbeef 00000000
deadbeef 80000404 # stval of breakpoint instruction adress (0x80000404)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000004 # scause from load address misaligned
deadbeef 00000000
deadbeef 8000040d # stval of misaligned address (0x8000040d)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000005 # scause from load access
deadbeef 00000000
deadbeef 00000000 # stval of accessed adress (0x0)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000006 # scause from store misaligned
deadbeef 00000000
deadbeef 80000429 # stval of address with misaligned store instr (0x80000429)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000007 # scause from store access
deadbeef 00000000
deadbeef 00000000 # stval of accessed address (0x0)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000008 # scause from U mode ecall
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 0007ec09 # value to indicate successful vectoring on s ext interrupt
deadbeef 00000000
deadbeef 00000009 # scause value from s ext interrupt
deadbeef 80000000
deadbeef 00000000 # stval for sext interrupt (0x0)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef 00000008 # scause from U mode ecall from test termination
deadbeef 00000000
deadbeef 00000000 # stval of ecall (*** defined to be zero for now)
deadbeef 00000000
deadbeef 00000020 # masked out sstatus.SPP = 0, sstatus.SPIE = 1, and sstatus.SIE = 0
deadbeef 00000000
deadbeef deadbeef
deadbeef deadbeef
deadbeef deadbeef

10
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S
View File

@ -52,12 +52,10 @@ jal cause_s_soft_interrupt
jal cause_m_soft_interrupt jal cause_m_soft_interrupt
jal cause_s_time_interrupt jal cause_s_time_interrupt
jal cause_m_time_interrupt jal cause_m_time_interrupt
//jal cause_s_ext_interrupt_GPIO jal cause_s_ext_interrupt_GPIO
jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO.
jal cause_m_ext_interrupt jal cause_m_ext_interrupt
// try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode // try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
@ -77,8 +75,10 @@ jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire si
jal cause_m_soft_interrupt jal cause_m_soft_interrupt
jal cause_s_time_interrupt jal cause_s_time_interrupt
jal cause_m_time_interrupt jal cause_m_time_interrupt
//jal cause_s_ext_interrupt_GPIO li a3, 0x40 // these interrupts involve a time loop waiting for the interrupt to go off.
jal cause_s_ext_interrupt_IP // cause external interrupt with both sip register and GPIO. // since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3
jal cause_s_ext_interrupt_GPIO
li a3, 0x40
jal cause_m_ext_interrupt jal cause_m_ext_interrupt

76
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S
View File

@ -25,34 +25,42 @@
INIT_TESTS INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.4 Basic trap tests // test 5.3.1.4 Basic trap tests
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps TRAP_HANDLER m, DEBUG=1 // necessary to handle switching privilege modes
TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
// Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg // Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1
WRITE_READ_CSR mie, 0xFFFF // sie is a subset of mie, so writing this also enables sie.
GOTO_S_MODE GOTO_S_MODE
li x28, 0x8 jal cause_instr_addr_misaligned
csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode jal cause_instr_access
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts jal cause_illegal_instr
jal cause_breakpnt
jal cause_load_addr_misaligned
jal cause_load_acc
jal cause_store_addr_misaligned
jal cause_store_acc
GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_s_soft_interrupt
CAUSE_INSTR_ACCESS jal cause_m_soft_interrupt
CAUSE_ILLEGAL_INSTR //jal cause_s_time_interrupt // *** S time interrupts cannot come from S mode as of 4/19/22.
CAUSE_BREAKPNT jal cause_m_time_interrupt
CAUSE_LOAD_ADDR_MISALIGNED li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
CAUSE_LOAD_ACC // since interrupts are not always enabled,
CAUSE_STORE_ADDR_MISALIGNED jal cause_s_ext_interrupt_GPIO
CAUSE_STORE_ACC li a3, 0x40
CAUSE_ECALL jal cause_m_ext_interrupt
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
// We can tell which one becuase the different trap handler modes write different bits of the status register // We can tell which one becuase the different trap handler modes write different bits of the status register
@ -63,21 +71,27 @@ GOTO_M_MODE // so we can write the delegate registers
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
GOTO_S_MODE GOTO_S_MODE // Since we're running in M mode, this ecall will NOT be delegated to S mode
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_instr_addr_misaligned
CAUSE_INSTR_ACCESS jal cause_instr_access
CAUSE_ILLEGAL_INSTR jal cause_illegal_instr
CAUSE_BREAKPNT jal cause_breakpnt
CAUSE_LOAD_ADDR_MISALIGNED jal cause_load_addr_misaligned
CAUSE_LOAD_ACC jal cause_load_acc
CAUSE_STORE_ADDR_MISALIGNED jal cause_store_addr_misaligned
CAUSE_STORE_ACC jal cause_store_acc
CAUSE_ECALL GOTO_U_MODE // Causes S mode ecall
GOTO_S_MODE // Causes U mode ecall
jal cause_s_soft_interrupt // *** M mode Interrupts cannot be delegated in this implementation
//jal cause_m_soft_interrupt
//jal cause_s_time_interrupt
//jal cause_m_time_interrupt
li a3, 0x40
jal cause_s_ext_interrupt_GPIO
//jal cause_m_ext_interrupt
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
END_TESTS END_TESTS

72
tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-u-01.S
View File

@ -25,6 +25,8 @@
INIT_TESTS INIT_TESTS
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
// test 5.3.1.4 Basic trap tests // test 5.3.1.4 Basic trap tests
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
@ -32,27 +34,31 @@ TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
// Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg // Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg
li x28, 0x2
csrs sstatus, x28 // set sstatus.SIE bit to 1. Not strictly necessary but this lets us differentiate which trap handler we went to
WRITE_READ_CSR mie, 0xFFFF
GOTO_U_MODE GOTO_U_MODE
// li x28, 0x8 jal cause_instr_addr_misaligned
// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode jal cause_instr_access
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts jal cause_illegal_instr
jal cause_breakpnt
jal cause_load_addr_misaligned
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_load_acc
CAUSE_INSTR_ACCESS jal cause_store_addr_misaligned
CAUSE_ILLEGAL_INSTR jal cause_store_acc
CAUSE_BREAKPNT jal cause_ecall
CAUSE_LOAD_ADDR_MISALIGNED
CAUSE_LOAD_ACC
CAUSE_STORE_ADDR_MISALIGNED
CAUSE_STORE_ACC
CAUSE_ECALL
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
//jal cause_s_soft_interrupt // *** writing SIP from u mode is illegal
jal cause_m_soft_interrupt
//jal cause_s_time_interrupt // *** S time interrupts cannot come from U mode as of 4/19/22.
jal cause_m_time_interrupt
li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off.
// since interrupts are not always enabled,
jal cause_s_ext_interrupt_GPIO
li a3, 0x40
jal cause_m_ext_interrupt
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler // Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
// We can tell which one becuase the different trap handler modes write different bits of the status register // We can tell which one becuase the different trap handler modes write different bits of the status register
@ -65,19 +71,25 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
GOTO_U_MODE GOTO_U_MODE
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled) jal cause_instr_addr_misaligned
CAUSE_INSTR_ACCESS jal cause_instr_access
CAUSE_ILLEGAL_INSTR jal cause_illegal_instr
CAUSE_BREAKPNT jal cause_breakpnt
CAUSE_LOAD_ADDR_MISALIGNED jal cause_load_addr_misaligned
CAUSE_LOAD_ACC jal cause_load_acc
CAUSE_STORE_ADDR_MISALIGNED jal cause_store_addr_misaligned
CAUSE_STORE_ACC jal cause_store_acc
CAUSE_ECALL jal cause_ecall
//jal cause_s_soft_interrupt // *** S Soft interrupts cannot be caused from u mode since writing SIP is illegal
// *** M mode Interrupts cannot be delegated in this implementation
//jal cause_m_soft_interrupt
//jal cause_s_time_interrupt
//jal cause_m_time_interrupt
li a3, 0x40
jal cause_s_ext_interrupt_GPIO
//jal cause_m_ext_interrupt
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
// CAUSE_EXT_INTERRUPT
END_TESTS END_TESTS