csr & wally cleanup

pipelined/src/wally/wallypipelinedcore.sv

@@ -52,11 +52,11 @@ module wallypipelinedcore (
   logic                          RetM;
   (* mark_debug = "true" *) logic TrapM;
 
-  // new signals that must connect through DP
+  //  signals that must connect through DP
   logic                          IntDivE, W64E;
   logic                          CSRReadM, CSRWriteM, PrivilegedM;
   logic [1:0]                    AtomicM;
-  logic [`XLEN-1:0]     ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE;
+  logic [`XLEN-1:0]              ForwardedSrcAE, ForwardedSrcBE;
 (* mark_debug = "true" *)  logic [`XLEN-1:0]         SrcAM;
   logic [2:0]                    Funct3E;
   logic [31:0]                   InstrD;
@@ -78,6 +78,7 @@ module wallypipelinedcore (
   logic                          DivBusyE;
   logic                          LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
   logic                          SquashSCW;
+
   // floating point unit signals
   logic [2:0]                    FRM_REGW;
   logic [4:0]                    RdE, RdM, RdW;
@@ -116,8 +117,6 @@ module wallypipelinedcore (
   logic                          IFUStallF;
   logic                          LSUStallM;
 
-  
-
   // cpu lsu interface
   logic [2:0]                    Funct3M;
   logic [`XLEN-1:0]              IEUAdrE;
@@ -162,6 +161,7 @@ module wallypipelinedcore (
   logic                          FCvtIntE;
   logic                          CommittedF;
   
+  // instruction fetch unit: PC, branch prediction, instruction cache
   ifu ifu(
     .clk, .reset,
     .StallF, .StallD, .StallE, .StallM, .StallW,
@@ -197,10 +197,9 @@ module wallypipelinedcore (
     // pmp/pma (inside mmu) signals.  *** temporarily from AHB bus but eventually replace with internal versions pre H
     .PMPCFG_ARRAY_REGW,  .PMPADDR_ARRAY_REGW,
     .InstrAccessFaultF,
-    .InstrDAPageFaultF
-      
-      ); // instruction fetch unit: PC, branch prediction, instruction cache
+    .InstrDAPageFaultF); 
     
+  // integer execution unit: integer register file, datapath and controller
   ieu ieu(
      .clk, .reset,
 
@@ -235,9 +234,7 @@ module wallypipelinedcore (
      .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD,
      .PCSrcE,
      .CSRReadM, .CSRWriteM, .PrivilegedM,
-     .CSRWriteFenceM, .StoreStallD
-
-  ); // integer execution unit: integer register file, datapath and controller
+     .CSRWriteFenceM, .StoreStallD); 
 
   lsu lsu(
     .clk, .reset, .StallM, .FlushM, .StallW,
@@ -279,10 +276,7 @@ module wallypipelinedcore (
     .InstrDAPageFaultF,
     
     .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
-    .LSUStallM);                     // change to LSUStallM
-
-
-   // *** Ross: please make EBU conditional when only supporting internal memories
+    .LSUStallM);                    
 
   if(`BUS) begin : ebu
     ebu ebu(// IFU connections
@@ -306,10 +300,9 @@ module wallypipelinedcore (
       .HREADY, .HRESP, .HCLK, .HRESETn,
       .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
       .HPROT, .HTRANS, .HMASTLOCK);
-    
   end
 
-  
+  // global stall and flush control  
   hazard  hzu(
     .BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM,
     .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
@@ -320,9 +313,9 @@ module wallypipelinedcore (
     .WFIStallM,
     // Stall & flush outputs
     .StallF, .StallD, .StallE, .StallM, .StallW,
-    .FlushD, .FlushE, .FlushM, .FlushW
-     );    // global stall and flush control
+    .FlushD, .FlushE, .FlushM, .FlushW);    
 
+  // privileged unit
   if (`ZICSR_SUPPORTED) begin:priv
     privileged priv(
       .clk, .reset,
@@ -344,16 +337,12 @@ module wallypipelinedcore (
       .MTIME_CLINT, 
       .IEUAdrM,
       .SetFflagsM,
-         // Trap signals from pmp/pma in mmu
-         // *** do these need to be split up into one for dmem and one for ifu?
-         // instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem?
       .InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
       .IllegalFPUInstrM,
       .PrivilegeModeW, .SATP_REGW,
       .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
       .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, 
-         .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM
-      );
+      .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM);
   end else begin
     assign CSRReadValW = 0;
     assign UnalignedPCNextF = PCNext2F;
@@ -363,19 +352,20 @@ module wallypipelinedcore (
     assign sfencevmaM = 0;
     assign BigEndianM = 0;
   end
+
+  // multiply/divide unit
   if (`M_SUPPORTED) begin:mdu
-      mdu mdu(
-         .clk, .reset,
+    mdu mdu(.clk, .reset,
       .ForwardedSrcAE, .ForwardedSrcBE, 
       .Funct3E, .Funct3M, .IntDivE, .W64E,
       .MDUResultW, .DivBusyE,  
-         .StallM, .StallW, .FlushE, .FlushM, .FlushW
-      ); 
+      .StallM, .StallW, .FlushE, .FlushM, .FlushW); 
   end else begin // no M instructions supported
     assign MDUResultW = 0; 
     assign DivBusyE = 0;
   end
 
+  // floating point unit
   if (`F_SUPPORTED) begin:fpu
     fpu fpu(
       .clk, .reset,
@@ -401,8 +391,7 @@ module wallypipelinedcore (
       .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
       .IllegalFPUInstrM, // Is the instruction an illegal fpu instruction
       .SetFflagsM,        // FPU flags (to privileged unit)
-         .FIntDivResultW
-      ); // floating point unit
+      .FIntDivResultW); 
   end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
     assign FPUStallD = 0;
     assign FWriteIntE = 0;