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csr & wally cleanup

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This commit is contained in:
David Harris 2023-01-13 22:25:19 -08:00
parent 53d0d28828
commit 50fae76207
1 changed files with 240 additions and 251 deletions
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47
pipelined/src/wally/wallypipelinedcore.sv
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@ -52,11 +52,11 @@ module wallypipelinedcore (
logic RetM; logic RetM;
(* mark_debug = "true" *) logic TrapM; (* mark_debug = "true" *) logic TrapM;
// new signals that must connect through DP // signals that must connect through DP
logic IntDivE, W64E; logic IntDivE, W64E;
logic CSRReadM, CSRWriteM, PrivilegedM; logic CSRReadM, CSRWriteM, PrivilegedM;
logic [1:0] AtomicM; logic [1:0] AtomicM;
logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE; //, SrcAE, SrcBE; logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE;
(* mark_debug = "true" *) logic [`XLEN-1:0] SrcAM; (* mark_debug = "true" *) logic [`XLEN-1:0] SrcAM;
logic [2:0] Funct3E; logic [2:0] Funct3E;
logic [31:0] InstrD; logic [31:0] InstrD;
@ -78,6 +78,7 @@ module wallypipelinedcore (
logic DivBusyE; logic DivBusyE;
logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD;
logic SquashSCW; logic SquashSCW;
// floating point unit signals // floating point unit signals
logic [2:0] FRM_REGW; logic [2:0] FRM_REGW;
logic [4:0] RdE, RdM, RdW; logic [4:0] RdE, RdM, RdW;
@ -116,8 +117,6 @@ module wallypipelinedcore (
logic IFUStallF; logic IFUStallF;
logic LSUStallM; logic LSUStallM;
// cpu lsu interface // cpu lsu interface
logic [2:0] Funct3M; logic [2:0] Funct3M;
logic [`XLEN-1:0] IEUAdrE; logic [`XLEN-1:0] IEUAdrE;
@ -162,6 +161,7 @@ module wallypipelinedcore (
logic FCvtIntE; logic FCvtIntE;
logic CommittedF; logic CommittedF;
// instruction fetch unit: PC, branch prediction, instruction cache
ifu ifu( ifu ifu(
.clk, .reset, .clk, .reset,
.StallF, .StallD, .StallE, .StallM, .StallW, .StallF, .StallD, .StallE, .StallM, .StallW,
@ -197,10 +197,9 @@ module wallypipelinedcore (
// pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H // pmp/pma (inside mmu) signals. *** temporarily from AHB bus but eventually replace with internal versions pre H
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.InstrAccessFaultF, .InstrAccessFaultF,
.InstrDAPageFaultF .InstrDAPageFaultF);
); // instruction fetch unit: PC, branch prediction, instruction cache
// integer execution unit: integer register file, datapath and controller
ieu ieu( ieu ieu(
.clk, .reset, .clk, .reset,
@ -235,9 +234,7 @@ module wallypipelinedcore (
.FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD, .FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD,
.PCSrcE, .PCSrcE,
.CSRReadM, .CSRWriteM, .PrivilegedM, .CSRReadM, .CSRWriteM, .PrivilegedM,
.CSRWriteFenceM, .StoreStallD .CSRWriteFenceM, .StoreStallD);
); // integer execution unit: integer register file, datapath and controller
lsu lsu( lsu lsu(
.clk, .reset, .StallM, .FlushM, .StallW, .clk, .reset, .StallM, .FlushM, .StallW,
@ -279,10 +276,7 @@ module wallypipelinedcore (
.InstrDAPageFaultF, .InstrDAPageFaultF,
.PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW, .PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
.LSUStallM); // change to LSUStallM .LSUStallM);
// *** Ross: please make EBU conditional when only supporting internal memories
if(`BUS) begin : ebu if(`BUS) begin : ebu
ebu ebu(// IFU connections ebu ebu(// IFU connections
@ -306,10 +300,9 @@ module wallypipelinedcore (
.HREADY, .HRESP, .HCLK, .HRESETn, .HREADY, .HRESP, .HCLK, .HRESETn,
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST,
.HPROT, .HTRANS, .HMASTLOCK); .HPROT, .HTRANS, .HMASTLOCK);
end end
// global stall and flush control
hazard hzu( hazard hzu(
.BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM, .BPPredWrongE, .CSRWriteFenceM, .RetM, .TrapM,
.LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD, .LoadStallD, .StoreStallD, .MDUStallD, .CSRRdStallD,
@ -320,9 +313,9 @@ module wallypipelinedcore (
.WFIStallM, .WFIStallM,
// Stall & flush outputs // Stall & flush outputs
.StallF, .StallD, .StallE, .StallM, .StallW, .StallF, .StallD, .StallE, .StallM, .StallW,
.FlushD, .FlushE, .FlushM, .FlushW .FlushD, .FlushE, .FlushM, .FlushW);
); // global stall and flush control
// privileged unit
if (`ZICSR_SUPPORTED) begin:priv if (`ZICSR_SUPPORTED) begin:priv
privileged priv( privileged priv(
.clk, .reset, .clk, .reset,
@ -344,16 +337,12 @@ module wallypipelinedcore (
.MTIME_CLINT, .MTIME_CLINT,
.IEUAdrM, .IEUAdrM,
.SetFflagsM, .SetFflagsM,
// Trap signals from pmp/pma in mmu
// *** do these need to be split up into one for dmem and one for ifu?
// instead, could we only care about the instr and F pins that come from ifu and only care about the load/store and m pins that come from dmem?
.InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW, .InstrAccessFaultF, .HPTWInstrAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .SelHPTW,
.IllegalFPUInstrM, .IllegalFPUInstrM,
.PrivilegeModeW, .SATP_REGW, .PrivilegeModeW, .SATP_REGW,
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .STATUS_FS,
.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW, .PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
.FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM .FRM_REGW,.BreakpointFaultM, .EcallFaultM, .WFIStallM, .BigEndianM);
);
end else begin end else begin
assign CSRReadValW = 0; assign CSRReadValW = 0;
assign UnalignedPCNextF = PCNext2F; assign UnalignedPCNextF = PCNext2F;
@ -363,19 +352,20 @@ module wallypipelinedcore (
assign sfencevmaM = 0; assign sfencevmaM = 0;
assign BigEndianM = 0; assign BigEndianM = 0;
end end
// multiply/divide unit
if (`M_SUPPORTED) begin:mdu if (`M_SUPPORTED) begin:mdu
mdu mdu( mdu mdu(.clk, .reset,
.clk, .reset,
.ForwardedSrcAE, .ForwardedSrcBE, .ForwardedSrcAE, .ForwardedSrcBE,
.Funct3E, .Funct3M, .IntDivE, .W64E, .Funct3E, .Funct3M, .IntDivE, .W64E,
.MDUResultW, .DivBusyE, .MDUResultW, .DivBusyE,
.StallM, .StallW, .FlushE, .FlushM, .FlushW .StallM, .StallW, .FlushE, .FlushM, .FlushW);
);
end else begin // no M instructions supported end else begin // no M instructions supported
assign MDUResultW = 0; assign MDUResultW = 0;
assign DivBusyE = 0; assign DivBusyE = 0;
end end
// floating point unit
if (`F_SUPPORTED) begin:fpu if (`F_SUPPORTED) begin:fpu
fpu fpu( fpu fpu(
.clk, .reset, .clk, .reset,
@ -401,8 +391,7 @@ module wallypipelinedcore (
.FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) .FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage)
.IllegalFPUInstrM, // Is the instruction an illegal fpu instruction .IllegalFPUInstrM, // Is the instruction an illegal fpu instruction
.SetFflagsM, // FPU flags (to privileged unit) .SetFflagsM, // FPU flags (to privileged unit)
.FIntDivResultW .FIntDivResultW);
); // floating point unit
end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low end else begin // no F_SUPPORTED or D_SUPPORTED; tie outputs low
assign FPUStallD = 0; assign FPUStallD = 0;
assign FWriteIntE = 0; assign FWriteIntE = 0;