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Fixed bug with performance counters not tracking the correct number of requested icache and dcache memory operations.

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This commit is contained in:
Ross Thompson 2023-07-14 16:31:44 -05:00
parent 59022099c7
commit 50bc679fef
2 changed files with 5 additions and 4 deletions
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3
src/cache/cachefsm.sv vendored
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@ -92,7 +92,8 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) (
assign FlushFlag = FlushAdrFlag & FlushWayFlag;
// outputs for the performance counters.
assign CacheAccess = (|CacheRW) & CurrState == STATE_READY; // exclusion-tag: icache CacheW
assign CacheAccess = (|CacheRW) & ((CurrState == STATE_READY & ~Stall & ~FlushStage) |
(CurrState == STATE_READ_HOLD & ~Stall & ~FlushStage)); // exclusion-tag: icache CacheW
assign CacheMiss = CacheAccess & ~CacheHit;
// special case on reset. When the fsm first exists reset the

4
src/privileged/csrc.sv
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@ -101,10 +101,10 @@ module csrc import cvw::*; #(parameter cvw_t P) (
assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong
assign CounterEvent[11] = LoadStallM; // Load Stalls. don't want to suppress on flush as this only happens if flushed.
assign CounterEvent[12] = StoreStallM; // Store Stall
assign CounterEvent[13] = DCacheAccess & InstrValidNotFlushedM; // data cache access
assign CounterEvent[13] = DCacheAccess; // data cache access
assign CounterEvent[14] = DCacheMiss; // data cache miss. Miss asserted 1 cycle at start of cache miss
assign CounterEvent[15] = DCacheStallM; // d cache miss cycles
assign CounterEvent[16] = ICacheAccess & InstrValidNotFlushedM; // instruction cache access
assign CounterEvent[16] = ICacheAccess; // instruction cache access
assign CounterEvent[17] = ICacheMiss; // instruction cache miss. Miss asserted 1 cycle at start of cache miss
assign CounterEvent[18] = ICacheStallF; // i cache miss cycles
assign CounterEvent[19] = CSRWriteM & InstrValidNotFlushedM; // CSR writes