From 905c5da7a9bfa44d25fa1a5978efcdb754422c57 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 24 Oct 2023 10:45:41 -0700 Subject: [PATCH 1/3] Tested assembly language file for the pause example --- .gitignore | 1 + examples/asm/etc/Makefile | 11 +++++++++++ examples/asm/etc/pause.S | 25 +++++++++++++++++++++++++ 3 files changed, 37 insertions(+) create mode 100644 examples/asm/etc/Makefile create mode 100644 examples/asm/etc/pause.S diff --git a/.gitignore b/.gitignore index 04ae44109..b4223b50e 100644 --- a/.gitignore +++ b/.gitignore @@ -62,6 +62,7 @@ examples/fp/fpcalc/fpcalc examples/C/inline/inline examples/C/sum_mixed/sum_mixed examples/asm/trap/trap +examples/asm/etc/pause src/fma/fma16_testgen linux/devicetree/debug/* !linux/devicetree/debug/dump-dts.sh diff --git a/examples/asm/etc/Makefile b/examples/asm/etc/Makefile new file mode 100644 index 000000000..72f99e975 --- /dev/null +++ b/examples/asm/etc/Makefile @@ -0,0 +1,11 @@ +TARGET = pause + +$(TARGET).objdump: $(TARGET) + riscv64-unknown-elf-objdump -D $(TARGET) > $(TARGET).objdump + +pause: pause.S Makefile + riscv64-unknown-elf-gcc -o pause -march=rv32ia_zihintpause -mabi=ilp32 -mcmodel=medany \ + -nostartfiles -T../../link/link.ld pause.S + +clean: + rm -f $(TARGET) $(TARGET).objdump diff --git a/examples/asm/etc/pause.S b/examples/asm/etc/pause.S new file mode 100644 index 000000000..4e0aacfb4 --- /dev/null +++ b/examples/asm/etc/pause.S @@ -0,0 +1,25 @@ +.section .text.init +.globl rvtest_entry_point +rvtest_entry_point: + + +la a0, lock + +spinlock: # address of lock is in a0 + lr.w t0, (a0) # read the lock + bnez t0, retry # spin until free + li t1, 1 + sc.w t0, t1, (a0) # try to write a 1 to take lock + bnez t0, retry # spin until successful + ret # got the lock! +retry: # no lock yet + pause # pause hint to reduce spin power + j spinlock # try again + + +self_loop: + j self_loop + +.data +lock: + .word 1 \ No newline at end of file From 3bb75394297858328e26e78105a973aec1b66423 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 24 Oct 2023 14:01:43 -0700 Subject: [PATCH 2/3] Fixed warnings of signed conversion and for Design Compiler --- src/ebu/ebufsmarb.sv | 2 +- src/ifu/ifu.sv | 2 +- src/lsu/swbytemask.sv | 2 +- synthDC/scripts/synth.tcl | 6 +++++- 4 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 91fa9e491..302c4752f 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -116,5 +116,5 @@ module ebufsmarb ( // 11 16 15 always_comb if (HBURST[2:1] == 2'b00) Threshold = 4'b0000; - else Threshold = (2 << HBURST[2:1]) - 1; + else Threshold = ('d2 << HBURST[2:1]) - 'd1; endmodule diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index af6f70898..bacff6b50 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -389,7 +389,7 @@ module ifu import cvw::*; #(parameter cvw_t P) ( flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD); flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE); - assign PCLinkE = PCE + (CompressedE ? 2 : 4); + assign PCLinkE = PCE + (CompressedE ? 'd2 : 'd4); // 'd4 means 4 but stops Design Compiler complaining about signed to unsigned conversion // pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE); diff --git a/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv index ad20a4414..d8c4ed167 100644 --- a/src/lsu/swbytemask.sv +++ b/src/lsu/swbytemask.sv @@ -33,7 +33,7 @@ module swbytemask #(parameter WORDLEN)( output logic [WORDLEN/8-1:0] ByteMask ); - assign ByteMask = ((2**(2**Size))-1) << Adr; + assign ByteMask =(('d2**('d2**Size))-'d1) << Adr; // 'd2 means 2, but stops Design Compiler from complaining about signed to unsigned conversion /* Equivalent to the following diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index bdd868dd1..997574312 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -12,6 +12,8 @@ suppress_message {VER-130} # statements in initial blocks are ignored suppress_message {VER-281} suppress_message {VER-173} + # Unsupported system task '$warn' +suppress_message {VER-274} # Enable Multicore set_host_options -max_cores $::env(MAXCORES) @@ -107,6 +109,7 @@ if { $saifpower == 1 } { if {$drive != "INV"} { set_false_path -from [get_ports reset] } +# for PPA multiplexer synthesis if {(($::env(DESIGN) == "ppa_mux2d_1") || ($::env(DESIGN) == "ppa_mux4d_1") || ($::env(DESIGN) == "ppa_mux8d_1"))} { set_false_path -from {s} } @@ -124,12 +127,13 @@ if { $find_clock != [list] } { set my_clk $my_clock_pin create_clock -period $my_period $my_clk set_clock_uncertainty $my_uncertainty [get_clocks $my_clk] -} else { + } else { echo "Did not find clock! Design is probably combinational!" set my_clk vclk create_clock -period $my_period -name $my_clk } + # Optimize paths that are close to critical set_critical_range 0.05 $current_design From 09c4aaa5d9b3d427658ee423214f5a5d15d3841b Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 26 Oct 2023 20:14:14 -0700 Subject: [PATCH 3/3] Fixed reporting of timing on modules with wrappers --- synthDC/scripts/synth.tcl | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 997574312..3e616e130 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -257,6 +257,19 @@ set write_hier 1 ;# generate hierarchy report if { $wrapper == 1 } { set designname [format "%s%s" $my_design "__*"] current_design $designname + + # recreate clock below wrapper level or reporting doesn't work properly + set find_clock [ find port [list $my_clock_pin] ] + if { $find_clock != [list] } { + echo "Found clock!" + set my_clk $my_clock_pin + create_clock -period $my_period $my_clk + set_clock_uncertainty $my_uncertainty [get_clocks $my_clk] + } else { + echo "Did not find clock! Design is probably combinational!" + set my_clk vclk + create_clock -period $my_period -name $my_clk + } } # Report Constraint Violators