Added parameter for cache's SRAM length.

Progress towards verilator support.

config/buildroot/config.vh

@@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/rv32e/config.vh

@@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/rv32gc/config.vh

@@ -71,6 +71,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/rv32i/config.vh

@@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/rv32imc/config.vh

@@ -69,6 +69,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/rv64fpquad/config.vh

@@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/rv64gc/config.vh

@@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/rv64i/config.vh

@@ -70,6 +70,7 @@ localparam DCACHE_LINELENINBITS = 32'd512;
 localparam ICACHE_NUMWAYS = 32'd4;
 localparam ICACHE_WAYSIZEINBYTES = 32'd4096;
 localparam ICACHE_LINELENINBITS = 32'd512;
+localparam CACHE_SRAMLEN = 32'd128;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

config/shared/parameter-defs.vh

@@ -38,6 +38,7 @@ localparam cvw_t P = '{
   ICACHE_NUMWAYS :        ICACHE_NUMWAYS,
   ICACHE_WAYSIZEINBYTES :        ICACHE_WAYSIZEINBYTES,
   ICACHE_LINELENINBITS :        ICACHE_LINELENINBITS,
+  CACHE_SRAMLEN : CACHE_SRAMLEN,
   IDIV_BITSPERCYCLE :        IDIV_BITSPERCYCLE,
   IDIV_ON_FPU :        IDIV_ON_FPU,
   PMP_ENTRIES :        PMP_ENTRIES,

src/cache/cacheway.sv

@@ -129,21 +129,20 @@ module cacheway import cvw::*; #(parameter cvw_t P,
 
   genvar               words;
 
-  localparam           SRAMLEN = 128;             // *** make this a global parameter
+  localparam           NUMSRAM = LINELEN/P.CACHE_SRAMLEN;
-  localparam           NUMSRAM = LINELEN/SRAMLEN;
+  localparam           SRAMLENINBYTES = P.CACHE_SRAMLEN/8;
-  localparam           SRAMLENINBYTES = SRAMLEN/8;
   localparam           LOGNUMSRAM = $clog2(NUMSRAM);
   
   for(words = 0; words < NUMSRAM; words++) begin: word
     if (!READ_ONLY_CACHE) begin:wordram
-      ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
+      ram1p1rwbe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
-      .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
+      .dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
-      .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
+      .din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
       .we(SelectedWriteWordEn), .bwe(FinalByteMask[SRAMLENINBYTES*(words+1)-1:SRAMLENINBYTES*words]));
     end else begin:wordram // no byte-enable needed for i$.
-      ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
+      ram1p1rwe #(.USE_SRAM(P.USE_SRAM), .DEPTH(NUMLINES), .WIDTH(P.CACHE_SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CacheSetData),
-      .dout(ReadDataLine[SRAMLEN*(words+1)-1:SRAMLEN*words]),
+      .dout(ReadDataLine[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
-      .din(LineWriteData[SRAMLEN*(words+1)-1:SRAMLEN*words]),
+      .din(LineWriteData[P.CACHE_SRAMLEN*(words+1)-1:P.CACHE_SRAMLEN*words]),
       .we(SelectedWriteWordEn));
     end
   end

src/cvw.sv

@@ -80,6 +80,7 @@ typedef struct packed {
   int           ICACHE_NUMWAYS;
   int           ICACHE_WAYSIZEINBYTES;
   int           ICACHE_LINELENINBITS;
+  int           CACHE_SRAMLEN;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4

src/generic/mem/ram2p1r1wbe.sv

@@ -110,11 +110,11 @@ module ram2p1r1wbe import cvw::*; #(parameter USE_SRAM=0, DEPTH=1024, WIDTH=68)
     // ***************************************************************************
     integer i;
     
-  /*  initial begin // initialize memory for simulation only; not needed because done in the testbench now
+    initial begin // initialize memory for simulation only; not needed because done in the testbench now
       integer j;
       for (j=0; j < DEPTH; j++) 
         mem[j] = '0;
-    end */
+    end 
     
     // Read
     logic [$clog2(DEPTH)-1:0] ra1d;

testbench/common/DCacheFlushFSM.sv

@@ -43,8 +43,8 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P)
     localparam numways        = P.DCACHE_NUMWAYS;
     localparam linelen        = P.DCACHE_LINELENINBITS;
     localparam linebytelen    = linelen/8;
-    localparam sramlen        = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;            
+    localparam sramlen        = P.CACHE_SRAMLEN;
-    localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
+    localparam cachesramwords = linelen/sramlen;
     localparam numwords       = sramlen/P.XLEN;
     localparam lognumlines    = $clog2(numlines);
     localparam loglinebytelen = $clog2(linebytelen);

testbench/testbench.sv

@@ -271,7 +271,7 @@ module testbench;
   ////////////////////////////////////////////////////////////////////////////////
     if(TestBenchReset) test = 1;
     if (TEST == "coremark")
-      if (dut.core.EcallFaultM) begin
+      if (dut.core.priv.priv.EcallFaultM) begin
         $display("Benchmark: coremark is done.");
         $stop;
       end
@@ -320,6 +320,7 @@ module testbench;
   ////////////////////////////////////////////////////////////////////////////////
   // Some memories are not reset, but should be zeros or set to some initial value for simulation
   ////////////////////////////////////////////////////////////////////////////////
+/* -----\/----- EXCLUDED -----\/-----
   integer adrindex;
   always @(posedge clk) begin
     if (ResetMem)  // program memory is sometimes reset
@@ -339,13 +340,49 @@ module testbench;
       end
     end
   end
+ -----/\----- EXCLUDED -----/\----- */
+
+  // still not working in this format
+/* -----\/----- EXCLUDED -----\/-----
+  integer adrindex;
+  if (P.UNCORE_RAM_SUPPORTED) begin
+    always @(posedge clk) begin
+      if (ResetMem)  // program memory is sometimes reset
+        for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1) 
+          dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0;
+    end
+  end
+  
+  genvar adrindex2;
+  
+  if (P.BPRED_SUPPORTED & (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR)) begin
+    for(adrindex2 = 0; adrindex2 < 2**P.BPRED_NUM_LHR; adrindex2++)
+      always @(posedge clk) begin
+        dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex2] = 0;
+    end
+  end        
+
+  if (P.BPRED_SUPPORTED) begin
+    always @(posedge clk) 
+      dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[0] = 0;    
+    for(adrindex2 = 0; adrindex2 < 2**P.BTB_SIZE; adrindex2++)
+      always @(posedge clk) begin
+        dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex2] = 0;
+      end
+    for(adrindex2 = 0; adrindex2 < 2**P.BPRED_SIZE; adrindex2++)
+      always @(posedge clk) begin
+        dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex2] = 0;
+      end
+  end
+ -----/\----- EXCLUDED -----/\----- */
   
   ////////////////////////////////////////////////////////////////////////////////
   // load memories with program image
   ////////////////////////////////////////////////////////////////////////////////
-  always @(posedge clk) begin
+
-    if (LoadMem) begin
+  if (P.SDC_SUPPORTED) begin
-      if (P.SDC_SUPPORTED) begin
+    always @(posedge clk) begin
+      if (LoadMem) begin
         string romfilename, sdcfilename;
         romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
         sdcfilename = {"../testbench/sdc/ramdisk2.hex"};   
@@ -354,10 +391,26 @@ module testbench;
         // shorten sdc timers for simulation
         //dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
       end
-      else if (P.IROM_SUPPORTED)     $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
+    end
-      else if (P.BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+  end else if (P.IROM_SUPPORTED) begin
-      if (P.DTIM_SUPPORTED)     $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
+    always @(posedge clk) begin
-      $display("Read memfile %s", memfilename);
+      if (LoadMem) begin
+        $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
+      end
+    end
+  end else if (P.BUS_SUPPORTED) begin
+    always @(posedge clk) begin
+      if (LoadMem) begin
+        $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+      end
+    end
+  end 
+  if (P.DTIM_SUPPORTED) begin
+    always @(posedge clk) begin
+      if (LoadMem) begin
+        $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
+        $display("Read memfile %s", memfilename);
+      end
     end
   end