From e2c990f47d43462ed82daf607d9e5767b06f0795 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 23 May 2023 15:37:09 -0700 Subject: [PATCH 1/3] Increased timeout for riscof because it is so slow --- tests/riscof/sail_cSim/riscof_sail_cSim.py | 3 ++- tests/riscof/spike/riscof_spike.py | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/riscof/sail_cSim/riscof_sail_cSim.py b/tests/riscof/sail_cSim/riscof_sail_cSim.py index b34425f72..972b838e1 100644 --- a/tests/riscof/sail_cSim/riscof_sail_cSim.py +++ b/tests/riscof/sail_cSim/riscof_sail_cSim.py @@ -130,4 +130,5 @@ class sail_cSim(pluginTemplate): make.add_target(execute) # make.execute_all(self.work_dir) # DH 7/26/22 increase timeout so sim will finish on slow machines - make.execute_all(self.work_dir, timeout = 1800) +# DH 5/17/23 increase timeout to 3600 seconds + make.execute_all(self.work_dir, timeout = 3600) diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py index 67c88b6ab..4a5b68b96 100644 --- a/tests/riscof/spike/riscof_spike.py +++ b/tests/riscof/spike/riscof_spike.py @@ -191,7 +191,8 @@ class spike(pluginTemplate): # parallel using the make command set above. #make.execute_all(self.work_dir) # DH 7/26/22 increase timeout to 1800 seconds so sim will finish on slow machines - make.execute_all(self.work_dir, timeout = 1800) + # DH 5/17/23 increase timeout to 3600 seconds + make.execute_all(self.work_dir, timeout = 3600) # if target runs are not required then we simply exit as this point after running all From ee3660b0f2a215f16c242da1a088b15ded42ae62 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 23 May 2023 15:43:11 -0700 Subject: [PATCH 2/3] Removed unnecessary imperas tests from coverage --- sim/regression-wally | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index 6e7ccf388..1569abd77 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -136,11 +136,9 @@ tests64gc = ["arch64f", "arch64d", "arch64f_fma", "arch64d_fma", "arch64i", "arc "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] if (coverage): # delete all but 64gc tests when running coverage configs = [] -# tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv", - "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", - "imperas64f", "imperas64d", "imperas64c", "imperas64i"] + "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs"] if (fp): tests64gc.append("arch64f") tests64gc.append("arch64d") From 8d03905e4b5e07f219c171ce37682fb60af70c57 Mon Sep 17 00:00:00 2001 From: David Harris Date: Tue, 23 May 2023 15:45:32 -0700 Subject: [PATCH 3/3] Added fulladder coverage script example --- examples/verilog/fulladder/fulladder-batch-coverage.do | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 examples/verilog/fulladder/fulladder-batch-coverage.do diff --git a/examples/verilog/fulladder/fulladder-batch-coverage.do b/examples/verilog/fulladder/fulladder-batch-coverage.do new file mode 100644 index 000000000..324ac9142 --- /dev/null +++ b/examples/verilog/fulladder/fulladder-batch-coverage.do @@ -0,0 +1,8 @@ +# fulladder-batch-coverage.do +# David_Harris@hmc.edu 22 May 2023 +vlog fulladder.sv +vopt +acc work.testbench -o workopt +cover=sbecf +vsim workopt -coverage +run -all +coverage save -instance /testbench/dut fulladder.ucdb +quit \ No newline at end of file