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Automatically enable I_CACHE_ADDR_LOGGER and I_CACHE_ADDR_LOGGER in rv64gc_CacheSim.py. Working for Questa and Verilator.

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Jordan Carlin 2024-08-10 12:21:44 -07:00
parent c19916a1d0
commit 4ffd10bbb8
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1 changed files with 5 additions and 2 deletions
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7
sim/rv64gc_CacheSim.py
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@ -65,8 +65,8 @@ if __name__ == '__main__':
parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="verilator") parser.add_argument('-s', "--sim", help="Simulator", choices=["questa", "verilator", "vcs"], default="verilator")
args = parser.parse_args() args = parser.parse_args()
simargs = "-GI_CACHE_ADDR_LOGGER=1\\\'b1 -GD_CACHE_ADDR_LOGGER=1\\\'b1"
testcmd = "wsim --sim " + args.sim + " rv64gc {} > /dev/null" testcmd = "wsim --sim " + args.sim + " rv64gc {} --args \"" + simargs + "\" > /dev/null"
cachecmd = "CacheSim.py 64 4 56 44 -f {}" cachecmd = "CacheSim.py 64 4 56 44 -f {}"
if args.perf: if args.perf:
@ -76,6 +76,9 @@ if __name__ == '__main__':
for test in tests64gc: for test in tests64gc:
print(f"{bcolors.HEADER}Commencing test", test+f":{bcolors.ENDC}") print(f"{bcolors.HEADER}Commencing test", test+f":{bcolors.ENDC}")
# remove wkdir to force recompile with logging enabled
os.system("rm -rf " + simdir + "/" + args.sim + "/wkdir/rv64gc_" + test)
os.system("rm -rf " + simdir + "/" + args.sim + "/*Cache.log")
print(testcmd.format(test)) print(testcmd.format(test))
os.system(testcmd.format(test)) os.system(testcmd.format(test))
for cache in cachetypes: for cache in cachetypes: