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https://github.com/openhwgroup/cvw
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Coverage improvements
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171430a695
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@ -92,6 +92,7 @@ for {set i 0} {$i < $numcacheways} {incr i} {
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coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6
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coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6
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# below: flushD can't go high during an icache write b/c of pipeline stall
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# below: flushD can't go high during an icache write b/c of pipeline stall
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coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
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coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
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coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4
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}
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}
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## D$ Exclusions.
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## D$ Exclusions.
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@ -107,6 +108,8 @@ for {set i 0} {$i < $numcacheways} {incr i} {
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# FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before
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# FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before
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# going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW.
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# going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW.
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coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
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coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
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coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache ClearValidEN"] -item e 1 -fecexprrow 4
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# Not right; other ways can get flushed and dirtied simultaneously coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache UpdateDirty"] -item c 1 -fecexprrow 6
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}
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}
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# D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush
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# D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush
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coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY
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coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY
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@ -237,11 +240,16 @@ coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item e
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coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item b 1
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coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item b 1
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coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item s 1
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coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line2 -item s 1
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# IMMU never disables translations
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coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign Translate"] -item e 1 -fecexprrow 2
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coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign UpdateDA"] -item e 1 -fecexprrow 5
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# never reaches this when ENVCFG_ADUE_1 because HPTW updates A bit first
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coverage exclude -scope /dut/core/ifu/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "assign PrePageFault"] -item e 1 -fecexprrow 18
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# IMMU PMP does not support CBO instructions
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# IMMU PMP does not support CBO instructions
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coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcbom"]
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coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcbom"]
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coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboz"]
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coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboz"]
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coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboaccess"]
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coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpcboaccess"]
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#coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange [GetLineNum ../src/mmu/pmpchecker.sv "exclusion-tag: immu-pmpstoreamoaccessfault"]
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# No irom
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# No irom
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set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & ~CacheableF & ~SelIROM"]
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set line [GetLineNum ../src/ifu/ifu.sv "~ITLBMissF & ~CacheableF & ~SelIROM"]
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4
src/cache/cacheway.sv
vendored
4
src/cache/cacheway.sv
vendored
@ -105,7 +105,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
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assign ClearDirtyWay = ClearDirty & SelData;
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assign ClearDirtyWay = ClearDirty & SelData;
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assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn
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assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn
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assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: cache SetValidEN
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assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: cache SetValidEN
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assign ClearValidEN = ClearValidWay & ~FlushStage; // exclusion-tag: cache SetValidEN
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assign ClearValidEN = ClearValidWay & ~FlushStage; // exclusion-tag: cache ClearValidEN
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// If writing the whole line set all write enables to 1, else only set the correct word.
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// If writing the whole line set all write enables to 1, else only set the correct word.
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assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR
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assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR
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@ -178,7 +178,7 @@ module cacheway import cvw::*; #(parameter cvw_t P,
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//if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
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//if (reset) DirtyBits <= #1 {NUMLINES{1'b0}};
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if(CacheEn) begin
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if(CacheEn) begin
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Dirty <= #1 DirtyBits[CacheSetTag];
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Dirty <= #1 DirtyBits[CacheSetTag];
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if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CacheSetData] <= #1 SetDirtyWay;
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if((SetDirtyWay | ClearDirtyWay) & ~FlushStage) DirtyBits[CacheSetData] <= #1 SetDirtyWay; // exclusion-tag: cache UpdateDirty
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end
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end
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end
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end
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end else assign Dirty = 1'b0;
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end else assign Dirty = 1'b0;
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@ -17,7 +17,7 @@ all: $(OBJECTS)
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# Change many things if bit width isn't 64
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# Change many things if bit width isn't 64
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%.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile
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%.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile
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riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom -mabi=lp64 -mcmodel=medany \
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riscv64-unknown-elf-gcc -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom -mabi=lp64 -mcmodel=medany \
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-nostartfiles -T../../examples/link/link.ld $<
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-nostartfiles -T../../examples/link/link.ld $<
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riscv64-unknown-elf-objdump -S $@ > $@.objdump
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riscv64-unknown-elf-objdump -S $@ > $@.objdump
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riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile
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riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile
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@ -36,6 +36,9 @@ rvtest_entry_point:
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csrw mtvec, t0 # Initialize MTVEC to trap_handler
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csrw mtvec, t0 # Initialize MTVEC to trap_handler
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csrw mideleg, zero # Don't delegate interrupts
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csrw mideleg, zero # Don't delegate interrupts
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csrw medeleg, zero # Don't delegate exceptions
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csrw medeleg, zero # Don't delegate exceptions
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li t0, -1 # set mtimecmp to biggest number so it doesnt interrupt again
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li t1, 0x02004000 # MTIMECMP in CLINT
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sd t0, 0(t1)
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li t0, 0x80
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li t0, 0x80
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csrw mie, t0 # Enable machine timer interrupt
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csrw mie, t0 # Enable machine timer interrupt
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la t0, topoftrapstack
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la t0, topoftrapstack
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@ -62,6 +62,30 @@ main:
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jalr ra, t0 # jump to misaligned gigapage
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jalr ra, t0 # jump to misaligned gigapage
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li t0, 0x80200000
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li t0, 0x80200000
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jalr ra, t0 # jump to misaligned megapage
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jalr ra, t0 # jump to misaligned megapage
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li t0, 0x7FFFFFFF80000000
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jalr ra, t0 # jump to page with UpperBitsUnequal
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li t0, 0x0000000080C00000
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jalr ra, t0 # jump to page with bad reserved bits 60:54 in PTE
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# test with ENVCFG_ADUE = 1: switch to machine mode, set ADUE, access page with A=0, clear ADUE,
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li a0, 3
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ecall # switch to machine mode
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li t0, 1
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slli t0, t0, 61
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csrs menvcfg, t0 # set menvcfg.ADUE
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li a0, 1
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ecall # switch back to supervisor mode
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li t0, 0x0000000080E00000
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jalr ra, t0 # jump to page without accessed bit yet set
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li a0, 3
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ecall # switch to machine mode
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li t0, 1
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slli t0, t0, 61
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csrc menvcfg, t0 # clear menvcfg.ADUE
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li a0, 1
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ecall # switch back to supervisor mode
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# exercise malformed PBMT pages
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# exercise malformed PBMT pages
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@ -147,6 +171,8 @@ main:
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li a0, 1
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li a0, 1
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ecall
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ecall
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# wrap up
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# wrap up
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li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
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li a0, 3 # switch back to machine mode because code at 0x80000000 may not have clean page table entry
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ecall
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ecall
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@ -222,8 +248,8 @@ pagetable:
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.8byte 0x4000000020004CC1 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0)
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.8byte 0x4000000020004CC1 # for VA starting at 80600000 (bad entry: nonleaf PTE can't have PBMT != 0)
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.8byte 0x00000000200054C1 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz)
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.8byte 0x00000000200054C1 # for VA starting at 80800000 (testing rwx permissiosn with cbom/cboz)
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.8byte 0x0000000020004CC1 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000)
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.8byte 0x0000000020004CC1 # for VA starting at 80A00000 (pointer to NAPOT 64 KiB pages like at 80000000)
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.8byte 0x0000000020004CC1
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.8byte 0x0F00000020004CCF # for VA starting at 80C00000 (bad reserved field in bits 60:54)
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.8byte 0x0000000020004CC1
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.8byte 0x000000002000000F # for VA starting at 80E00000 (not dirty or accessed)
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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.8byte 0x0000000020004CC1
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