cleaning

src/wrappers/wallypipelinedcorewrapper.sv

@@ -30,18 +30,19 @@
 
 import cvw::*;
 
+`include "parameter-defs.vh"
 module wallypipelinedcorewrapper (
    input  logic                  clk, reset,
    // Privileged
    input  logic                  MTimerInt, MExtInt, SExtInt, MSwInt,
    input  logic [63:0]           MTIME_CLINT, 
    // Bus Interface
-   input  logic [AHBW-1:0]     HRDATA,
+   input  logic [P.XLEN-1:0]     HRDATA,
    input  logic                  HREADY, HRESP,
    output logic                  HCLK, HRESETn,
-   output logic [PA_BITS-1:0]  HADDR,
-   output logic [AHBW-1:0]     HWDATA,
-   output logic [XLEN/8-1:0]   HWSTRB,
+   output logic [P.PA_BITS-1:0]  HADDR,
+   output logic [32-1:0]     HWDATA,
+   output logic [32/8-1:0]   HWSTRB,
    output logic                  HWRITE,
    output logic [2:0]            HSIZE,
    output logic [2:0]            HBURST,
@@ -49,7 +50,6 @@ module wallypipelinedcorewrapper (
    output logic [1:0]            HTRANS,
    output logic                  HMASTLOCK
 );
-  `include "parameter-defs.vh"
 
   wallypipelinedcore  #(P) core(.*); 
 

synthDC/scripts/synth.tcl

@@ -36,15 +36,13 @@ if {$wrapper ==1 } {
 }
 
 
-# Only for FMA class project; comment out when done
-# eval file copy -force [glob ${hdl_src}/fma/fma16.v] {hdl/}
-
 # Enables name mapping
 if { $saifpower == 1 } {
     saif_map -start
 }
 
 # Verilog files
+#set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv $outputDir/config/*.vh]
 set my_verilog_files [glob $outputDir/hdl/cvw.sv $outputDir/hdl/*.sv]
 
 # Set toplevel

synthDC/wrappers/drsuwrapper.sv

@@ -1,5 +1,5 @@
 ///////////////////////////////////////////
-// drsu.sv
+// drsuwrapper.sv
 //
 // Written: kekim@hmc.edu
 // Modified:19 May 2023
@@ -29,6 +29,7 @@
 
 import cvw::*;
 
+`include "parameter-defs.vh"
 module drsuwrapper (
   input  logic                clk, 
   input  logic                reset, 
@@ -57,7 +58,7 @@ module drsuwrapper(
 );
 //`include "parameter-defs.vh"
 
-drsu #(P) d(.*);
+  drsu #(P) drsucore(.*);
 
 
 endmodule