Modified dcache to ensure nontranslated index is used.

wally-pipelined/src/cache/dcache.sv

@@ -38,6 +38,7 @@ module dcache
    input logic 								FlushDCacheM,
    input logic [11:0] 						LsuAdrE, // virtual address, but we only use the lower 12 bits.
    input logic [`PA_BITS-1:0] 				LsuPAdrM, // physical address
+   input logic [11:0] 						PreLsuPAdrM, // physical or virtual address   
    input logic [`XLEN-1:0] 					FinalWriteDataM,
    output logic [`XLEN-1:0] 				ReadDataWordM,
    output logic 							DCacheCommittedM, 
@@ -122,7 +123,7 @@ module dcache
 
   mux3 #(INDEXLEN)
   AdrSelMux(.d0(LsuAdrE[INDEXLEN+OFFSETLEN-1:OFFSETLEN]),
-			.d1(LsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), // *** optimize change to virtual address.
+			.d1(PreLsuPAdrM[INDEXLEN+OFFSETLEN-1:OFFSETLEN]), // *** optimize change to virtual address.
 			.d2(FlushAdr),
 			.s(SelAdrM),
 			.y(RAdr));

wally-pipelined/src/cache/dcachefsm.sv

@@ -35,7 +35,7 @@ module dcachefsm
    // hazard inputs
    input logic 		  CPUBusy,
    input logic 		  CacheableM,
-   // hptw inputs
+   // interlock fsm
    input logic 		  IgnoreRequest,
    // Bus inputs
    input logic 		  DCacheBusAck,

wally-pipelined/src/lsu/lsu.sv

@@ -307,7 +307,7 @@ module lsu
   generate
     if(`MEM_DCACHE) begin : dcache
       dcache dcache(.clk, .reset, .CPUBusy,
-            .LsuRWM, .FlushDCacheM, .LsuAtomicM, .LsuAdrE, .LsuPAdrM,
+            .LsuRWM, .FlushDCacheM, .LsuAtomicM, .LsuAdrE, .LsuPAdrM, .PreLsuPAdrM(PreLsuPAdrM[11:0]), // still don't like this name PreLsuPAdrM, not always physical
             .FinalWriteDataM, .ReadDataWordM, .DCacheStall,
             .DCacheMiss, .DCacheAccess, 
             .IgnoreRequest, .CacheableM, .DCacheCommittedM,