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Eliminate reserved bits from TLB RAM

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This commit is contained in:
David Harris 2021-07-08 17:35:00 -04:00
parent 38772de21f
commit 4f1a85ca7c
2 changed files with 6 additions and 6 deletions
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10
wally-pipelined/src/mmu/tlbram.sv
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@ -36,13 +36,13 @@ module tlbram #(parameter TLB_ENTRIES = 8) (
output logic [TLB_ENTRIES-1:0] PTE_Gs output logic [TLB_ENTRIES-1:0] PTE_Gs
); );
logic [`XLEN-1:0] RamRead[TLB_ENTRIES-1:0]; logic [`PPN_BITS+9:0] RamRead[TLB_ENTRIES-1:0];
logic [`XLEN-1:0] PageTableEntry; logic [`PPN_BITS+9:0] PageTableEntry;
// Generate a flop for every entry in the RAM
tlbramline #(`XLEN) tlblineram[TLB_ENTRIES-1:0](clk, reset, Matches, WriteEnables, PTE, RamRead, PTE_Gs);
// RAM implemented with array of flops and AND/OR read logic
tlbramline #(`PPN_BITS+10) tlblineram[TLB_ENTRIES-1:0](clk, reset, Matches, WriteEnables, PTE[`PPN_BITS+9:0], RamRead, PTE_Gs);
assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE assign PageTableEntry = RamRead.or; // OR each column of RAM read to read PTE
// Rename the bits read from the TLB RAM
assign PTEAccessBits = PageTableEntry[7:0]; assign PTEAccessBits = PageTableEntry[7:0];
assign PPN = PageTableEntry[`PPN_BITS+9:10]; assign PPN = PageTableEntry[`PPN_BITS+9:10];
endmodule endmodule

2
wally-pipelined/src/mmu/tlbramline.sv
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@ -34,7 +34,7 @@ module tlbramline #(parameter WIDTH)
logic [WIDTH-1:0] line; logic [WIDTH-1:0] line;
flopenr #(`XLEN) pteflop(clk, reset, we, d, line); flopenr #(WIDTH) pteflop(clk, reset, we, d, line);
assign q = re ? line : 0; assign q = re ? line : 0;
assign PTE_G = line[5]; // send global bit to CAM as part of ASID matching assign PTE_G = line[5]; // send global bit to CAM as part of ASID matching
endmodule endmodule