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Add TV for testbenches (to be added shortly) however had to leave off fma due to size. The TV were slightly modified within TestFloat to add underscores for readability. The scripts I created to create these TV were also included

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This commit is contained in:
James E. Stine 2021-10-06 08:56:01 -05:00
parent b90d7b8083
commit 4ece7b5341
2 changed files with 60 additions and 0 deletions
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30
wally-pipelined/testbench/fp/create_vectors32.csh Executable file
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#!/bin/sh
./testfloat_gen -rnear_even f32_add > f32_add_rne.tv
./testfloat_gen -rminMag f32_add > f32_add_rz.tv
./testfloat_gen -rmax f32_add > f32_add_ru.tv
./testfloat_gen -rmin f32_add > f32_add_rd.tv
./testfloat_gen -rnear_even f32_sub > f32_sub_rne.tv
./testfloat_gen -rminMag f32_sub > f32_sub_rz.tv
./testfloat_gen -rmax f32_sub > f32_sub_ru.tv
./testfloat_gen -rmin f32_sub > f32_sub_rd.tv
./testfloat_gen -rnear_even f32_mul > f32_mul_rne.tv
./testfloat_gen -rminMag f32_mul > f32_mul_rz.tv
./testfloat_gen -rmax f32_mul > f32_mul_ru.tv
./testfloat_gen -rmin f32_mul > f32_mul_rd.tv
./testfloat_gen -rnear_even f32_mulAdd > f32_fma_rne.tv
./testfloat_gen -rminMag f32_mulAdd > f32_fma_rz.tv
./testfloat_gen -rmax f32_mulAdd > f32_fma_ru.tv
./testfloat_gen -rmin f32_mulAdd > f32_fma_rd.tv
./testfloat_gen -rnear_even f32_div > f32_div_rne.tv
./testfloat_gen -rminMag f32_div > f32_div_rz.tv
./testfloat_gen -rmax f32_div > f32_div_ru.tv
./testfloat_gen -rmin f32_div > f32_div_rd.tv
./testfloat_gen -rnear_even f32_sqrt > f32_sqrt_rne.tv
./testfloat_gen -rminMag f32_sqrt > f32_sqrt_rz.tv
./testfloat_gen -rmax f32_sqrt > f32_sqrt_ru.tv
./testfloat_gen -rmin f32_sqrt > f32_sqrt_rd.tv

30
wally-pipelined/testbench/fp/create_vectors64.csh Executable file
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#!/bin/sh
./testfloat_gen -rnear_even f64_add > f64_add_rne.tv
./testfloat_gen -rminMag f64_add > f64_add_rz.tv
./testfloat_gen -rmax f64_add > f64_add_ru.tv
./testfloat_gen -rmin f64_add > f64_add_rd.tv
./testfloat_gen -rnear_even f64_sub > f64_sub_rne.tv
./testfloat_gen -rminMag f64_sub > f64_sub_rz.tv
./testfloat_gen -rmax f64_sub > f64_sub_ru.tv
./testfloat_gen -rmin f64_sub > f64_sub_rd.tv
./testfloat_gen -rnear_even f64_mul > f64_mul_rne.tv
./testfloat_gen -rminMag f64_mul > f64_mul_rz.tv
./testfloat_gen -rmax f64_mul > f64_mul_ru.tv
./testfloat_gen -rmin f64_mul > f64_mul_rd.tv
./testfloat_gen -rnear_even f64_mulAdd > f64_fma_rne.tv
./testfloat_gen -rminMag f64_mulAdd > f64_fma_rz.tv
./testfloat_gen -rmax f64_mulAdd > f64_fma_ru.tv
./testfloat_gen -rmin f64_mulAdd > f64_fma_rd.tv
./testfloat_gen -rnear_even f64_div > f64_div_rne.tv
./testfloat_gen -rminMag f64_div > f64_div_rz.tv
./testfloat_gen -rmax f64_div > f64_div_ru.tv
./testfloat_gen -rmin f64_div > f64_div_rd.tv
./testfloat_gen -rnear_even f64_sqrt > f64_sqrt_rne.tv
./testfloat_gen -rminMag f64_sqrt > f64_sqrt_rz.tv
./testfloat_gen -rmax f64_sqrt > f64_sqrt_ru.tv
./testfloat_gen -rmin f64_sqrt > f64_sqrt_rd.tv