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Changed the IROM and DTIM memories to behave like edge-triggered srams.

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This commit is contained in:
Ross Thompson 2022-01-21 15:42:54 -06:00
parent c2c7351b24
commit 4ecc2d029a
3 changed files with 30 additions and 17 deletions
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11
pipelined/src/generic/flop/simpleram.sv
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@ -54,23 +54,26 @@ module simpleram #(parameter BASE=0, RANGE = 65535) (
logic memwrite; logic memwrite;
logic [3:0] busycount; logic [3:0] busycount;
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);
flopenr #(32) haddrreg(HCLK, 1'b0, 1'b1, HADDR, A);
/* verilator lint_off WIDTH */ /* verilator lint_off WIDTH */
if (`XLEN == 64) begin:ramrw if (`XLEN == 64) begin:ramrw
always_ff @(posedge HCLK) begin always_ff @(posedge HCLK) begin
if (HWRITE & |HTRANS) RAM[HADDR[31:3]] <= #1 HWDATA; if (HWRITE & |HTRANS) RAM[A[31:3]] <= #1 HWDATA;
end end
end else begin end else begin
always_ff @(posedge HCLK) begin:ramrw always_ff @(posedge HCLK) begin:ramrw
if (HWRITE & |HTRANS) RAM[HADDR[31:2]] <= #1 HWDATA; if (HWRITE & |HTRANS) RAM[A[31:2]] <= #1 HWDATA;
end end
end end
// read // read
if(`XLEN == 64) begin: ramr if(`XLEN == 64) begin: ramr
assign HREADRam0 = RAM[HADDR[31:3]]; assign HREADRam0 = RAM[A[31:3]];
end else begin end else begin
assign HREADRam0 = RAM[HADDR[31:2]]; assign HREADRam0 = RAM[A[31:2]];
end end
/* verilator lint_on WIDTH */ /* verilator lint_on WIDTH */

32
pipelined/src/ifu/ifu.sv
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@ -96,7 +96,7 @@ module ifu (
logic [`XLEN-1:0] PCD; logic [`XLEN-1:0] PCD;
localparam [31:0] nop = 32'h00000013; // instruction for NOP localparam [31:0] nop = 32'h00000013; // instruction for NOP
//logic reset_q; // see comment below about PCNextF and icache. logic reset_q; // see comment below about PCNextF and icache.
logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE; logic BPPredDirWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
logic [`XLEN-1:0] PCBPWrongInvalidate; logic [`XLEN-1:0] PCBPWrongInvalidate;
@ -236,11 +236,20 @@ module ifu (
simpleram #( simpleram #(
.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( .BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.HCLK(clk), .HRESETn(~reset), .HCLK(clk), .HRESETn(~reset),
.HSELRam(1'b1), .HADDR(PCPF[31:0]), .HSELRam(1'b1), .HADDR(CPUBusy ? PCPF[31:0] : PCNextF[31:0]), // mux is also inside $, have to replay address if CPU is stalled.
.HWRITE(1'b0), .HREADY(1'b1), .HWRITE(1'b0), .HREADY(1'b1),
.HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF_FIXME), .HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF_FIXME),
.HRESPRam(), .HREADYRam()); .HRESPRam(), .HREADYRam());
/* -----\/----- EXCLUDED -----\/-----
ram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.HCLK(clk), .HRESETn(~reset),
.HSELRam(1'b1), .HADDR(PCNextF[31:0]),
.HWRITE(1'b0), .HREADY(1'b1),
.HTRANS(2'b10), .HWDATA(0), .HREADRam(FinalInstrRawF_FIXME),
.HRESPRam(), .HREADYRam());
-----/\----- EXCLUDED -----/\----- */
assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0]; assign FinalInstrRawF = FinalInstrRawF_FIXME[31:0];
assign BusStall = 0; assign BusStall = 0;
assign IFUBusRead = 0; assign IFUBusRead = 0;
@ -354,9 +363,9 @@ module ifu (
mux2 #(`XLEN) pcmux3(.d0(PCNext2F), mux2 #(`XLEN) pcmux3(.d0(PCNext2F),
.d1(PrivilegedNextPCM), .d1(PrivilegedNextPCM),
.s(PrivilegedChangePCM), .s(PrivilegedChangePCM),
.y(UnalignedPCNextF)); //.y(UnalignedPCNextF));
.y(PCNext3F));
//.y(PCNext3F));
// This mux is not strictly speaking required. Because the icache takes in // This mux is not strictly speaking required. Because the icache takes in
// PCNextF rather than PCPF, PCNextF should stay in reset while the cache // PCNextF rather than PCPF, PCNextF should stay in reset while the cache
// looks up the addresses. Without this mux PCNextF will increment + 2/4. // looks up the addresses. Without this mux PCNextF will increment + 2/4.
@ -367,13 +376,14 @@ module ifu (
// cache line so the mux is not required. I am leaving this comment and mux // cache line so the mux is not required. I am leaving this comment and mux
// a a reminder as to what is happening in case keep PCNextF at RESET_VECTOR // a a reminder as to what is happening in case keep PCNextF at RESET_VECTOR
// during reset becomes a requirement. // during reset becomes a requirement.
//mux2 #(`XLEN) pcmux4(.d0(PCNext3F), mux2 #(`XLEN) pcmux4(.d0(PCNext3F),
// .d1(`RESET_VECTOR), .d1(`RESET_VECTOR),
// .s(reset_q), .s(`MEM_IROM ? reset : reset_q),
// .y(UnalignedPCNextF)); .y(UnalignedPCNextF));
//flop #(1) resetReg (.clk(clk),
// .d(reset), flop #(1) resetReg (.clk(clk),
// .q(reset_q)); .d(reset),
.q(reset_q));
flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM), flopenrc #(1) BPPredWrongMReg(.clk, .reset, .en(~StallM), .clear(FlushM),

4
pipelined/src/lsu/lsu.sv
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@ -247,7 +247,7 @@ module lsu (
if (`MEM_DTIM) begin : dtim if (`MEM_DTIM) begin : dtim
simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram ( simpleram #(.BASE(`RAM_BASE), .RANGE(`RAM_RANGE)) ram (
.HCLK(clk), .HRESETn(~reset), .HCLK(clk), .HRESETn(~reset),
.HSELRam(1'b1), .HADDR(LSUPAdrM[31:0]), .HSELRam(1'b1), .HADDR(CPUBusy ? IEUAdrM[31:0] : IEUAdrE[31:0]),
.HWRITE(LSURWM[0]), .HREADY(1'b1), .HWRITE(LSURWM[0]), .HREADY(1'b1),
.HTRANS(|LSURWM ? 2'b10 : 2'b00), .HWDATA(FinalWriteDataM), .HREADRam(ReadDataWordM), .HTRANS(|LSURWM ? 2'b10 : 2'b00), .HWDATA(FinalWriteDataM), .HREADRam(ReadDataWordM),
.HRESPRam(), .HREADYRam()); .HRESPRam(), .HREADYRam());
@ -259,7 +259,7 @@ module lsu (
assign {DCacheStallM, DCacheCommittedM, DCacheWriteLine, DCacheFetchLine, DCacheBusAdr} = '0; assign {DCacheStallM, DCacheCommittedM, DCacheWriteLine, DCacheFetchLine, DCacheBusAdr} = '0;
assign ReadDataLineSetsM[0] = 0; assign ReadDataLineSetsM[0] = 0;
assign DCacheMiss = 1'b0; assign DCacheAccess = 1'b0; assign DCacheMiss = 1'b0; assign DCacheAccess = 1'b0;
end else begin : bus // *** lsubusdp end else begin : bus // *** lsubusdp
// Bus Side logic // Bus Side logic
// register the fetch data from the next level of memory. // register the fetch data from the next level of memory.
// This register should be necessary for timing. There is no register in the uncore or // This register should be necessary for timing. There is no register in the uncore or