From 4eb522123f3b8d1948ffab834f4a508c28e773fd Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 28 Mar 2024 16:24:45 -0500 Subject: [PATCH] Changed D suffix to Delay in ebufsmarb. --- src/ebu/ebufsmarb.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 55ba9a506..571bdcc63 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -51,7 +51,7 @@ module ebufsmarb ( statetype CurrState, NextState; logic both; // Both the LSU and IFU request at the same time - logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration + logic IFUReqDelay; // 1 cycle delayed IFU request. Part of arbitration logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst logic BeatCntEn; logic [3:0] BeatCount; // Position within a burst transfer @@ -85,11 +85,11 @@ module ebufsmarb ( // Controller 1 (LSU) // When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state. // Once the LSU request is done the fsm returns to IDLE. To prevent the LSU from regaining - // priority and re-issuing the same memory operation, the delayed IFUReqD squashes the LSU request. + // priority and re-issuing the same memory operation, the delayed IFUReqDelay squashes the LSU request. // This is necessary because the pipeline is stalled for the entire duration of both transactions, // and the LSU memory request will stil be active. - flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD); - assign LSUDisable = (CurrState == ARBITRATE) ? 1'b0 : (IFUReqD & ~(HREADY & FinalBeatD)); + flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqDelay); + assign LSUDisable = (CurrState == ARBITRATE) ? 1'b0 : (IFUReqDelay & ~(HREADY & FinalBeatD)); assign LSUSelect = (NextState == ARBITRATE) ? 1'b1: LSUReq; ////////////////////////////////////////////////////////////////////////////////////////////////////