From 4e54e5169b3c37b605717c842b4943b676b5c981 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 7 Jul 2023 18:22:28 -0500 Subject: [PATCH] Changes for xcelium. --- sim/wally.xrun | 2 ++ src/fpu/fdivsqrt/fdivsqrtfsm.sv | 2 +- src/mmu/pmpchecker.sv | 2 +- testbench/common/functionName.sv | 6 +++--- testbench/common/loggers.sv | 26 +++++++++++++++----------- testbench/common/shadowmem.sv | 8 ++++---- testbench/common/wallyTracer.sv | 2 +- testbench/testbench.sv | 2 +- 8 files changed, 28 insertions(+), 22 deletions(-) create mode 100644 sim/wally.xrun diff --git a/sim/wally.xrun b/sim/wally.xrun new file mode 100644 index 000000000..9e20e7fee --- /dev/null +++ b/sim/wally.xrun @@ -0,0 +1,2 @@ +xrun -setenv CADENCE_ENABLE_AVSREQ_44905_PHASE_1=1 -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench -compile ../src/cvw.sv ../testbench/testbench.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv +xrun -elaborate -top testbench ../testbench/testbench.sv -incdir ../config/rv64gc -incdir ../config/shared -incdir ../testbench diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index a727e5536..0e2cba90e 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -55,7 +55,7 @@ module fdivsqrtfsm import cvw::*; #(parameter cvw_t P) ( assign FDivBusyE = (state == BUSY) | IFDivStartE; // terminate immediately on special cases - assign FSpecialCaseE = XZeroE | | XInfE | XNaNE | (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE; + assign FSpecialCaseE = XZeroE | XInfE | XNaNE | (XsE&SqrtE) | (YZeroE | YInfE | YNaNE)&~SqrtE; if (P.IDIV_ON_FPU) assign SpecialCaseE = IntDivE ? ISpecialCaseE : FSpecialCaseE; else assign SpecialCaseE = FSpecialCaseE; flopenr #(1) SpecialCaseReg(clk, reset, IFDivStartE, SpecialCaseE, SpecialCaseM); // save SpecialCase for checking in fdivsqrtpostproc diff --git a/src/mmu/pmpchecker.sv b/src/mmu/pmpchecker.sv index fd1243031..89c22c486 100644 --- a/src/mmu/pmpchecker.sv +++ b/src/mmu/pmpchecker.sv @@ -67,7 +67,7 @@ module pmpchecker import cvw::*; #(parameter cvw_t P) ( priorityonehot #(P.PMP_ENTRIES) pmppriority(.a(Match), .y(FirstMatch)); // combine the match signal from all the adress decoders to find the first one that matches. // Only enforce PMP checking for S and U modes or in Machine mode when L bit is set in selected region - assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | |(L & FirstMatch); // *** switch to this logic when PMP is initialized for non-machine mode + assign EnforcePMP = (PrivilegeModeW != P.M_MODE) | (|(L & FirstMatch)); // *** switch to this logic when PMP is initialized for non-machine mode assign PMPInstrAccessFaultF = EnforcePMP & ExecuteAccessF & ~|(X & FirstMatch) ; assign PMPStoreAmoAccessFaultM = EnforcePMP & WriteAccessM & ~|(W & FirstMatch) ; diff --git a/testbench/common/functionName.sv b/testbench/common/functionName.sv index 90157f255..8498a425d 100644 --- a/testbench/common/functionName.sv +++ b/testbench/common/functionName.sv @@ -119,8 +119,8 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( // initial begin always @ (negedge reset) begin // clear out the old mapping between programs. - foreach(ProgramAddrMapMemory[i]) ProgramAddrMapMemory.delete(i); - foreach(ProgramLabelMapMemory[i]) ProgramLabelMapMemory.delete(i); + ProgramAddrMapMemory.delete(); + ProgramLabelMapMemory.delete(); $readmemh(ProgramAddrMapFile, ProgramAddrMapMemory); // we need to count the number of lines in the file so we can set FunctionRadixLineCount. @@ -169,7 +169,7 @@ module FunctionName import cvw::*; #(parameter cvw_t P) ( assign AnyUnknown = (OrReducedAdr === 1'bx) ? 1'b1 : 1'b0; initial ProgramAddrIndex = '0; - assign FunctionName = AnyUnknown ? "Unknown!" : ProgramLabelMapMemory[ProgramAddrIndex]; + always @(*) FunctionName = AnyUnknown ? "Unknown!" : ProgramLabelMapMemory[ProgramAddrIndex]; endmodule // function_radix diff --git a/testbench/common/loggers.sv b/testbench/common/loggers.sv index cf42fe4ec..18aa2de34 100644 --- a/testbench/common/loggers.sv +++ b/testbench/common/loggers.sv @@ -151,8 +151,10 @@ module loggers import cvw::*; #(parameter cvw_t P, $fwrite(file, "BEGIN %s\n", memfilename); end string AccessTypeString, HitMissString; - assign HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" : - dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M"; + always @(*) begin + HitMissString = dut.core.ifu.bus.icache.icache.CacheHit ? "H" : + dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M"; + end always @(posedge clk) begin if(resetEdge) $fwrite(file, "TRAIN\n"); if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename); @@ -174,15 +176,17 @@ module loggers import cvw::*; #(parameter cvw_t P, flop #(1) ResetDReg(clk, reset, resetD); assign resetEdge = ~reset & resetD; - assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" : - (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" : - dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E"; - assign AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" : - dut.core.lsu.bus.dcache.CacheAtomicM[1] ? "A" : - dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : - dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : - "NULL"; - + always @(*) begin + HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" : + (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" : + dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E"; + AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" : + dut.core.lsu.bus.dcache.CacheAtomicM[1] ? "A" : + dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : + dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : + "NULL"; + end + assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn & ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable & diff --git a/testbench/common/shadowmem.sv b/testbench/common/shadowmem.sv index 021d4b82f..19884390d 100644 --- a/testbench/common/shadowmem.sv +++ b/testbench/common/shadowmem.sv @@ -39,10 +39,10 @@ module DCacheFlushFSM import cvw::*; #(parameter cvw_t P) logic startD; if(P.DCACHE_SUPPORTED) begin - localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES; - localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS; - localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN; - localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN; + localparam numlines = P.DCACHE_WAYSIZEINBYTES*8/P.DCACHE_LINELENINBITS; + localparam numways = P.DCACHE_NUMWAYS; + localparam linelen = P.DCACHE_LINELENINBITS; + localparam linebytelen = linelen/8; localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN; localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM; localparam numwords = sramlen/P.XLEN; diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index a1dc318ec..66accfc9f 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -163,7 +163,7 @@ module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); CSRArray[12'h140] = testbench.dut.core.priv.priv.csr.csrs.csrs.SSCRATCH_REGW; CSRArray[12'h143] = testbench.dut.core.priv.priv.csr.csrs.csrs.STVAL_REGW; CSRArray[12'h142] = testbench.dut.core.priv.priv.csr.csrs.csrs.SCAUSE_REGW; - CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; + CSRArray[12'h144] = testbench.dut.core.priv.priv.csr.csrm.MIP_REGW & 12'h222 & testbench.dut.core.priv.priv.csr.csrm.MIDELEG_REGW; CSRArray[12'h14D] = testbench.dut.core.priv.priv.csr.csrs.csrs.STIMECMP_REGW; // user CSRs CSRArray[12'h001] = testbench.dut.core.priv.priv.csr.csru.csru.FFLAGS_REGW; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 0bcc34079..caa60e23c 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -466,7 +466,7 @@ module testbench; integer i; logic [31:0] sig32[0:SIGNATURESIZE]; logic [P.XLEN-1:0] signature[0:SIGNATURESIZE]; - string signame, pathname; + string signame; logic [P.XLEN-1:0] testadr, testadrNoBase; // for tests with no self checking mechanism, read .signature.output file and compare to check for errors