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Possible fix for ifu/lsu arbiration issue.
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@ -97,6 +97,8 @@ module ebu
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logic [2:0] LocalBurstType;
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logic CntReset;
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logic [3:0] Threshold;
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logic IFUReqD;
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assign HCLK = clk;
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assign HRESETn = ~reset;
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@ -195,7 +197,10 @@ module ebu
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// Controller 1 (LSU)
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assign save[1] = 1'b0;
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assign restore[1] = 1'b0;
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assign dis[1] = 1'b0;
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assign dis[1] = CurrState == ARBITRATE ? 1'b0 : (IFUReqD & ~(HREADY & FinalBeat));
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assign sel[1] = NextState == ARBITRATE ? 1'b1: LSUReq;
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flopr #(1) ifureqreg(clk, ~HRESETn, IFUReq, IFUReqD);
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endmodule
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