From 4d961bd0806a7a5fa8cb0da873ad7c4b53b05c4d Mon Sep 17 00:00:00 2001
From: Ross Thompson <ross1728@gmail.com>
Date: Fri, 26 May 2023 11:26:09 -0500
Subject: [PATCH] Completed LSU parameterization based on Lim's changes.
---
src/lsu/atomic.sv | 2 +-
src/lsu/lrsc.sv | 12 +++++-------
src/lsu/lsu.sv | 2 +-
src/lsu/subwordread.sv | 2 --
src/lsu/subwordwrite.sv | 12 +++++-------
src/lsu/swbytemask.sv | 6 ++----
6 files changed, 14 insertions(+), 22 deletions(-)
diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv
index 869cc2bb3..5c2035699 100644
--- a/src/lsu/atomic.sv
+++ b/src/lsu/atomic.sv
@@ -52,6 +52,6 @@ module atomic import cvw::*; #(parameter cvw_t P) (
mux2 #(P.XLEN) wdmux(IHWriteDataM, AMOResultM, LSUAtomicM[1], IMAWriteDataM);
assign MemReadM = PreLSURWM[1] & ~IgnoreRequest;
- lrsc lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
+ lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM);
endmodule
diff --git a/src/lsu/lrsc.sv b/src/lsu/lrsc.sv
index 5b4b37665..a1fbe6fdb 100644
--- a/src/lsu/lrsc.sv
+++ b/src/lsu/lrsc.sv
@@ -28,9 +28,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
-`include "wally-config.vh"
-
-module lrsc(
+module lrsc import cvw::*; #(parameter cvw_t P) (
input logic clk,
input logic reset,
input logic StallW,
@@ -38,20 +36,20 @@ module lrsc(
input logic [1:0] PreLSURWM, // Memory operation from the HPTW or IEU [1]: read, [0]: write
output logic [1:0] LSURWM, // Memory operation after potential squash of SC
input logic [1:0] LSUAtomicM, // Atomic memory operaiton
- input logic [`PA_BITS-1:0] PAdrM, // Physical memory address
+ input logic [P.PA_BITS-1:0] PAdrM, // Physical memory address
output logic SquashSCW // Squash the store conditional by not allowing rf write
);
// possible bug: *** double check if PreLSURWM needs to be flushed by ignorerequest.
// Handle atomic load reserved / store conditional
- logic [`PA_BITS-1:2] ReservationPAdrW;
+ logic [P.PA_BITS-1:2] ReservationPAdrW;
logic ReservationValidM, ReservationValidW;
logic lrM, scM, WriteAdrMatchM;
logic SquashSCM;
assign lrM = MemReadM & LSUAtomicM[0];
assign scM = PreLSURWM[0] & LSUAtomicM[0];
- assign WriteAdrMatchM = PreLSURWM[0] & (PAdrM[`PA_BITS-1:2] == ReservationPAdrW) & ReservationValidW;
+ assign WriteAdrMatchM = PreLSURWM[0] & (PAdrM[P.PA_BITS-1:2] == ReservationPAdrW) & ReservationValidW;
assign SquashSCM = scM & ~WriteAdrMatchM;
assign LSURWM = SquashSCM ? 2'b00 : PreLSURWM;
always_comb begin // ReservationValidM (next value of valid reservation)
@@ -61,7 +59,7 @@ module lrsc(
else ReservationValidM = ReservationValidW; // otherwise don't change valid
end
- flopenr #(`PA_BITS-2) resadrreg(clk, reset, lrM & ~StallW, PAdrM[`PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
+ flopenr #(P.PA_BITS-2) resadrreg(clk, reset, lrM & ~StallW, PAdrM[P.PA_BITS-1:2], ReservationPAdrW); // could drop clear on this one but not valid
flopenr #(1) resvldreg(clk, reset, ~StallW, ReservationValidM, ReservationValidW);
flopenr #(1) squashreg(clk, reset, ~StallW, SquashSCM, SquashSCW);
endmodule
diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv
index 94b52d1af..595f1eec4 100644
--- a/src/lsu/lsu.sv
+++ b/src/lsu/lsu.sv
@@ -337,7 +337,7 @@ module lsu import cvw::*; #(parameter cvw_t P) (
/////////////////////////////////////////////////////////////////////////////////////////////
subwordread #(P.LLEN) subwordread(.ReadDataWordMuxM(LittleEndianReadDataWordM), .PAdrM(PAdrM[2:0]), .BigEndianM,
.FpLoadStoreM, .Funct3M(LSUFunct3M), .ReadDataM);
- subwordwrite subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
+ subwordwrite #(P.LLEN) subwordwrite(.LSUFunct3M, .IMAFWriteDataM, .LittleEndianWriteDataM);
// Compute byte masks
swbytemask #(P.LLEN) swbytemask(.Size(LSUFunct3M), .Adr(PAdrM[$clog2(P.LLEN/8)-1:0]), .ByteMask(ByteMaskM));
diff --git a/src/lsu/subwordread.sv b/src/lsu/subwordread.sv
index 063df6a27..4c529ec07 100644
--- a/src/lsu/subwordread.sv
+++ b/src/lsu/subwordread.sv
@@ -27,8 +27,6 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
-`include "wally-config.vh"
-
module subwordread #(parameter LLEN)
(
input logic [LLEN-1:0] ReadDataWordMuxM,
diff --git a/src/lsu/subwordwrite.sv b/src/lsu/subwordwrite.sv
index ee26b78fd..f53f121e7 100644
--- a/src/lsu/subwordwrite.sv
+++ b/src/lsu/subwordwrite.sv
@@ -27,16 +27,14 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
-`include "wally-config.vh"
-
-module subwordwrite (
+module subwordwrite #(parameter LLEN) (
input logic [2:0] LSUFunct3M,
- input logic [`LLEN-1:0] IMAFWriteDataM,
- output logic [`LLEN-1:0] LittleEndianWriteDataM
+ input logic [LLEN-1:0] IMAFWriteDataM,
+ output logic [LLEN-1:0] LittleEndianWriteDataM
);
// Replicate data for subword writes
- if (`LLEN == 128) begin:sww
+ if (LLEN == 128) begin:sww
always_comb
case(LSUFunct3M[2:0])
3'b000: LittleEndianWriteDataM = {16{IMAFWriteDataM[7:0]}}; // sb
@@ -45,7 +43,7 @@ module subwordwrite (
3'b011: LittleEndianWriteDataM = {2{IMAFWriteDataM[63:0]}}; // sd
default: LittleEndianWriteDataM = IMAFWriteDataM; // sq
endcase
- end else if (`LLEN == 64) begin:sww
+ end else if (LLEN == 64) begin:sww
always_comb
case(LSUFunct3M[1:0])
2'b00: LittleEndianWriteDataM = {8{IMAFWriteDataM[7:0]}}; // sb
diff --git a/src/lsu/swbytemask.sv b/src/lsu/swbytemask.sv
index 17eedd4c4..51076fc7d 100644
--- a/src/lsu/swbytemask.sv
+++ b/src/lsu/swbytemask.sv
@@ -27,9 +27,7 @@
// and limitations under the License.
////////////////////////////////////////////////////////////////////////////////////////////////
-`include "wally-config.vh"
-
-module swbytemask #(parameter WORDLEN = `XLEN)(
+module swbytemask #(parameter WORDLEN)(
input logic [2:0] Size,
input logic [$clog2(WORDLEN/8)-1:0] Adr,
output logic [WORDLEN/8-1:0] ByteMask
@@ -39,7 +37,7 @@ module swbytemask #(parameter WORDLEN = `XLEN)(
/* Equivalent to the following
- if(`XLEN == 64) begin
+ if(WORDLEN == 64) begin
always_comb begin
case(Size[1:0])
2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1; end // sb