Add a comment to explain a detail

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Jarred Allen 2021-04-14 23:14:59 -04:00
parent c32fe09056
commit 4d58f673b2

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@ -68,6 +68,7 @@ module icache(
rodirectmappedmem #(.LINESIZE(ICACHELINESIZE), .NUMLINES(ICACHENUMLINES), .WORDSIZE(`XLEN)) cachemem( rodirectmappedmem #(.LINESIZE(ICACHELINESIZE), .NUMLINES(ICACHENUMLINES), .WORDSIZE(`XLEN)) cachemem(
.*, .*,
// Stall it if the pipeline is stalled, unless we're stalling it and we're ending our stall
.stall(StallF && (~ICacheStallF || ~EndFetchState)), .stall(StallF && (~ICacheStallF || ~EndFetchState)),
.flush(FlushMem), .flush(FlushMem),
.ReadUpperPAdr(ICacheMemReadUpperPAdr), .ReadUpperPAdr(ICacheMemReadUpperPAdr),