diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv
index 9f60a692f..8dae34f89 100755
--- a/src/fpu/fctrl.sv
+++ b/src/fpu/fctrl.sv
@@ -148,10 +148,10 @@ module fctrl import cvw::*;  #(parameter cvw_t P) (
                                   else if (Funct3D == 3'b000 & Rs2D == 5'b00000) 
                                                 ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_0; // fmv.x.w/d/h/q  fp to int register
                                   else if (P.ZFA_SUPPORTED & P.XLEN == 32 & P.D_SUPPORTED & Funct7D[1:0] == 2'b01 & Funct3D == 3'b000 & Rs2D == 5'b00001) 
-                                                  ControlsD = '0; // fmvh.x.d  (Zfa) *** needs values for all moves
+                                                  ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1; // fmvh.x.d  (Zfa) 
                                   // coverage off    Q not supported in RV64GC
                                   else if (P.ZFA_SUPPORTED & P.XLEN == 64 & P.Q_SUPPORTED & Funct7D[1:0] == 2'b11 & Funct3D == 3'b000 & Rs2D == 5'b00001) 
-                                                  ControlsD = '0; // fmvh.x.q  (Zfa)
+                                                  ControlsD = `FCTRLW'b0_1_11_00_000_0_0_0_1; // fmvh.x.q  (Zfa)
                                   // coverage on
                       7'b11110??: if (Funct3D == 3'b000 & Rs2D == 5'b00000) 
                                                 ControlsD = `FCTRLW'b1_0_00_00_011_0_0_0_0; // fmv.w/d/h/q.x  int to fp reg
diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv
index 430750c71..85ea9dba6 100755
--- a/src/fpu/fpu.sv
+++ b/src/fpu/fpu.sv
@@ -310,7 +310,8 @@ module fpu import cvw::*;  #(parameter cvw_t P) (
 
   // sign extend to XLEN if necessary
   if (P.FLEN>P.XLEN)
-    assign IntSrcXE = SgnExtXE[P.XLEN-1:0];
+    if (P.ZFA_SUPPORTED) assign IntSrcXE = ZfaE ? XE[P.FLEN-1:P.FLEN/2] : SgnExtXE[P.XLEN-1:0]; // either fmvh.x.* or fmv.x.*
+    else                 assign IntSrcXE = SgnExtXE[P.XLEN-1:0];
   else 
     assign IntSrcXE = {{P.XLEN-P.FLEN{mvsgn}}, SgnExtXE};
   mux3 #(P.XLEN) IntResMux (ClassResE, IntSrcXE, CmpIntResE, {~FResSelE[1], FResSelE[0]}, FIntResE);
diff --git a/testbench/tests.vh b/testbench/tests.vh
index 0c60228dd..7d2d320a8 100644
--- a/testbench/tests.vh
+++ b/testbench/tests.vh
@@ -2031,7 +2031,14 @@ string arch64zbs[] = '{
     "rv32i_m/D_Zfa/src/fmaxm_b1-01.S",
     "rv32i_m/D_Zfa/src/fmaxm_b19-01.S",
     "rv32i_m/D_Zfa/src/fmaxm.d_b1-01.S",
-    "rv32i_m/D_Zfa/src/fmaxm.d_b19-01.S"
+    "rv32i_m/D_Zfa/src/fmaxm.d_b19-01.S",
+    "rv32i_m/D_Zfa/src/fmvh.x.d_b1-01.S",
+    "rv32i_m/D_Zfa/src/fmvh.x.d_b22-01.S",
+    "rv32i_m/D_Zfa/src/fmvh.x.d_b23-01.S",
+    "rv32i_m/D_Zfa/src/fmvh.x.d_b24-01.S",
+    "rv32i_m/D_Zfa/src/fmvh.x.d_b27-01.S",
+    "rv32i_m/D_Zfa/src/fmvh.x.d_b28-01.S",
+    "rv32i_m/D_Zfa/src/fmvh.x.d_b29-01.S"
 /*    "rv32i_m/D_Zfa/src/fround_b1-01.S" */
   };