From 4cea8d1a29be64cd30c2d808d3d3f9bcb8f3e02c Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Thu, 9 Dec 2021 14:48:17 -0600 Subject: [PATCH] Performance counters now output of coremark. --- .../riscv64-baremetal/syscalls.c | 25 +++++++++++++++++-- .../config/coremark_bare/wally-config.vh | 7 +++--- 2 files changed, 26 insertions(+), 6 deletions(-) diff --git a/benchmarks/riscv-coremark/riscv64-baremetal/syscalls.c b/benchmarks/riscv-coremark/riscv64-baremetal/syscalls.c index 96a2f627b..8945385be 100644 --- a/benchmarks/riscv-coremark/riscv64-baremetal/syscalls.c +++ b/benchmarks/riscv-coremark/riscv64-baremetal/syscalls.c @@ -154,8 +154,29 @@ void _init(int cid, int nc) if (counters[i]) pbuf += sprintf(pbuf, "%s = %d\n", counter_names[i], counters[i]); if (pbuf != buf) - //printstr(buf); - ee_printf(buf); + printstr(buf); + counters[3] = read_csr(mhpmcounter3) - counters[3]; + counters[4] = read_csr(mhpmcounter4) - counters[4]; + counters[5] = read_csr(mhpmcounter5) - counters[5]; + counters[6] = read_csr(mhpmcounter6) - counters[6]; + counters[7] = read_csr(mhpmcounter7) - counters[7]; + counters[8] = read_csr(mhpmcounter8) - counters[8]; + counters[9] = read_csr(mhpmcounter9) - counters[9]; + counters[10] = read_csr(mhpmcounter10) - counters[10]; + counters[11] = read_csr(mhpmcounter11) - counters[11]; + counters[12] = read_csr(mhpmcounter12) - counters[12]; + + ee_printf("Load Stalls %d\n", counters[3]); + ee_printf("D-Cache Accesses %d\n", counters[11]); + ee_printf("D-Cache Misses %d\n", counters[12]); + ee_printf("Branches %d\n", counters[5]); + ee_printf("Branches Miss Predictions %d\n", counters[4]); + ee_printf("BTB Misses %d\n", counters[6]); + ee_printf("Jump, JAL, JALR %d\n", counters[7]); + ee_printf("RAS Wrong %d\n", counters[8]); + ee_printf("Returns %d\n", counters[9]); + ee_printf("BP Class Wrong %d\n", counters[10]); + ee_printf("Done printing performance counters\n"); exit(ret); } diff --git a/wally-pipelined/config/coremark_bare/wally-config.vh b/wally-pipelined/config/coremark_bare/wally-config.vh index ae479a25b..0adca26be 100644 --- a/wally-pipelined/config/coremark_bare/wally-config.vh +++ b/wally-pipelined/config/coremark_bare/wally-config.vh @@ -37,7 +37,7 @@ //`define MISA (32'h00000104) //`define MISA (32'h00001104 | 1<<5 | 1<<18 | 1 << 20 | 1 << 12 | 1 << 0) -`define MISA (32'h00000104 | 0 << 5 | 0 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) +`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0) `define ZICSR_SUPPORTED 1 `define ZIFENCEI_SUPPORTED 1 `define COUNTERS 32 @@ -62,10 +62,9 @@ // Cache configuration. Sizes should be a power of two // typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks `define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 2048 +`define DCACHE_WAYSIZEINBYTES 4096 `define DCACHE_BLOCKLENINBITS 256 -`define DCACHE_REPLBITS 3 -`define ICACHE_NUMWAYS 1 +`define ICACHE_NUMWAYS 4 `define ICACHE_WAYSIZEINBYTES 4096 `define ICACHE_BLOCKLENINBITS 256