From 4c7eb1d11f4c863753730f36063e7991356ab363 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Fri, 11 Oct 2024 15:41:40 -0500 Subject: [PATCH] Renamed IgnoreRequestTLB to HPTWFlushW and IgnoreRequest to LSUFlushW. --- src/lsu/atomic.sv | 4 ++-- src/lsu/lsu.sv | 22 +++++++++++----------- src/mmu/hptw.sv | 6 ++---- 3 files changed, 15 insertions(+), 17 deletions(-) diff --git a/src/lsu/atomic.sv b/src/lsu/atomic.sv index 9c37b636c..8ad9159ce 100644 --- a/src/lsu/atomic.sv +++ b/src/lsu/atomic.sv @@ -39,7 +39,7 @@ module atomic import cvw::*; #(parameter cvw_t P) ( input logic [2:0] LSUFunct3M, // IEU or HPTW memory operation size input logic [1:0] LSUAtomicM, // 10: AMO operation, select AMOResultM as the writedata output, 01: LR/SC operation input logic [1:0] PreLSURWM, // IEU or HPTW Read/Write signal - input logic IgnoreRequest, // On FlushM or TLB miss ignore memory operation + input logic LSUFlushW, // On FlushM or TLB miss ignore memory operation output logic [P.XLEN-1:0] IMAWriteDataM, // IEU, HPTW, or AMO write data output logic SquashSCW, // Store conditional failed disable write to GPR output logic [1:0] LSURWM // IEU or HPTW Read/Write signal gated by LR/SC @@ -57,7 +57,7 @@ module atomic import cvw::*; #(parameter cvw_t P) ( // LRSC unit if (P.ZALRSC_SUPPORTED) begin - assign MemReadM = PreLSURWM[1] & ~IgnoreRequest; + assign MemReadM = PreLSURWM[1] & ~LSUFlushW; lrsc #(P) lrsc(.clk, .reset, .StallW, .MemReadM, .PreLSURWM, .LSUAtomicM, .PAdrM, .SquashSCW, .LSURWM); end else begin assign SquashSCW = 0; diff --git a/src/lsu/lsu.sv b/src/lsu/lsu.sv index 51f4d9d6e..08e62f9ad 100644 --- a/src/lsu/lsu.sv +++ b/src/lsu/lsu.sv @@ -110,7 +110,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic GatedStallW; // Hazard unit StallW gated when SelHPTW = 1 - logic LSUBusStallM; // Bus interface busy with multicycle operation masked by IgnoreRequestTLB + logic LSUBusStallM; // Bus interface busy with multicycle operation masked by HPTWFlushW logic HPTWStall; // HPTW busy with multicycle operation logic DCacheBusStallM; // Cache or bus stall logic CacheBusHPWTStall; // Cache, bus, or hptw is requesting a stall @@ -145,8 +145,8 @@ module lsu import cvw::*; #(parameter cvw_t P) ( logic DTLBWriteM; // Writes PTE and PageType to DTLB logic LSULoadAccessFaultM; // Load acces fault logic LSUStoreAmoAccessFaultM; // Store access fault - logic IgnoreRequestTLB; // On either ITLB or DTLB miss, ignore miss so HPTW can handle - logic IgnoreRequest; // On FlushM or TLB miss ignore memory operation + logic HPTWFlushW; // HPTW needs to flush operation + logic LSUFlushW; // HPTW or hazard unit flushes operation logic SelDTIM; // Select DTIM rather than bus or D$ logic [P.XLEN-1:0] WriteDataZM; logic LSULoadPageFaultM, LSUStoreAmoPageFaultM; @@ -199,7 +199,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .WriteDataM(WriteDataZM), .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M, .IEUAdrExtM, .PTE, .IHWriteDataM, .PageType, .PreLSURWM, .LSUAtomicM, .IHAdrM, .HPTWStall, .SelHPTW, - .IgnoreRequestTLB, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM, + .HPTWFlushW, .LSULoadAccessFaultM, .LSUStoreAmoAccessFaultM, .LoadAccessFaultM, .StoreAmoAccessFaultM, .HPTWInstrAccessFaultF, .LoadPageFaultM, .StoreAmoPageFaultM, .LSULoadPageFaultM, .LSUStoreAmoPageFaultM, .HPTWInstrPageFaultF ); @@ -214,7 +214,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign StoreAmoAccessFaultM = LSUStoreAmoAccessFaultM; assign LoadPageFaultM = LSULoadPageFaultM; assign StoreAmoPageFaultM = LSUStoreAmoPageFaultM; - assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, IgnoreRequestTLB} = '0; + assign {HPTWStall, SelHPTW, PTE, PageType, DTLBWriteM, ITLBWriteF, HPTWFlushW} = '0; assign {HPTWInstrAccessFaultF, HPTWInstrPageFaultF} = '0; end @@ -273,7 +273,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( // Pause IEU memory request if TLB miss. After TLB fill, replay request. // Discard memory request on pipeline flush - assign IgnoreRequest = IgnoreRequestTLB | FlushW; + assign LSUFlushW = HPTWFlushW | FlushW; if (P.DTIM_SUPPORTED) begin : dtim logic [P.PA_BITS-1:0] DTIMAdr; @@ -284,7 +284,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign DTIMMemRWM = SelDTIM ? LSURWM : 0; dtim #(P) dtim(.clk, .reset, .ce(~GatedStallW), .MemRWM(DTIMMemRWM), - .DTIMAdr, .FlushW(IgnoreRequest), .WriteDataM(LSUWriteDataM), + .DTIMAdr, .FlushW(LSUFlushW), .WriteDataM(LSUWriteDataM), .ReadDataWordM(DTIMReadDataWordM[P.LLEN-1:0]), .ByteMaskM(ByteMaskM)); end else assign DTIMReadDataWordM = '0; @@ -328,7 +328,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( cache #(.P(P), .PA_BITS(P.PA_BITS), .XLEN(P.XLEN), .LINELEN(P.DCACHE_LINELENINBITS), .NUMSETS(P.DCACHE_WAYSIZEINBYTES*8/LINELEN), .NUMWAYS(P.DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(CACHEWORDLEN), .MUXINTERVAL(P.LLEN), .READ_ONLY_CACHE(0)) dcache( - .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(IgnoreRequest), + .clk, .reset, .Stall(GatedStallW & ~SelSpillE), .SelBusBeat, .FlushStage(LSUFlushW), .CacheRW(CacheRWM), .FlushCache(FlushDCache), .NextSet(IEUAdrExtE[11:0]), .PAdr(PAdrM), .ByteMask(ByteMaskSpillM), .BeatCount(BeatCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]), @@ -340,7 +340,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0), .CMOpM(CacheCMOpM)); ahbcacheinterface #(.P(P), .BEATSPERLINE(BEATSPERLINE), .AHBWLOGBWPL(AHBWLOGBWPL), .LINELEN(LINELEN), .LLENPOVERAHBW(LLENPOVERAHBW), .READ_ONLY_CACHE(0)) ahbcacheinterface( - .HCLK(clk), .HRESETn(~reset), .Flush(IgnoreRequest), + .HCLK(clk), .HRESETn(~reset), .Flush(LSUFlushW), .HRDATA, .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HREADY(LSUHREADY), .BeatCount, .SelBusBeat, .CacheReadDataWordM(DCacheReadDataWordM[P.LLEN-1:0]), .WriteDataM(LSUWriteDataM), @@ -360,7 +360,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( assign LSUHADDR = PAdrM; assign LSUHSIZE = LSUFunct3M; - ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(IgnoreRequest), .HREADY(LSUHREADY), + ahbinterface #(P.XLEN, 1'b1) ahbinterface(.HCLK(clk), .HRESETn(~reset), .Flush(LSUFlushW), .HREADY(LSUHREADY), .HRDATA(HRDATA), .HTRANS(LSUHTRANS), .HWRITE(LSUHWRITE), .HWDATA(LSUHWDATA), .HWSTRB(LSUHWSTRB), .BusRW, .BusAtomic(AtomicM[1]), .ByteMask(ByteMaskM[P.XLEN/8-1:0]), .WriteData(LSUWriteDataM[P.XLEN-1:0]), .Stall(GatedStallW), .BusStall(LSUBusStallM), .BusCommitted(BusCommittedM), .FetchBuffer(FetchBuffer)); @@ -386,7 +386,7 @@ module lsu import cvw::*; #(parameter cvw_t P) ( if (P.ZAAMO_SUPPORTED | P.ZALRSC_SUPPORTED) begin:atomic atomic #(P) atomic(.clk, .reset, .StallW, .ReadDataM(ReadDataM[P.XLEN-1:0]), .IHWriteDataM, .PAdrM, - .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .IgnoreRequest, + .LSUFunct7M, .LSUFunct3M, .LSUAtomicM, .PreLSURWM, .LSUFlushW, .IMAWriteDataM, .SquashSCW, .LSURWM); end else begin:lrsc assign SquashSCW = 1'b0; diff --git a/src/mmu/hptw.sv b/src/mmu/hptw.sv index e48bf85dd..4e9003dc3 100644 --- a/src/mmu/hptw.sv +++ b/src/mmu/hptw.sv @@ -58,7 +58,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( output logic [1:0] LSUAtomicM, output logic [2:0] LSUFunct3M, output logic [6:0] LSUFunct7M, - output logic IgnoreRequestTLB, + output logic HPTWFlushW, output logic SelHPTW, output logic HPTWStall, input logic LSULoadAccessFaultM, LSUStoreAmoAccessFaultM, @@ -304,9 +304,7 @@ module hptw import cvw::*; #(parameter cvw_t P) ( default: NextWalkerState = IDLE; // Should never be reached endcase // case (WalkerState) - assign IgnoreRequestTLB = (WalkerState == IDLE & TLBMissOrUpdateDA) | - //((WalkerState == L3_RD | WalkerState == L2_RD | WalkerState == L1_RD | WalkerState == L0_RD) & HPTWFaultM); // HPTWFaultM is hear because the hptw faults are delayed one cycle and we need to prevent the cache/bus from taking the operation. On the next cycle the CPU will trap. - (WalkerState != IDLE & HPTWFaultM); + assign HPTWFlushW = (WalkerState == IDLE & TLBMissOrUpdateDA) | (WalkerState != IDLE & HPTWFaultM); assign ResetPTE = reset | (NextWalkerState == IDLE); assign SelHPTW = WalkerState != IDLE;