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LSU cleanup
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37bf5347cf
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@ -346,12 +346,13 @@ module lsu
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.HCLK(clk), .HRESETn(~reset),
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.HCLK(clk), .HRESETn(~reset),
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.HSELRam(1'b1), .HADDR(LSUPAdrM[31:0]),
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.HSELRam(1'b1), .HADDR(LSUPAdrM[31:0]),
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.HWRITE(LSURWM[0]), .HREADY(1'b1),
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.HWRITE(LSURWM[0]), .HREADY(1'b1),
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.HTRANS(|LSURWM ? 2'b10 : 2'b00), .HWDATA(FinalWriteDataM), .HREADRam(ReadDataWordMuxM),
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.HTRANS(|LSURWM ? 2'b10 : 2'b00), .HWDATA(FinalWriteDataM), .HREADRam(ReadDataWordM),
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.HRESPRam(), .HREADYRam());
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.HRESPRam(), .HREADYRam());
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// since we have a local memory the bus connections are all disabled.
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// since we have a local memory the bus connections are all disabled.
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// There are no peripherals supported.
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// There are no peripherals supported.
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assign {BusStall, LSUBusWrite, LSUBusRead, DCacheBusAck, BusCommittedM, SelUncachedAdr} = '0;
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assign {BusStall, LSUBusWrite, LSUBusRead, DCacheBusAck, BusCommittedM, SelUncachedAdr} = '0;
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assign ReadDataWordMuxM = ReadDataWordM;
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end else begin : bus // *** lsubusdp
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end else begin : bus // *** lsubusdp
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// Bus Side logic
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// Bus Side logic
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// register the fetch data from the next level of memory.
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// register the fetch data from the next level of memory.
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