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LSU cleanup

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This commit is contained in:
David Harris 2022-01-15 00:03:03 +00:00
parent 37bf5347cf
commit 4c5962095e
1 changed files with 2 additions and 1 deletions
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3
pipelined/src/lsu/lsu.sv
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@ -346,12 +346,13 @@ module lsu
.HCLK(clk), .HRESETn(~reset), .HCLK(clk), .HRESETn(~reset),
.HSELRam(1'b1), .HADDR(LSUPAdrM[31:0]), .HSELRam(1'b1), .HADDR(LSUPAdrM[31:0]),
.HWRITE(LSURWM[0]), .HREADY(1'b1), .HWRITE(LSURWM[0]), .HREADY(1'b1),
.HTRANS(|LSURWM ? 2'b10 : 2'b00), .HWDATA(FinalWriteDataM), .HREADRam(ReadDataWordMuxM), .HTRANS(|LSURWM ? 2'b10 : 2'b00), .HWDATA(FinalWriteDataM), .HREADRam(ReadDataWordM),
.HRESPRam(), .HREADYRam()); .HRESPRam(), .HREADYRam());
// since we have a local memory the bus connections are all disabled. // since we have a local memory the bus connections are all disabled.
// There are no peripherals supported. // There are no peripherals supported.
assign {BusStall, LSUBusWrite, LSUBusRead, DCacheBusAck, BusCommittedM, SelUncachedAdr} = '0; assign {BusStall, LSUBusWrite, LSUBusRead, DCacheBusAck, BusCommittedM, SelUncachedAdr} = '0;
assign ReadDataWordMuxM = ReadDataWordM;
end else begin : bus // *** lsubusdp end else begin : bus // *** lsubusdp
// Bus Side logic // Bus Side logic
// register the fetch data from the next level of memory. // register the fetch data from the next level of memory.