mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-02 09:45:18 +00:00
Update device tree isa format to supported form and add all supported extensions
This commit is contained in:
parent
3c6c997d05
commit
4c338e9fb8
@ -5,7 +5,7 @@
|
|||||||
#size-cells = <0x02>;
|
#size-cells = <0x02>;
|
||||||
compatible = "wally-virt";
|
compatible = "wally-virt";
|
||||||
model = "wally-virt,qemu";
|
model = "wally-virt,qemu";
|
||||||
|
|
||||||
chosen {
|
chosen {
|
||||||
linux,initrd-end = <0x85c43a00>;
|
linux,initrd-end = <0x85c43a00>;
|
||||||
linux,initrd-start = <0x84200000>;
|
linux,initrd-start = <0x84200000>;
|
||||||
@ -30,9 +30,10 @@
|
|||||||
reg = <0x00>;
|
reg = <0x00>;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
compatible = "riscv";
|
compatible = "riscv";
|
||||||
riscv,isa = "rv64imafdcsu";
|
|
||||||
riscv,isa-base = "rv64i";
|
riscv,isa-base = "rv64i";
|
||||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
|
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm",
|
||||||
|
riscv,cbop-block-size = <64>;
|
||||||
|
riscv,cboz-block-size = <64>;
|
||||||
riscv,cbom-block-size = <64>;
|
riscv,cbom-block-size = <64>;
|
||||||
mmu-type = "riscv,sv48";
|
mmu-type = "riscv,sv48";
|
||||||
|
|
||||||
|
@ -30,9 +30,10 @@
|
|||||||
reg = <0x00>;
|
reg = <0x00>;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
compatible = "riscv";
|
compatible = "riscv";
|
||||||
riscv,isa = "rv64imafdcsu";
|
|
||||||
riscv,isa-base = "rv64i";
|
riscv,isa-base = "rv64i";
|
||||||
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
|
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm",
|
||||||
|
riscv,cbop-block-size = <64>;
|
||||||
|
riscv,cboz-block-size = <64>;
|
||||||
riscv,cbom-block-size = <64>;
|
riscv,cbom-block-size = <64>;
|
||||||
mmu-type = "riscv,sv48";
|
mmu-type = "riscv,sv48";
|
||||||
|
|
||||||
|
@ -9,7 +9,7 @@
|
|||||||
chosen {
|
chosen {
|
||||||
linux,initrd-end = <0x85c43a00>;
|
linux,initrd-end = <0x85c43a00>;
|
||||||
linux,initrd-start = <0x84200000>;
|
linux,initrd-start = <0x84200000>;
|
||||||
bootargs = "root=/dev/vda ro console=ttyS0,115200";
|
bootargs = "root=/dev/vda ro console=ttyS0,115200";
|
||||||
stdout-path = "/soc/uart@10000000";
|
stdout-path = "/soc/uart@10000000";
|
||||||
};
|
};
|
||||||
|
|
||||||
@ -30,8 +30,11 @@
|
|||||||
reg = <0x00>;
|
reg = <0x00>;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
compatible = "riscv";
|
compatible = "riscv";
|
||||||
riscv,isa = "rv64imafdcsu";
|
riscv,isa-base = "rv64i";
|
||||||
riscv,isa-extensions = "imafdc", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
|
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm",
|
||||||
|
riscv,cbop-block-size = <64>;
|
||||||
|
riscv,cboz-block-size = <64>;
|
||||||
|
riscv,cbom-block-size = <64>;
|
||||||
mmu-type = "riscv,sv48";
|
mmu-type = "riscv,sv48";
|
||||||
|
|
||||||
interrupt-controller {
|
interrupt-controller {
|
||||||
|
@ -15,7 +15,7 @@
|
|||||||
|
|
||||||
memory@80000000 {
|
memory@80000000 {
|
||||||
device_type = "memory";
|
device_type = "memory";
|
||||||
reg = <0x00 0x80000000 0x00 0x10000000>;
|
reg = <0x00 0x80000000 0x00 0x10000000>;
|
||||||
};
|
};
|
||||||
|
|
||||||
cpus {
|
cpus {
|
||||||
@ -30,8 +30,11 @@
|
|||||||
reg = <0x00>;
|
reg = <0x00>;
|
||||||
status = "okay";
|
status = "okay";
|
||||||
compatible = "riscv";
|
compatible = "riscv";
|
||||||
riscv,isa = "rv64imafdcsu";
|
riscv,isa-base = "rv64i";
|
||||||
riscv,isa-extensions = "svadu";
|
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm",
|
||||||
|
riscv,cbop-block-size = <64>;
|
||||||
|
riscv,cboz-block-size = <64>;
|
||||||
|
riscv,cbom-block-size = <64>;
|
||||||
mmu-type = "riscv,sv48";
|
mmu-type = "riscv,sv48";
|
||||||
|
|
||||||
interrupt-controller {
|
interrupt-controller {
|
||||||
|
Loading…
Reference in New Issue
Block a user