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https://github.com/openhwgroup/cvw
synced 2025-01-22 20:44:28 +00:00
Update device tree isa format to supported form and add all supported extensions
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parent
3c6c997d05
commit
4c338e9fb8
@ -5,7 +5,7 @@
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#size-cells = <0x02>;
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compatible = "wally-virt";
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model = "wally-virt,qemu";
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chosen {
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linux,initrd-end = <0x85c43a00>;
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linux,initrd-start = <0x84200000>;
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@ -30,9 +30,10 @@
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reg = <0x00>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsu";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm",
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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riscv,cbom-block-size = <64>;
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mmu-type = "riscv,sv48";
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@ -30,9 +30,10 @@
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reg = <0x00>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsu";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm",
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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riscv,cbom-block-size = <64>;
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mmu-type = "riscv,sv48";
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@ -9,7 +9,7 @@
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chosen {
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linux,initrd-end = <0x85c43a00>;
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linux,initrd-start = <0x84200000>;
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bootargs = "root=/dev/vda ro console=ttyS0,115200";
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bootargs = "root=/dev/vda ro console=ttyS0,115200";
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stdout-path = "/soc/uart@10000000";
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};
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@ -30,8 +30,11 @@
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reg = <0x00>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsu";
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riscv,isa-extensions = "imafdc", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm",
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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riscv,cbom-block-size = <64>;
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mmu-type = "riscv,sv48";
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interrupt-controller {
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@ -15,7 +15,7 @@
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memory@80000000 {
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device_type = "memory";
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reg = <0x00 0x80000000 0x00 0x10000000>;
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reg = <0x00 0x80000000 0x00 0x10000000>;
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};
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cpus {
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@ -30,8 +30,11 @@
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reg = <0x00>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsu";
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riscv,isa-extensions = "svadu";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm",
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riscv,cbop-block-size = <64>;
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riscv,cboz-block-size = <64>;
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riscv,cbom-block-size = <64>;
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mmu-type = "riscv,sv48";
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interrupt-controller {
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