Update device tree isa format to supported form and add all supported extensions

This commit is contained in:
Jordan Carlin 2025-01-05 00:40:40 -08:00
parent 3c6c997d05
commit 4c338e9fb8
No known key found for this signature in database
4 changed files with 19 additions and 11 deletions

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@ -5,7 +5,7 @@
#size-cells = <0x02>;
compatible = "wally-virt";
model = "wally-virt,qemu";
chosen {
linux,initrd-end = <0x85c43a00>;
linux,initrd-start = <0x84200000>;
@ -30,9 +30,10 @@
reg = <0x00>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcsu";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm",
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
riscv,cbom-block-size = <64>;
mmu-type = "riscv,sv48";

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@ -30,9 +30,10 @@
reg = <0x00>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcsu";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm",
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
riscv,cbom-block-size = <64>;
mmu-type = "riscv,sv48";

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@ -9,7 +9,7 @@
chosen {
linux,initrd-end = <0x85c43a00>;
linux,initrd-start = <0x84200000>;
bootargs = "root=/dev/vda ro console=ttyS0,115200";
bootargs = "root=/dev/vda ro console=ttyS0,115200";
stdout-path = "/soc/uart@10000000";
};
@ -30,8 +30,11 @@
reg = <0x00>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcsu";
riscv,isa-extensions = "imafdc", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm",
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
riscv,cbom-block-size = <64>;
mmu-type = "riscv,sv48";
interrupt-controller {

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@ -15,7 +15,7 @@
memory@80000000 {
device_type = "memory";
reg = <0x00 0x80000000 0x00 0x10000000>;
reg = <0x00 0x80000000 0x00 0x10000000>;
};
cpus {
@ -30,8 +30,11 @@
reg = <0x00>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdcsu";
riscv,isa-extensions = "svadu";
riscv,isa-base = "rv64i";
riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svadu", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zca", "zcb", "zcd", "zfa", "zfh", "zkn", "zkt", "zicbom", "zicbop", "zicboz", "zicntr", "zicond", "zicsr", "zifencei", "zihpm",
riscv,cbop-block-size = <64>;
riscv,cboz-block-size = <64>;
riscv,cbom-block-size = <64>;
mmu-type = "riscv,sv48";
interrupt-controller {