From 4c2ba2b0b45ec0afa84f51b6bbeb68f2a7dfe8d7 Mon Sep 17 00:00:00 2001 From: Rose Thompson Date: Thu, 18 Jan 2024 14:43:34 -0600 Subject: [PATCH] Added StoreStall back to csrc. --- src/ieu/controller.sv | 2 +- src/ieu/ieu.sv | 3 ++- src/privileged/csr.sv | 4 ++-- src/privileged/csrc.sv | 8 ++++++-- src/privileged/privileged.sv | 3 ++- src/wally/wallypipelinedcore.sv | 5 +++-- 6 files changed, 16 insertions(+), 9 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index e5cfff9ed..35da15efe 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -41,6 +41,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic BranchD, // Branch instruction output logic StructuralStallD, // Structural stalls detected by controller output logic LoadStallD, // Structural stalls for load, sent to performance counters + output logic StoreStallD, // load after store hazard output logic [4:0] Rs1D, Rs2D, // Register sources to read in Decode or Execute stage // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage @@ -158,7 +159,6 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic CMOStallD; // Structural hazards from cache management ops logic MatchDE; // Match between a source register in Decode stage and destination register in Execute stage logic FCvtIntStallD, MDUStallD, CSRRdStallD; // Stall due to conversion, load, multiply/divide, CSR read - logic StoreStallD; // load after store hazard logic FunctCZeroD; // Funct7 and Funct3 indicate czero.* (not including Op check) // Extract fields diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 870a37963..ddd6fe089 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -75,6 +75,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( input logic FlushD, FlushE, FlushM, FlushW, // Flush signals output logic StructuralStallD, // IEU detects structural hazard in Decode stage output logic LoadStallD, // Structural stalls for load, sent to performance counters + output logic StoreStallD, // load after store hazard output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction output logic CSRWriteFenceM // CSR write or fence instruction needs to flush subsequent instructions ); @@ -106,7 +107,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( controller #(P) c( .clk, .reset, .StallD, .FlushD, .InstrD, .STATUS_FS, .ENVCFG_CBE, .ImmSrcD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, - .StructuralStallD, .LoadStallD, .Rs1D, .Rs2D, + .StructuralStallD, .LoadStallD, .StoreStallD, .Rs1D, .Rs2D, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, diff --git a/src/privileged/csr.sv b/src/privileged/csr.sv index e43712d81..9405cfdb9 100644 --- a/src/privileged/csr.sv +++ b/src/privileged/csr.sv @@ -53,7 +53,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( input logic [3:0] CauseM, // Trap cause input logic SelHPTW, // hardware page table walker active, so base endianness on supervisor mode // inputs for performance counters - input logic LoadStallD, + input logic LoadStallD, StoreStallD, input logic ICacheStallF, input logic DCacheStallM, input logic BPDirPredWrongM, @@ -274,7 +274,7 @@ module csr import cvw::*; #(parameter cvw_t P) ( if (P.ZICNTR_SUPPORTED) begin:counters csrc #(P) counters(.clk, .reset, .StallE, .StallM, .FlushM, - .InstrValidNotFlushedM, .LoadStallD, .CSRWriteM, .CSRMWriteM, + .InstrValidNotFlushedM, .LoadStallD, .StoreStallD, .CSRWriteM, .CSRMWriteM, .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .IClassWrongM, .BPWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .sfencevmaM, .InterruptM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE, diff --git a/src/privileged/csrc.sv b/src/privileged/csrc.sv index c3dbf1f6b..bc8768f47 100644 --- a/src/privileged/csrc.sv +++ b/src/privileged/csrc.sv @@ -32,7 +32,7 @@ module csrc import cvw::*; #(parameter cvw_t P) ( input logic clk, reset, input logic StallE, StallM, input logic FlushM, - input logic InstrValidNotFlushedM, LoadStallD, + input logic InstrValidNotFlushedM, LoadStallD, StoreStallD, input logic CSRMWriteM, CSRWriteM, input logic BPDirPredWrongM, input logic BTAWrongM, @@ -75,6 +75,7 @@ module csrc import cvw::*; #(parameter cvw_t P) ( logic [P.XLEN-1:0] HPMCOUNTER_REGW[P.COUNTERS-1:0]; logic [P.XLEN-1:0] HPMCOUNTERH_REGW[P.COUNTERS-1:0]; logic LoadStallE, LoadStallM; + logic StoreStallE, StoreStallM; logic [P.COUNTERS-1:0] WriteHPMCOUNTERM; logic [P.COUNTERS-1:0] CounterEvent; logic [63:0] HPMCOUNTERPlusM[P.COUNTERS-1:0]; @@ -84,6 +85,9 @@ module csrc import cvw::*; #(parameter cvw_t P) ( // Interface signals flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(LoadStallD), .q(LoadStallE)); // don't flush the load stall during a load stall. flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM)); + + flopenrc #(1) StoreStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(StoreStallD), .q(StoreStallE)); // don't flush the load stall during a load stall. + flopenrc #(1) StoreStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(StoreStallE), .q(StoreStallM)); // Determine when to increment each counter assign CounterEvent[0] = 1'b1; // MCYCLE always increments @@ -99,7 +103,7 @@ module csrc import cvw::*; #(parameter cvw_t P) ( assign CounterEvent[9] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address assign CounterEvent[10] = IClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong assign CounterEvent[11] = LoadStallM; // Load Stalls. don't want to suppress on flush as this only happens if flushed. - assign CounterEvent[12] = 0; // depricated Store Stall + assign CounterEvent[12] = StoreStallM; // depricated Store Stall assign CounterEvent[13] = DCacheAccess; // data cache access assign CounterEvent[14] = DCacheMiss; // data cache miss. Miss asserted 1 cycle at start of cache miss assign CounterEvent[15] = DCacheStallM; // d cache miss cycles diff --git a/src/privileged/privileged.sv b/src/privileged/privileged.sv index 2d217b6d6..063504730 100644 --- a/src/privileged/privileged.sv +++ b/src/privileged/privileged.sv @@ -45,6 +45,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( // processor events for performance counter logging input logic FRegWriteM, // instruction will write floating-point registers input logic LoadStallD, // load instruction is stalling + input logic StoreStallD, // store instruction is stalling input logic ICacheStallF, // I cache stalled input logic DCacheStallM, // D cache stalled input logic BPDirPredWrongM, // branch predictor guessed wrong direction @@ -134,7 +135,7 @@ module privileged import cvw::*; #(parameter cvw_t P) ( .InstrM, .InstrOrigM, .PCM, .SrcAM, .IEUAdrM, .CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .InterruptM, .MTimerInt, .MExtInt, .SExtInt, .MSwInt, - .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, + .MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD, .StoreStallD, .BPDirPredWrongM, .BTAWrongM, .RASPredPCWrongM, .BPWrongM, .sfencevmaM, .ExceptionM, .InvalidateICacheM, .ICacheStallF, .DCacheStallM, .DivBusyE, .FDivBusyE, .IClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 79c4364cb..9f84cc7bf 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -77,6 +77,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic DivBusyE; logic StructuralStallD; logic LoadStallD; + logic StoreStallD; logic SquashSCW; logic MDUActiveE; // Mul/Div instruction being executed logic ENVCFG_ADUE; // HPTW A/D Update enable @@ -211,7 +212,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW, // hazards .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .StructuralStallD, .LoadStallD, .PCSrcE, + .StructuralStallD, .LoadStallD, .StoreStallD, .PCSrcE, .CSRReadM, .CSRWriteM, .PrivilegedM, .CSRWriteFenceM, .InvalidateICacheM); lsu #(P) lsu( @@ -285,7 +286,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .InstrM, .InstrOrigM, .CSRReadValW, .EPCM, .TrapVectorM, .RetM, .TrapM, .sfencevmaM, .InvalidateICacheM, .DCacheStallM, .ICacheStallF, .InstrValidM, .CommittedM, .CommittedF, - .FRegWriteM, .LoadStallD, + .FRegWriteM, .LoadStallD, .StoreStallD, .BPDirPredWrongM, .BTAWrongM, .BPWrongM, .RASPredPCWrongM, .IClassWrongM, .DivBusyE, .FDivBusyE, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,