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Design loads in modelsim, but trap is an X.

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This commit is contained in:
Ross Thompson 2021-07-09 15:37:16 -05:00
parent ec80cc1820
commit 4c0cee1c19
2 changed files with 8 additions and 11 deletions
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2
wally-pipelined/src/cache/DCacheMem.sv vendored
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@ -89,6 +89,6 @@ module DCacheMem #(parameter NUMLINES=512, parameter BLOCKLEN = 256, TAGLEN = 26
end end
endmodule; // DCacheMemWay endmodule // DCacheMemWay

17
wally-pipelined/src/cache/dcache.sv vendored
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@ -88,7 +88,7 @@ module dcache
logic [NUMWAYS-1:0] Valid, Dirty, WayHit; logic [NUMWAYS-1:0] Valid, Dirty, WayHit;
logic CacheHit; logic CacheHit;
logic [NUMREPL_BITS-1:0] ReplacementBits [NUMLINES-1:0]; logic [NUMREPL_BITS-1:0] ReplacementBits [NUMLINES-1:0];
logic [NUMREPL_BITS-1:0] NewReplacement [NUMLINES-1:0]; logic [NUMREPL_BITS-1:0] NewReplacement;
logic [BLOCKLEN-1:0] ReadDataBlockM; logic [BLOCKLEN-1:0] ReadDataBlockM;
logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0]; logic [`XLEN-1:0] ReadDataBlockSetsM [(WORDSPERLINE)-1:0];
logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM; logic [`XLEN-1:0] ReadDataWordM, FinalReadDataWordM;
@ -184,11 +184,7 @@ module dcache
end end
// *** TODO add replacement policy // *** TODO add replacement policy
genvar index; assign NewReplacement = '0;
generate
for(index = 0; index < NUMLINES-1; index++)
assign NewReplacement[index] = '0;
endgenerate
assign VictimWay = 4'b0001; assign VictimWay = 4'b0001;
mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableW ? WayHit : '0), mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWriteEnableW ? WayHit : '0),
.d1(SRAMBlockWriteEnableM ? VictimWay : '0), .d1(SRAMBlockWriteEnableM ? VictimWay : '0),
@ -201,12 +197,13 @@ module dcache
// ReadDataBlockWayMaskedM is a 2d array of cache block len by number of ways. // ReadDataBlockWayMaskedM is a 2d array of cache block len by number of ways.
// Need to OR together each way in a bitwise manner. // Need to OR together each way in a bitwise manner.
// Final part of the AO Mux. // Final part of the AO Mux.
genvar index;
always_comb begin always_comb begin
ReadDataBlockM = '0; ReadDataBlockM = '0;
VictimReadDataBlockM = '0; VictimReadDataBlockM = '0;
for(int index = 0; index < NUMWAYS; index++) begin for(int index = 0; index < NUMWAYS; index++) begin
ReadDataBlockM = ReadDataBlockM | ReadDataBlockWayMaskedM; ReadDataBlockM = ReadDataBlockM | ReadDataBlockWayMaskedM[index];
VictimReadDataBlockM = VictimReadDataBlockM | VictimReadDataBLockWayMaskedM; VictimReadDataBlockM = VictimReadDataBlockM | VictimReadDataBLockWayMaskedM[index];
end end
end end
assign VictimDirty = | VictimDirtyWay; assign VictimDirty = | VictimDirtyWay;
@ -363,7 +360,7 @@ module dcache
SRAMWritePipeReg(.clk(clk), SRAMWritePipeReg(.clk(clk),
.reset(reset), .reset(reset),
.d({SRAMWordWriteEnableM, SetValidM, ClearValidM, SetDirtyM, ClearDirtyM, AtomicM}), .d({SRAMWordWriteEnableM, SetValidM, ClearValidM, SetDirtyM, ClearDirtyM, AtomicM}),
.q({SRAMWordWriteEnableW, SetValidW, ClearValidM, SetDirtyM, ClearDirtyM, AtomicW})); .q({SRAMWordWriteEnableW, SetValidW, ClearValidW, SetDirtyW, ClearDirtyW, AtomicW}));
// fsm state regs // fsm state regs
@ -491,4 +488,4 @@ module dcache
assign CntEn = PreCntEn & AHBAck; assign CntEn = PreCntEn & AHBAck;
endmodule; // dcache endmodule // dcache