mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Add JTAG simulation driver
This commit is contained in:
Matthew Otto
parent
a72a49ff00
commit
4c0ab90507
@ -79,6 +79,7 @@ module tap (
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PauseIR : State <= tms ? Exit2IR : PauseIR;
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Exit2IR : State <= tms ? UpdateIR : ShiftIR;
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UpdateIR : State <= tms ? SelectDR : RunTestIdle;
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default : State <= TLReset;
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endcase
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end
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19
testbench/jtag/clk_divider.sv
Normal file
19
testbench/jtag/clk_divider.sv
Normal file
@ -0,0 +1,19 @@
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module clk_divider #(parameter DIV) (
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input logic clk_in, reset,
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output logic clk_out
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);
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integer count;
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always_ff @(posedge clk_in) begin
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if (reset) begin
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count <= 0;
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clk_out <= 0;
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end else if (count == DIV) begin
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clk_out <= ~clk_out;
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count <= 0;
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end else begin
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count <= count + 1;
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end
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end
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endmodule
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174
testbench/jtag/jtag_driver.sv
Normal file
174
testbench/jtag/jtag_driver.sv
Normal file
@ -0,0 +1,174 @@
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module jtag_driver(
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input logic clk, reset,
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output logic tdi, tms, tck,
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input logic tdo
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);
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localparam logic [2:0] INSTR_RUN = 3'b000;
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localparam logic [2:0] INSTR_SIR = 3'b001;
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localparam logic [2:0] INSTR_SDR = 3'b010;
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localparam CMD_BITS = 3;
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localparam LENGTH_BITS = 10;
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localparam DATA_BITS = 48;
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localparam WIDTH = CMD_BITS + LENGTH_BITS + DATA_BITS*3;
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localparam DEPTH = 100;
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enum logic [4:0] {RESET, NOP, LOAD, DECODE, COMPLETE, ERROR, DR1, DR2, DR3, SHIFTDR,
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IR1, IR2, IR3, IR4, SHIFTIR, RTI1, RTI2} State;
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bit [WIDTH-1:0] MEM [DEPTH-1:0];
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logic [$clog2(DEPTH)-1:0] IP;
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logic [CMD_BITS-1:0] Instruction;
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logic [LENGTH_BITS-1:0] Length, Idx;
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logic [DATA_BITS-1:0] ScanIn, ScanOut, Mask, ScanData;
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always_ff @(posedge clk) begin
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if (reset) begin
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IP <= 0;
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Idx <= 0;
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State <= RESET;
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end else
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case (State)
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RESET : begin
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// TAP controller has no reset signal
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// we must clock a 111110 into TMS to guarantee Run-Test/Idle state
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if (Idx == 5)
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State <= LOAD;
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else
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Idx <= Idx + 1;
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end
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LOAD : begin
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{Instruction, Length, ScanIn, ScanOut, Mask} <= MEM[IP];
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if (|MEM[IP])
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State <= DECODE;
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else
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State <= COMPLETE;
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IP <= IP + 1;
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end
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DECODE : begin
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ScanData <= '0;
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Idx <= 0;
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case (Instruction)
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INSTR_RUN : State <= NOP;
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INSTR_SDR : State <= DR1;
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INSTR_SIR : State <= IR1;
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default : State <= ERROR;
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endcase
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end
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NOP : begin
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if (Idx == Length-1)
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State <= LOAD;
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else
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Idx <= Idx + 1;
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end
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DR1 : State <= DR2;
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DR2 : State <= DR3;
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DR3 : State <= SHIFTDR;
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SHIFTDR : begin
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ScanData[Idx] <= tdo;
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if (Idx == Length-1)
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State <= RTI1;
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else
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Idx <= Idx + 1;
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end
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IR1 : State <= IR2;
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IR2 : State <= IR3;
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IR3 : State <= IR4;
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IR4 : State <= SHIFTIR;
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SHIFTIR : begin
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ScanData[Idx] <= tdo;
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if (Idx == Length-1)
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State <= RTI1;
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else
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Idx <= Idx + 1;
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end
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RTI1 : begin
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if (|(ScanOut & Mask) & ((ScanData & Mask) != (ScanOut & Mask)))
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State <= ERROR;
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else
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State <= RTI2;
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end
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RTI2 : State <= LOAD;
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COMPLETE : State <= COMPLETE;
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ERROR : State <= ERROR;
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endcase
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end
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// Drive TMS/TDI on falling edge of clock to match spec and also avoid weird simulation bugs
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always_ff @(negedge clk) begin
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// default values
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tdi <= 1'bx;
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case (State)
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RESET : tms <= (Idx != 5);
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LOAD,
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DECODE,
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NOP,
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COMPLETE : tms <= 0;
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DR1 : tms <= 1;
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DR2 : tms <= 0;
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DR3 : tms <= 0;
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SHIFTDR : begin
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tms <= (Idx == Length-1);
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tdi <= ScanIn[Idx];
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end
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IR1 : tms <= 1;
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IR2 : tms <= 1;
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IR3 : tms <= 0;
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IR4 : tms <= 0;
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SHIFTIR : begin
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tms <= (Idx == Length-1);
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tdi <= ScanIn[Idx];
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end
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RTI1 : tms <= 1;
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RTI2 : tms <= 0;
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endcase
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end
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// tck driver
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always_comb begin
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case (State)
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LOAD,
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DECODE,
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COMPLETE,
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ERROR : begin
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tck = 0;
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end
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RESET,
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NOP,
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DR1,
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DR2,
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DR3,
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SHIFTDR,
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IR1,
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IR2,
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IR3,
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IR4,
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SHIFTIR,
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RTI1,
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RTI2 : begin
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tck = clk;
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end
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endcase
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end
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endmodule
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192
testbench/jtag/svf_convert.py
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192
testbench/jtag/svf_convert.py
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@ -0,0 +1,192 @@
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from enum import Enum
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from math import log2
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# Assembled SVF command format
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CMD_BITS = 3
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LENGTH_BITS = 10
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DATA_BITS = 48
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# Derived constants
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MAXLEN = 2**LENGTH_BITS
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def main():
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filepath = "testbench/jtag/test.svf"
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dest_filepath = "testbench/jtag/test.mem"
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with open(filepath, "r") as file:
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data = file.read()
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data = data.lower()
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tokens = svf_tokenizer(data)
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tokens = remove_comments(tokens)
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cmds = parse_tokens(tokens)
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with open(dest_filepath, "w") as file:
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for cmd in cmds:
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asm = assemble_svf(cmd)
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file.write(asm + '\n')
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def svf_tokenizer(data):
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"""Reads raw SVF ascii and converts to a list of tokens"""
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keywords = ["sir", "sdr", "runtest", "tdi", "tdo", "mask", "smask", "(", ")", ";"]
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comment_keywords = ["//", "!"]
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keywords += comment_keywords
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tokens = []
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eof = len(data)
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token = ""
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for idx, char in enumerate(data):
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if char != " " and char != "\n":
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token += char
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if (idx+1 < eof):
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if data[idx+1] == " ":
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if token:
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tokens.append(token)
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token = ""
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elif data[idx+1] == "\n":
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if token:
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tokens.append(token)
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token = ""
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tokens.append("\n")
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elif token in keywords or data[idx+1] in keywords:
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if token:
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tokens.append(token)
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token = ""
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return tokens
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def remove_comments(tokens):
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"""Removes comments and newlines from list of tokens"""
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pruned = []
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comment = False
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for t in tokens:
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if t == "\n":
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comment = False
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continue
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if comment:
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continue
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if t in ["//", "!"]:
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comment = True
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continue
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pruned.append(t)
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return pruned
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def parse_tokens(tokens):
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"""groups tokens belonging to the same SVF command and checks if valid"""
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cmds = []
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cmd = Command()
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start_idx = 0
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i = -1
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while i+1 < len(tokens):
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i += 1
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t = tokens[i]
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if t == ";":
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if cmd.complete():
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cmds.append(cmd)
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cmd = Command()
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start_idx = i+1
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continue
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else:
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raise Exception(f"Error: incomplete SVF command terminated : '{' '.join(tokens[start_idx:i+1])}'")
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if cmd.op is None:
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try:
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cmd.op = SVF[t]
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except KeyError:
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raise Exception(f"Error: expected an SVF command, got '{t}' : '{' '.join(tokens[start_idx:i+1])}'")
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continue
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if cmd.length is None:
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try:
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cmd.length = int(t)
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except Exception:
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raise Exception(f"Error: expected a length value, got '{t}' : '{' '.join(tokens[start_idx:i+1])}'")
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if cmd.length == 0:
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raise Exception(f"Error: length parameter must not be 0 : '{' '.join(tokens[start_idx:i+1])}'")
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if cmd.length >= MAXLEN:
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raise Exception(f"Error: not enough bits to represent command length : {cmd.length} > {MAXLEN-1} : '{' '.join(tokens[start_idx:i+2])}'")
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if cmd.op != SVF.runtest and cmd.length > DATA_BITS:
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raise Exception(f"Error: length exceeds number of bits in data field : {cmd.length} > {DATA_BITS} : '{' '.join(tokens[start_idx:i+2])}'")
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continue
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match cmd.op:
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case SVF.runtest:
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continue
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case SVF.sdr | SVF.sir:
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if t not in ("tdi", "tdo", "mask"):
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raise Exception(f"Error: unknown keyword '{t}' : '{' '.join(tokens[start_idx:i+1])}'")
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if not (tokens[i+1] == "(" and tokens[i+3] == ")"):
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raise Exception(f"Error: could not interpret value following token '{t}' (missing parentheses) : '{' '.join(tokens[start_idx:i+2])}'")
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try:
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val = int(tokens[i+2], 16)
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i += 3
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if t == "tdi":
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cmd.tdi = val
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elif t == "tdo":
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cmd.tdo = val
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elif t == "mask":
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cmd.mask = val
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except Exception:
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raise Exception(f"Error: could not interpret {t} value: '{tokens[i+2]}' : '{' '.join(tokens[start_idx:i+1])}'")
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if val > 0 and int(log2(val)) > cmd.length:
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raise Exception(f"Error: shift data cannot be a value larger than the maximum implied by the length parameter : log2({val}) > {cmd.length}" +
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f" : '{' '.join(tokens[start_idx:i+2])}'")
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continue
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case _:
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raise Exception(f"Error: did not match on valid SVF command : '{' '.join(tokens[start_idx:i+1])}'")
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if t != ";":
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raise Exception(f"Error: file ended with incomplete command")
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return cmds
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def assemble_svf(cmd):
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"""Converts svf command object to proprietary format for Wally simulation"""
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cmdcode = (cmd.op.value << (LENGTH_BITS + DATA_BITS*3))
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match cmd.op:
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case SVF.runtest:
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cmdcode += (cmd.length << DATA_BITS*3)
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case SVF.sdr | SVF.sir:
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if cmd.length:
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cmdcode += (cmd.length << DATA_BITS*3)
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if cmd.tdi:
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cmdcode += (cmd.tdi << DATA_BITS*2)
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if cmd.tdo:
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cmdcode += (cmd.tdo << DATA_BITS)
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if cmd.mask:
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cmdcode += (cmd.mask)
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elif not cmd.mask: # If mask isnt specified, set all bits to 1
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cmdcode += 2**DATA_BITS-1
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hexcmd = hex(cmdcode)[2:]
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# TODO: pad left with 0 if needed (if CMD_BITS increases)
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return hexcmd
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class Command:
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def __init__(self):
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self.op = None
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self.length = None
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self.tdi = None
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self.tdo = None
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self.mask = None
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def complete(self):
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"""Returns true if object contains enough information to form a complete command"""
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if self.op == SVF.runtest:
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return self.length
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elif self.op in (SVF.sdr, SVF.sir):
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z = self.length and (self.tdi is not None or self.tdo is not None)
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return z
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else:
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return False
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# Supported SVF commands
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class SVF(Enum):
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runtest = 0
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sir = 1
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sdr = 2
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if __name__ == "__main__":
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main()
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8
testbench/jtag/test.svf
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8
testbench/jtag/test.svf
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@ -0,0 +1,8 @@
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// SVF commands to pull to idcode out of jtag module
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SIR 5 TDI(1); // IDCODE
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SDR 32 TDO(DEADBEEF);
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SDR 32 TDO(DEADBEAF); // JTAG_Driver should throw error if TDO value doesn't match what is scanned out
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RUNTEST 55;
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sir 8 !and multiline commands
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tdo(99);
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@ -67,6 +67,8 @@ module testbench;
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logic reset_ext, reset;
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logic ResetMem;
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// JTAG driver signals
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logic jtag_clk; // divided clock that runs jtag_driver
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logic tck;
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logic tdi;
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logic tms;
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@ -271,7 +273,7 @@ module testbench;
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logic ResetCntRst;
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logic CopyRAM;
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string signame, elffilename, memfilename, bootmemfilename, uartoutfilename, pathname;
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string signame, elffilename, memfilename, bootmemfilename, uartoutfilename, pathname, jtagmemfilename;
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integer begin_signature_addr, end_signature_addr, signature_size;
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integer uartoutfile;
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@ -579,10 +581,21 @@ module testbench;
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assign SDCIntr = 1'b0;
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end
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// Change these if testing debug
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assign tck = 0;
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assign tdi = 0;
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assign tms = 0;
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// TODO: drive jtag clock at 1/10th core clock (variable)
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if (P.DEBUG_SUPPORTED) begin
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always @(posedge clk) begin
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jtagmemfilename = "../tests/test.svf.memfile";
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if (LoadMem) begin
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$readmemh(jtagmemfilename, jtag.MEM);
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$display("Read memfile %s", jtagmemfilename);
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end
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end
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clk_divider #(2) cdiv (.clk_in(clk), .clk_out(jtag_clk), .reset(reset_ext));
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jtag_driver jtag(.clk(jtag_clk), .reset(reset_ext), .tdi, .tms, .tck, .tdo);
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end else begin
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assign {tdi,tms,tck} = '0;
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end
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wallypipelinedsoc #(P) dut(
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.clk, .reset_ext, .reset, .tck, .tdi, .tms, .tdo,
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