lint cleanup

wally-pipelined/src/ieu/controller.sv

@@ -230,7 +230,7 @@ module controller(
                          {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, AtomicM, InvalidateICacheM, FlushDCacheM, InstrValidM});
   
   // Writeback stage pipeline control register
-  flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW,
+  flopenrc #(4) controlregW(clk, reset, FlushW, ~StallW,
                          {RegWriteM, ResultSrcM},
                          {RegWriteW, ResultSrcW});  
 

wally-pipelined/src/ieu/ieu.sv

@@ -55,7 +55,6 @@ module ieu (
   output logic [2:0] 	   Funct3M, // size and signedness to LSU
   output logic [`XLEN-1:0] SrcAM, // to privilege and fpu
   output logic [4:0]    RdM,
-  input logic 		   DataAccessFaultM,
   input logic [`XLEN-1:0]  FIntResM, 
   output logic       InvalidateICacheM, FlushDCacheM,
 
@@ -84,7 +83,6 @@ module ieu (
   logic [2:0]  ResultSrcW;
   logic        TargetSrcE;
   logic        SCE;
-  logic        InstrValidW;
 
   // forwarding signals
   logic [4:0]       Rs1D, Rs2D, Rs1E, Rs2E;

wally-pipelined/src/wally/wallypipelinedhart.sv

@@ -26,14 +26,10 @@
 `include "wally-config.vh"
 /* verilator lint_on UNUSED */
 
-module wallypipelinedhart 
-  (
+module wallypipelinedhart (
    input logic 		    clk, reset,
-   output logic [`XLEN-1:0] PCF,
-   //  input  logic [31:0]      InstrF,
    // Privileged
    input logic 		    TimerIntM, ExtIntM, SwIntM,
-   input logic 		    DataAccessFaultM,
    input logic [63:0] 	    MTIME_CLINT, MTIMECMP_CLINT,
    // Bus Interface
    input logic [`AHBW-1:0]  HRDATA,
@@ -68,7 +64,7 @@ module wallypipelinedhart
   logic [2:0] 		    Funct3E;
   //  logic [31:0] InstrF;
   logic [31:0] 		    InstrD, InstrE, InstrM, InstrW;
-  logic [`XLEN-1:0] 	    PCD, PCE, PCM, PCLinkE;
+  logic [`XLEN-1:0] 	    PCF, PCD, PCE, PCM, PCLinkE;
   logic [`XLEN-1:0] 	    PCTargetE;
   logic [`XLEN-1:0] 	    CSRReadValW, MulDivResultW;
   logic [`XLEN-1:0] 	    PrivilegedNextPCM;