Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

lint cleanup

Browse Source
This commit is contained in:
David Harris 2021-10-23 11:03:28 -07:00
parent d570df864f
commit 4bf823e063
3 changed files with 3 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
wally-pipelined/src/ieu/controller.sv
View File

@ -230,7 +230,7 @@ module controller(
{RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, AtomicM, InvalidateICacheM, FlushDCacheM, InstrValidM}); {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, AtomicM, InvalidateICacheM, FlushDCacheM, InstrValidM});
// Writeback stage pipeline control register // Writeback stage pipeline control register
flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW, flopenrc #(4) controlregW(clk, reset, FlushW, ~StallW,
{RegWriteM, ResultSrcM}, {RegWriteM, ResultSrcM},
{RegWriteW, ResultSrcW}); {RegWriteW, ResultSrcW});

2
wally-pipelined/src/ieu/ieu.sv
View File

@ -55,7 +55,6 @@ module ieu (
output logic [2:0] Funct3M, // size and signedness to LSU output logic [2:0] Funct3M, // size and signedness to LSU
output logic [`XLEN-1:0] SrcAM, // to privilege and fpu output logic [`XLEN-1:0] SrcAM, // to privilege and fpu
output logic [4:0] RdM, output logic [4:0] RdM,
input logic DataAccessFaultM,
input logic [`XLEN-1:0] FIntResM, input logic [`XLEN-1:0] FIntResM,
output logic InvalidateICacheM, FlushDCacheM, output logic InvalidateICacheM, FlushDCacheM,
@ -84,7 +83,6 @@ module ieu (
logic [2:0] ResultSrcW; logic [2:0] ResultSrcW;
logic TargetSrcE; logic TargetSrcE;
logic SCE; logic SCE;
logic InstrValidW;
// forwarding signals // forwarding signals
logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E;

8
wally-pipelined/src/wally/wallypipelinedhart.sv
View File

@ -26,14 +26,10 @@
`include "wally-config.vh" `include "wally-config.vh"
/* verilator lint_on UNUSED */ /* verilator lint_on UNUSED */
module wallypipelinedhart module wallypipelinedhart (
(
input logic clk, reset, input logic clk, reset,
output logic [`XLEN-1:0] PCF,
// input logic [31:0] InstrF,
// Privileged // Privileged
input logic TimerIntM, ExtIntM, SwIntM, input logic TimerIntM, ExtIntM, SwIntM,
input logic DataAccessFaultM,
input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT, input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT,
// Bus Interface // Bus Interface
input logic [`AHBW-1:0] HRDATA, input logic [`AHBW-1:0] HRDATA,
@ -68,7 +64,7 @@ module wallypipelinedhart
logic [2:0] Funct3E; logic [2:0] Funct3E;
// logic [31:0] InstrF; // logic [31:0] InstrF;
logic [31:0] InstrD, InstrE, InstrM, InstrW; logic [31:0] InstrD, InstrE, InstrM, InstrW;
logic [`XLEN-1:0] PCD, PCE, PCM, PCLinkE; logic [`XLEN-1:0] PCF, PCD, PCE, PCM, PCLinkE;
logic [`XLEN-1:0] PCTargetE; logic [`XLEN-1:0] PCTargetE;
logic [`XLEN-1:0] CSRReadValW, MulDivResultW; logic [`XLEN-1:0] CSRReadValW, MulDivResultW;
logic [`XLEN-1:0] PrivilegedNextPCM; logic [`XLEN-1:0] PrivilegedNextPCM;