Vivado requires an intermediate wrapper file for parameterization.

fpga/generator/wally.tcl

@@ -12,6 +12,17 @@ if {$boardName!="ArtyA7"} {
     set_property board_part $boardName [current_project]
 }
 
+# read package first
+read_verilog -sv  ../src/CopiedFiles_do_not_add_to_repo/cvw.sv
+read_verilog -sv  ../src/wallypipelinedsocwrapper.sv
+# then read top level
+if {$board=="ArtyA7"} {
+    read_verilog  {../src/fpgaTopArtyA7.v}
+} else {
+    read_verilog  {../src/fpgaTop.v}
+}
+
+# read in ip
 read_ip IP/xlnx_proc_sys_reset.srcs/sources_1/ip/xlnx_proc_sys_reset/xlnx_proc_sys_reset.xci
 read_ip IP/xlnx_ahblite_axi_bridge.srcs/sources_1/ip/xlnx_ahblite_axi_bridge/xlnx_ahblite_axi_bridge.xci
 read_ip IP/xlnx_axi_clock_converter.srcs/sources_1/ip/xlnx_axi_clock_converter/xlnx_axi_clock_converter.xci
@@ -23,17 +34,13 @@ if {$board=="ArtyA7"} {
     read_ip IP/xlnx_ddr4.srcs/sources_1/ip/xlnx_ddr4/xlnx_ddr4.xci
 }
 
-read_verilog -sv [glob -type f ../src/CopiedFiles_do_not_add_to_repo/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
+# read in all other rtl
-if {$board=="ArtyA7"} {
+read_verilog -sv [glob -type f  ../src/CopiedFiles_do_not_add_to_repo/*/*.sv ../src/CopiedFiles_do_not_add_to_repo/*/*/*.sv]
-    read_verilog  {../src/fpgaTopArtyA7.v}
+
-} else {
-    read_verilog  {../src/fpgaTop.v}
-}
 read_verilog -sv  [glob -type f ../src/sdc/*.sv]
 
 set_property include_dirs {../../config/fpga ../../config/shared} [current_fileset]
 
-
 if {$board=="ArtyA7"} {
     add_files -fileset constrs_1 -norecurse ../constraints/constraints-$board.xdc
     set_property PROCESSING_ORDER NORMAL [get_files  ../constraints/constraints-$board.xdc]
@@ -45,7 +52,6 @@ if {$board=="ArtyA7"} {
 # define top level
 set_property top fpgaTop [current_fileset]
 
-
 update_compile_order -fileset sources_1
 # This is important as the ddr3/4 IP contains the generate clock constraint which the user constraints depend on.
 exec mkdir -p reports/

fpga/src/fpgaTop.v

@@ -24,8 +24,6 @@
 // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 ///////////////////////////////////////////
 
-`include "config.vh"
-
 module fpgaTop 
   (input           default_250mhz_clk1_0_n,
    input 		   default_250mhz_clk1_0_p, 
@@ -62,9 +60,6 @@ module fpgaTop
    output [0 : 0]  c0_ddr4_ck_t
    );
 
-`include "parameter-defs.vh"
-  
-
   wire 			   CPUCLK;
   wire 			   c0_ddr4_ui_clk_sync_rst;
   wire 			   bus_struct_reset;
@@ -75,12 +70,12 @@ module fpgaTop
   
   wire 			   HCLKOpen;
   wire 			   HRESETnOpen;
-  wire [P.AHBW-1:0] HRDATAEXT;
+  wire [64-1:0] HRDATAEXT;
   wire 			   HREADYEXT;
   wire 			   HRESPEXT;
   wire 			   HSELEXT;
   wire [31:0] 	   HADDR;
-  wire [P.AHBW-1:0] HWDATA;
+  wire [64-1:0] HWDATA;
   wire 			   HWRITE;
   wire [2:0] 	   HSIZE;
   wire [2:0] 	   HBURST;
@@ -214,7 +209,7 @@ module fpgaTop
   
 
   // wally
-  wallypipelinedsoc #(P) wallypipelinedsoc
+  wallypipelinedsocwrapper wallypipelinedsocwrapper
     (.clk(CPUCLK),
      .reset_ext(bus_struct_reset),
      // bus interface

fpga/src/wallypipelinedsocwrapper.sv

@@ -0,0 +1,72 @@
+///////////////////////////////////////////
+// wallypipelinedsocwrapper.sv
+//
+// Written: Ross Thompson ross1728@gmail.com 16 June 2023
+// Modified: 
+//
+// Purpose: A wrapper to set parameters.  Vivado cannot set the top level parameters because it only supports verilog,
+//          not system verilog.
+// 
+// A component of the Wally configurable RISC-V project.
+// 
+// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
+//
+// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+//
+// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file 
+// except in compliance with the License, or, at your option, the Apache License version 2.0. You 
+// may obtain a copy of the License at
+//
+// https://solderpad.org/licenses/SHL-2.1/
+//
+// Unless required by applicable law or agreed to in writing, any work distributed under the 
+// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, 
+// either express or implied. See the License for the specific language governing permissions 
+// and limitations under the License.
+////////////////////////////////////////////////////////////////////////////////////////////////
+
+`include "config.vh"
+
+import cvw::*;
+
+module wallypipelinedsocwrapper (
+  input  logic                clk, 
+  input  logic                reset_ext,        // external asynchronous reset pin
+  output logic                reset,            // reset synchronized to clk to prevent races on release
+  // AHB Interface
+  input  logic [P.AHBW-1:0]     HRDATAEXT,
+  input  logic                HREADYEXT, HRESPEXT,
+  output logic                HSELEXT,
+  // outputs to external memory, shared with uncore memory
+  output logic                HCLK, HRESETn,
+  output logic [64-1:0]  HADDR,
+  output logic [64-1:0]     HWDATA,
+  output logic [64/8-1:0]   HWSTRB,
+  output logic                HWRITE,
+  output logic [2:0]          HSIZE,
+  output logic [2:0]          HBURST,
+  output logic [3:0]          HPROT,
+  output logic [1:0]          HTRANS,
+  output logic                HMASTLOCK,
+  output logic                HREADY,
+  // I/O Interface
+  input  logic                TIMECLK,          // optional for CLINT MTIME counter
+  input  logic [31:0]         GPIOIN,           // inputs from GPIO
+  output logic [31:0]         GPIOOUT,          // output values for GPIO
+  output logic [31:0]         GPIOEN,           // output enables for GPIO
+  input  logic                UARTSin,          // UART serial data input
+  output logic                UARTSout,         // UART serial data output
+  input  logic                SDCCmdIn,         // SDC Command input
+  output logic                SDCCmdOut,        // SDC Command output
+  output logic                SDCCmdOE,         // SDC Command output enable
+  input  logic [3:0]          SDCDatIn,         // SDC data input
+  output logic                SDCCLK            // SDC clock
+);
+  `include "parameter-defs.vh"
+
+  wallypipelinedsoc  #(P) dut(.clk, .reset_ext, .reset, .HRDATAEXT,.HREADYEXT, .HRESPEXT,.HSELEXT,
+    .HCLK, .HRESETn, .HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT,
+    .HTRANS, .HMASTLOCK, .HREADY, .TIMECLK(1'b0), .GPIOIN, .GPIOOUT, .GPIOEN,
+    .UARTSin, .UARTSout, .SDCCmdIn, .SDCCmdOut, .SDCCmdOE, .SDCDatIn, .SDCCLK); 
+
+endmodule

testbench/wallywrapper.sv

@@ -26,36 +26,16 @@
 ////////////////////////////////////////////////////////////////////////////////////////////////
 
 `include "config.vh"
-`include "tests.vh"
-
-`define PrintHPMCounters 0
-`define BPRED_LOGGER 0
-`define I_CACHE_ADDR_LOGGER 0
-`define D_CACHE_ADDR_LOGGER 0
 
 import cvw::*;
 
 module wallywrapper;
-  parameter DEBUG=0;
-  parameter TEST="none";
  
 `include "parameter-defs.vh"
 
   logic        clk;
   logic        reset_ext, reset;
 
-  parameter SIGNATURESIZE = 5000000;
-
-  int test, i, errors, totalerrors;
-  logic [31:0] sig32[0:SIGNATURESIZE];
-  logic [P.XLEN-1:0] signature[0:SIGNATURESIZE];
-  logic [P.XLEN-1:0] testadr, testadrNoBase;
-  string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
-  logic [31:0] InstrW;
-
-  string tests[];
-  logic [3:0] dummy;
-
   logic [P.AHBW-1:0]    HRDATAEXT;
   logic                HREADYEXT, HRESPEXT;
   logic [P.PA_BITS-1:0] HADDR;