From f126d1e0ef9757fc735cbd7f52973e7c37487cd3 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 1 Feb 2023 21:31:25 -0800 Subject: [PATCH 001/231] added beginning of a ZBS instruction module to the ALU. Control signals still needed --- pipelined/src/ieu/alu.sv | 5 ++++ pipelined/src/ieu/zbs.sv | 58 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 pipelined/src/ieu/zbs.sv diff --git a/pipelined/src/ieu/alu.sv b/pipelined/src/ieu/alu.sv index ccd55779c..e7f7786a8 100644 --- a/pipelined/src/ieu/alu.sv +++ b/pipelined/src/ieu/alu.sv @@ -32,6 +32,7 @@ module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform + input logic [6:0] Funct7, input logic [2:0] Funct3, // With ALUControl, indicates operation to perform output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands @@ -83,6 +84,10 @@ module alu #(parameter WIDTH=32) ( 3'b111: FullResult = A & B; // and endcase + if (`ZBS_SUPPORTED) + zbs zbs(.A, .B, .Funct7, .Funct3, .ZBSResult); + else assign ZBSResult = 0; + // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits if (WIDTH == 64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; else assign Result = FullResult; diff --git a/pipelined/src/ieu/zbs.sv b/pipelined/src/ieu/zbs.sv new file mode 100644 index 000000000..021594ac6 --- /dev/null +++ b/pipelined/src/ieu/zbs.sv @@ -0,0 +1,58 @@ +/////////////////////////////////////////// +// zbs.sv +// +// Written: Kevin Kim and Kip Macsai-Goren +// Created: 31 January 2023 +// Modified: +// +// Purpose: RISC-V single bit manipulation unit (ZBS instructions) +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module zbs #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, // Operands + //input logic [2:0] ALUControl, // With Funct3, indicates operation to perform + input logic [6:0] Funct7, + input logic [2:0] Funct3, // With ***Control, indicates operation to perform + output logic [WIDTH-1:0] ZBSResult); // ZBS result + //output logic [WIDTH-1:0] Sum); // Sum of operands + + logic [WIDTH-1:0] BMask, ClrResult, InvResult, ExtResult, SetResult; + + decoder #(clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], BMask); + + assign InvResult = A ^ BMask; + assign ClrResult = A & ~BMask; + assign SetResult = A | BMask; + assign ExtResult = |(A & BMask); + + casez ({Funct7, Funct3}) + 10'b010010?_001: ZBSResult = ClrResult; + 10'b010010?_101: ZBSResult = ExtResult; + 10'b011010?_001: ZBSResult = ClrResult; + 10'b001010?_001: ZBSResult = ClrResult; + default: ZBSResult = 0; // *** should never be reached or selected + endcase + +endmodule + From bd8f0189ee19387efbffa4511ac83afb979c5778 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Feb 2023 16:40:58 +0000 Subject: [PATCH 002/231] started clmul --- pipelined/src/ieu/clmul.sv | 0 1 file changed, 0 insertions(+), 0 deletions(-) create mode 100644 pipelined/src/ieu/clmul.sv diff --git a/pipelined/src/ieu/clmul.sv b/pipelined/src/ieu/clmul.sv new file mode 100644 index 000000000..e69de29bb From f07ffbb63b93e0f46425cb6ee8fe4dc32bed4790 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Feb 2023 18:54:33 +0000 Subject: [PATCH 003/231] continued clmul unit --- pipelined/src/ieu/clmul.sv | 53 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/pipelined/src/ieu/clmul.sv b/pipelined/src/ieu/clmul.sv index e69de29bb..2fba79f02 100644 --- a/pipelined/src/ieu/clmul.sv +++ b/pipelined/src/ieu/clmul.sv @@ -0,0 +1,53 @@ +/////////////////////////////////////////// +// clmul.sv +// +// Written: Kevin Kim and Kip Macsai-Goren +// Created: 1 February 2023 +// Modified: +// +// Purpose: RISC-V single bit manipulation unit (ZBS instructions) +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module clmul #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, // Operands + output logic [WIDTH-1:0] Result); // ZBS result + //output logic [WIDTH-1:0] Sum); // Sum of operands + + logic [WIDTH-1] pp [WIDTH-1]; //partial AND products + logic [WIDTH-1] sop; //sum of partial products + genvar i; + for (i=0; i Date: Thu, 2 Feb 2023 19:49:14 +0000 Subject: [PATCH 004/231] clmul finished initial hdl; passes lint --- pipelined/src/ieu/clmul.sv | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ieu/clmul.sv b/pipelined/src/ieu/clmul.sv index 2fba79f02..bd2615a91 100644 --- a/pipelined/src/ieu/clmul.sv +++ b/pipelined/src/ieu/clmul.sv @@ -32,21 +32,23 @@ module clmul #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands output logic [WIDTH-1:0] Result); // ZBS result - //output logic [WIDTH-1:0] Sum); // Sum of operands - logic [WIDTH-1] pp [WIDTH-1]; //partial AND products - logic [WIDTH-1] sop; //sum of partial products - genvar i; - for (i=0; i Date: Thu, 2 Feb 2023 20:04:38 +0000 Subject: [PATCH 005/231] zbs passes lint --- pipelined/src/ieu/zbs.sv | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/pipelined/src/ieu/zbs.sv b/pipelined/src/ieu/zbs.sv index 021594ac6..3d764c0f4 100644 --- a/pipelined/src/ieu/zbs.sv +++ b/pipelined/src/ieu/zbs.sv @@ -35,7 +35,6 @@ module zbs #(parameter WIDTH=32) ( input logic [6:0] Funct7, input logic [2:0] Funct3, // With ***Control, indicates operation to perform output logic [WIDTH-1:0] ZBSResult); // ZBS result - //output logic [WIDTH-1:0] Sum); // Sum of operands logic [WIDTH-1:0] BMask, ClrResult, InvResult, ExtResult, SetResult; @@ -46,13 +45,15 @@ module zbs #(parameter WIDTH=32) ( assign SetResult = A | BMask; assign ExtResult = |(A & BMask); - casez ({Funct7, Funct3}) - 10'b010010?_001: ZBSResult = ClrResult; - 10'b010010?_101: ZBSResult = ExtResult; - 10'b011010?_001: ZBSResult = ClrResult; - 10'b001010?_001: ZBSResult = ClrResult; - default: ZBSResult = 0; // *** should never be reached or selected - endcase + always_comb begin + casez ({Funct7, Funct3}) + 10'b010010?_001: ZBSResult = ClrResult; + 10'b010010?_101: ZBSResult = ExtResult; + 10'b011010?_001: ZBSResult = InvResult; + 10'b001010?_001: ZBSResult = SetResult; + default: ZBSResult = 0; // *** should never be reached or selected + endcase + end endmodule From e2228f634132646bd280f9e6fc137d53095d5956 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Feb 2023 20:11:11 +0000 Subject: [PATCH 006/231] started zbc --- pipelined/src/ieu/clmul.sv | 2 +- pipelined/src/ieu/zbc.sv | 41 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 1 deletion(-) create mode 100644 pipelined/src/ieu/zbc.sv diff --git a/pipelined/src/ieu/clmul.sv b/pipelined/src/ieu/clmul.sv index bd2615a91..4fa8dda5a 100644 --- a/pipelined/src/ieu/clmul.sv +++ b/pipelined/src/ieu/clmul.sv @@ -5,7 +5,7 @@ // Created: 1 February 2023 // Modified: // -// Purpose: RISC-V single bit manipulation unit (ZBS instructions) +// Purpose: Carry-Less multiplication top-level unit // // Documentation: RISC-V System on Chip Design Chapter *** // diff --git a/pipelined/src/ieu/zbc.sv b/pipelined/src/ieu/zbc.sv new file mode 100644 index 000000000..14cc2b889 --- /dev/null +++ b/pipelined/src/ieu/zbc.sv @@ -0,0 +1,41 @@ +/////////////////////////////////////////// +// zbc.sv +// +// Written: Kevin Kim and Kip Macsai-Goren +// Created: 2 February 2023 +// Modified: +// +// Purpose: RISC-V single bit manipulation unit (ZBC instructions) +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module zbs #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, // Operands + //input logic [2:0] ALUControl, // With Funct3, indicates operation to perform + input logic [6:0] Funct7, + input logic [2:0] Funct3, // With ***Control, indicates operation to perform + output logic [WIDTH-1:0] ZBCResult); // ZBC result + + + +endmodule \ No newline at end of file From adc96ecaaa02ccb7fe71476116d067ee29a2b376 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Feb 2023 23:10:57 +0000 Subject: [PATCH 007/231] added bit reverse module, passes lint --- pipelined/src/ieu/bitreverse.sv | 43 +++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 pipelined/src/ieu/bitreverse.sv diff --git a/pipelined/src/ieu/bitreverse.sv b/pipelined/src/ieu/bitreverse.sv new file mode 100644 index 000000000..5d195d241 --- /dev/null +++ b/pipelined/src/ieu/bitreverse.sv @@ -0,0 +1,43 @@ + +/////////////////////////////////////////// +// bitreverse.sv +// +// Written: Kevin Kim and Kip Macsai-Goren +// Created: 1 February 2023 +// Modified: +// +// Purpose: Carry-Less multiplication top-level unit +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// +`include "wally-config.vh" + +module bitreverse #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] a, + output logic [WIDTH-1:0] b); + + genvar i; + for (i=0; i Date: Fri, 3 Feb 2023 04:48:23 +0000 Subject: [PATCH 008/231] zbc initial done; passes lint. clmul logic changes have not verified yet --- pipelined/src/ieu/clmul.sv | 11 ++++----- pipelined/src/ieu/zbc.sv | 47 ++++++++++++++++++++++++++++++++++---- 2 files changed, 47 insertions(+), 11 deletions(-) diff --git a/pipelined/src/ieu/clmul.sv b/pipelined/src/ieu/clmul.sv index 4fa8dda5a..5557283f9 100644 --- a/pipelined/src/ieu/clmul.sv +++ b/pipelined/src/ieu/clmul.sv @@ -31,23 +31,22 @@ module clmul #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands - output logic [WIDTH-1:0] Result); // ZBS result + output logic [WIDTH-1:0] ClmulResult); // ZBS result logic [WIDTH-1:0] pp [WIDTH-1:0]; //partial AND products - logic [WIDTH-1:0] sop; //sum of partial products genvar i,j; - for (i=1; i CLMUL -> MUX -> RESULT + //alternate could have CLMUL * 3 -> MUX -> MUX + always_comb begin + casez (Funct3) + 3'b001: begin //clmul + X = A; + Y = B; + end + 3'b011: begin //clmulh + X = {RevA[WIDTH-2:0], {1'b0}}; + Y = {{1'b0}, RevB[WIDTH-2:0]}; + end + 3'b010: begin //clmulr + X = {A[WIDTH-2:0], {1'b0}}; + Y = B; + end + default: begin + X = 0; + Y = 0; + end + endcase + + end + clmul clm(.A(X), .B(Y), .ClmulResult(ClmulResult)); + bitreverse brClmulResult(.a(ClmulResult), .b(RevClmulResult)); + + assign ZBCResult = (Funct3 == 3'b011) ? RevClmulResult : ClmulResult; endmodule \ No newline at end of file From a0ea436b9c37ed44a219fdc4bd7771f2cceb0819 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Feb 2023 05:31:50 +0000 Subject: [PATCH 009/231] zbs minor lint fix --- pipelined/src/ieu/datapath.sv | 31 +------------------------------ pipelined/src/ieu/zbs.sv | 2 +- 2 files changed, 2 insertions(+), 31 deletions(-) diff --git a/pipelined/src/ieu/datapath.sv b/pipelined/src/ieu/datapath.sv index 60d43de92..e1202bb90 100644 --- a/pipelined/src/ieu/datapath.sv +++ b/pipelined/src/ieu/datapath.sv @@ -1,32 +1,3 @@ -/////////////////////////////////////////// -// datapath.sv -// -// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu -// Created: 9 January 2021 -// Modified: -// -// Purpose: Wally Integer Datapath -// -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - `include "wally-config.vh" module datapath ( @@ -141,4 +112,4 @@ module datapath ( // handle Store Conditional result if atomic extension supported if (`A_SUPPORTED) assign SCResultW = {{(`XLEN-1){1'b0}}, SquashSCW}; else assign SCResultW = 0; -endmodule +endmodule \ No newline at end of file diff --git a/pipelined/src/ieu/zbs.sv b/pipelined/src/ieu/zbs.sv index 3d764c0f4..ae3b751af 100644 --- a/pipelined/src/ieu/zbs.sv +++ b/pipelined/src/ieu/zbs.sv @@ -38,7 +38,7 @@ module zbs #(parameter WIDTH=32) ( logic [WIDTH-1:0] BMask, ClrResult, InvResult, ExtResult, SetResult; - decoder #(clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], BMask); + decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], BMask); assign InvResult = A ^ BMask; assign ClrResult = A & ~BMask; From f0730c13e27d4b8b502f851b9573fcaaca480751 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Feb 2023 05:40:38 +0000 Subject: [PATCH 010/231] Started Zbb -Performs byte instructions (orc.b, rev8 (32/64)) --- pipelined/src/ieu/zbb.sv | 59 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 pipelined/src/ieu/zbb.sv diff --git a/pipelined/src/ieu/zbb.sv b/pipelined/src/ieu/zbb.sv new file mode 100644 index 000000000..2a7ea3024 --- /dev/null +++ b/pipelined/src/ieu/zbb.sv @@ -0,0 +1,59 @@ + +/////////////////////////////////////////// +// zbb.sv +// +// Written: Kevin Kim and Kip Macsai-Goren +// Created: 2 February 2023 +// Modified: +// +// Purpose: RISC-V miscellaneous bit manipulation unit (subset of ZBB instructions) +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module zbb #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, // Operands + input logic [2:0] Funct3, // Indicates operation to perform + input logic [6:0] Funct7, // Indicates operation to perform + output logic [WIDTH-1:0] ZBBResult); // ZBC result + + logic [WIDTH-1:0] OrcBResult; + logic [WIDTH-1:0] Rev8Result; + + genvar i; + + for (i=0;i Date: Fri, 3 Feb 2023 16:00:32 +0000 Subject: [PATCH 011/231] ALU changes (ZBB) - handles inverted operand instructions - handles shift-and-add instructions --- pipelined/src/ieu/alu.sv | 61 +++++++++++++++++++++++++++++++--------- 1 file changed, 48 insertions(+), 13 deletions(-) diff --git a/pipelined/src/ieu/alu.sv b/pipelined/src/ieu/alu.sv index e7f7786a8..1d472268c 100644 --- a/pipelined/src/ieu/alu.sv +++ b/pipelined/src/ieu/alu.sv @@ -37,22 +37,52 @@ module alu #(parameter WIDTH=32) ( output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands - // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. + // CondInvB = ~B when subtracting or inverted operand instruction in ZBB, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult; // Intermediate results + logic [WIDTH-1:0] ZBBResult, ZBSResult; + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult, CondShiftA; // Intermediate results logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction logic SubArith; // Performing subtraction or arithmetic right shift logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B + logic InvB; // Is Inverted Operand Instruction (ZBB) // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; + // Addition - assign CondInvB = SubArith ? ~B : B; - assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; + if (`ZBB_SUPPORTED) + always_comb begin + case({Funct7, Funct3}) + 10'b0010000_010: CondShiftA = {A[WIDTH-1:1], {1'b0}}; //sh1add + 10'b0010000_100: CondShiftA = {A[WIDTH-1:2], {2'b00}}; //sh2add + 10'b0010000_110: CondShiftA = {A[WIDTH-1:3], {3'b000}}; //sh3add + 10'b0000100_000: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw + 10'b0010000_010: CondShiftA = {{31{1'b0}},A[31:0], {1'b0}}; //sh1add.uw + 10'b0010000_100: CondShiftA = {{30{1'b0}},A[31:0], {2'b0}}; //sh2add.uw + 10'b0010000_110: CondShiftA = {{29{1'b0}},A[31:0], {3'b0}}; //sh3add.uw + default: CondShiftA = A; + endcase + + case ({Funct7,Funct3}) + 10'b0100000_111: InvB = 1'b1; //andn + 10'b0100000_110: InvB = 1'b1; //orn + 10'b0100000_100: InvB = 1'b1; //xnor + default: InvB = 1'b0; + endcase + + end + else begin + assign CondShiftA = A; + assign InvB = 1'b0; + end + + assign CondInvB = (SubArith | InvB) ? ~B : B; + + assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift)); @@ -73,20 +103,25 @@ module alu #(parameter WIDTH=32) ( // Select appropriate ALU Result always_comb - if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) - else casez (Funct3) // Otherwise check Funct3 - 3'b000: FullResult = Sum; // add or sub - 3'b?01: FullResult = Shift; // sll, sra, or srl - 3'b010: FullResult = SLT; // slt - 3'b011: FullResult = SLTU; // sltu - 3'b100: FullResult = A ^ B; // xor - 3'b110: FullResult = A | B; // or - 3'b111: FullResult = A & B; // and + if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) + else casez (Funct3) // Otherwise check Funct3 + 3'b000: FullResult = Sum; // add or sub + 3'b?01: FullResult = Shift; // sll, sra, or srl + 3'b010: FullResult = SLT; // slt + 3'b011: FullResult = SLTU; // sltu + 3'b100: FullResult = A ^ CondInvB; // xor + 3'b110: FullResult = A | CondInvB; // or + 3'b111: FullResult = A & CondInvB; // and endcase if (`ZBS_SUPPORTED) zbs zbs(.A, .B, .Funct7, .Funct3, .ZBSResult); else assign ZBSResult = 0; + + + if (`ZBB_SUPPORTED) + zbb zbb(.A, .B, .Funct7, .Funct3, .ZBBResult); + else assign ZBBResult = 0; // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits if (WIDTH == 64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; From 9c3f062f4d471d7c95a4245624fb4b046a1e3572 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Feb 2023 17:40:02 +0000 Subject: [PATCH 012/231] arch32ba includes the 32i_m tests instead of 64 --- pipelined/testbench/tests.vh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/pipelined/testbench/tests.vh b/pipelined/testbench/tests.vh index 1d094254e..2214d2a8f 100644 --- a/pipelined/testbench/tests.vh +++ b/pipelined/testbench/tests.vh @@ -883,9 +883,9 @@ string imperas32f[] = '{ string arch32ba[] = '{ `RISCVARCHTEST, // *** unclear why add.uw isn't in the list - "rv64i_m/B/src/sh1add-01.S", - "rv64i_m/B/src/sh1add-02.S", - "rv64i_m/B/src/sh1add-013.S" + "rv32i_m/B/src/sh1add-01.S", + "rv32i_m/B/src/sh1add-02.S", + "rv32i_m/B/src/sh1add-013.S" }; string arch64m[] = '{ From 8b6aad27c77d46f1e8539242a12405010f70ede0 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 4 Feb 2023 20:01:41 +0000 Subject: [PATCH 013/231] Started count instructions --- pipelined/src/ieu/zbb.sv | 52 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/pipelined/src/ieu/zbb.sv b/pipelined/src/ieu/zbb.sv index 2a7ea3024..623530673 100644 --- a/pipelined/src/ieu/zbb.sv +++ b/pipelined/src/ieu/zbb.sv @@ -34,8 +34,55 @@ module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] Funct3, // Indicates operation to perform input logic [6:0] Funct7, // Indicates operation to perform + input logic [6:0] W64, // Indicates word operation output logic [WIDTH-1:0] ZBBResult); // ZBC result + + //count instructions + logic [WIDTH-1:0] czResult; + logic [WIDTH-1:0] clzResult; //leading zeros result + logic [WIDTH-1:0] ctzResult; //trailing zeros result + logic [WIDTH-1:0] clzA, clzB; + logic [WIDTH-1:0] clzwA, clzwB; + logic [WIDTH-1:0] ctzA, ctzB; + logic [WIDTH-1:0] ctzwA, ctzwB; + logic [WIDTH-1:0] clzResult, ctzResult; + + //in both rv64, rv32 + assign clzA = A; + bitreverse #(WIDTH) brtz(.a(A), .b(ctzA)); + + //only in rv64 + assign clzwA = {A[31:0],{32{1'b1}}}; + bitreverse #(WIDTH) brtzw(.a({{32{1'b1}},A[31:0]}), .b(ctzwA)); + + //NOTE: Can be simplified to a single lzc with a 4-select mux. + lzc #(WIDTH) lzc(.num(clzA), .ZeroCnt(clzB)); + lzc #(WIDTH) lzwc(.num(clzwA), .ZeroCnt(clzwB)); + lzc #(WIDTH) tzc(.num(ctzA), .ZeroCnt(ctzB)); + lzc #(WIDTH) tzwc(.num(ctzwA), .ZeroCnt(ctzwB)); + + if (WIDTH==64) begin + assign clzResult = W64 ? clzwB : clzB; + assign ctzResult = W64 ? ctzwB : ctzB; + end + else begin + assign clzResult = clzB; + assign ctzResult = ctzB; + end + + + + + + + + + + + + + //byte instructions logic [WIDTH-1:0] OrcBResult; logic [WIDTH-1:0] Rev8Result; @@ -52,6 +99,11 @@ module zbb #(parameter WIDTH=32) ( 15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; + 15'b0110000_001_00000: ZBBResult = clzResult; + 15'b0110000_001_00010: //cpopResult goes here + 15'b0110000_001_00001: ZBBResult = ctzResult; + 15'b0110101_101_11000: ZBBResult = Rev8Result; + 15'b0110101_101_11000: ZBBResult = Rev8Result; endcase end From 4b6a757d68019870b9ecc4fd58250256c476d9a0 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Feb 2023 00:11:12 +0000 Subject: [PATCH 014/231] added population count in generic modules --- pipelined/src/generic/popcnt.sv | 40 +++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 pipelined/src/generic/popcnt.sv diff --git a/pipelined/src/generic/popcnt.sv b/pipelined/src/generic/popcnt.sv new file mode 100644 index 000000000..a5135dd1f --- /dev/null +++ b/pipelined/src/generic/popcnt.sv @@ -0,0 +1,40 @@ + +/////////////////////////////////////////// +// +// Written: Kevin Kim +// Modified: 2/4/2023 +// +// Purpose: Population Count +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +module popcnt #(parameter WIDTH = 32) ( + input logic [WIDTH-1:0] num, // number to count total ones + output logic [$clog2(WIDTH):0] PopCnt // the total number of ones +); + + logic [$clog2(WIDTH):0] sum; + genvar i; + for (i=0;i Date: Sun, 5 Feb 2023 00:11:24 +0000 Subject: [PATCH 015/231] zbb handles popcnt and passes lint --- pipelined/src/ieu/zbb.sv | 31 ++++++++++++++++++++++++------- 1 file changed, 24 insertions(+), 7 deletions(-) diff --git a/pipelined/src/ieu/zbb.sv b/pipelined/src/ieu/zbb.sv index 623530673..1c10cdcc7 100644 --- a/pipelined/src/ieu/zbb.sv +++ b/pipelined/src/ieu/zbb.sv @@ -40,35 +40,52 @@ module zbb #(parameter WIDTH=32) ( //count instructions logic [WIDTH-1:0] czResult; - logic [WIDTH-1:0] clzResult; //leading zeros result - logic [WIDTH-1:0] ctzResult; //trailing zeros result + logic [WIDTH-1:0] clzResult; //leading zeros result + logic [WIDTH-1:0] ctzResult; //trailing zeros result + logic [WIDTH-1:0] cpopResult; //population count result logic [WIDTH-1:0] clzA, clzB; logic [WIDTH-1:0] clzwA, clzwB; logic [WIDTH-1:0] ctzA, ctzB; logic [WIDTH-1:0] ctzwA, ctzwB; - logic [WIDTH-1:0] clzResult, ctzResult; + logic [WIDTH-1:0] cpopwA, cpopA; + logic [WIDTH-1:0] cpopwB, cpopB; //in both rv64, rv32 assign clzA = A; bitreverse #(WIDTH) brtz(.a(A), .b(ctzA)); //only in rv64 - assign clzwA = {A[31:0],{32{1'b1}}}; - bitreverse #(WIDTH) brtzw(.a({{32{1'b1}},A[31:0]}), .b(ctzwA)); + if (WIDTH==64) begin + assign clzwA = {A[31:0],{32{1'b1}}}; + bitreverse #(WIDTH) brtzw(.a({{32{1'b1}},A[31:0]}), .b(ctzwA)); + assign cpopwA = {{32{1'b0}},A}; - //NOTE: Can be simplified to a single lzc with a 4-select mux. + end + else begin + assign clzwA = 32'b0; + assign ctzwA = 32'b0; + assign cpopwA = 32'b0; + end + + //NOTE: Can be simplified to a single lzc with a 4-select mux. We are currently producing all cz results and selecting from those later. + //NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later. lzc #(WIDTH) lzc(.num(clzA), .ZeroCnt(clzB)); lzc #(WIDTH) lzwc(.num(clzwA), .ZeroCnt(clzwB)); lzc #(WIDTH) tzc(.num(ctzA), .ZeroCnt(ctzB)); lzc #(WIDTH) tzwc(.num(ctzwA), .ZeroCnt(ctzwB)); + popcnt #(WIDTH) popcntw(.num(cpopwA), .PopCnt(cpopwB)); + popcnt #(WIDTH) popcnt(.num(cpopA), .PopCnt(cpopB)); + if (WIDTH==64) begin assign clzResult = W64 ? clzwB : clzB; assign ctzResult = W64 ? ctzwB : ctzB; + assign cpopResult = W64 ? cpopwB : cpopB; end else begin assign clzResult = clzB; assign ctzResult = ctzB; + assign cpopResult = cpopB; end @@ -100,7 +117,7 @@ module zbb #(parameter WIDTH=32) ( 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0110000_001_00000: ZBBResult = clzResult; - 15'b0110000_001_00010: //cpopResult goes here + 15'b0110000_001_00010: ZBBResult = cpopResult; 15'b0110000_001_00001: ZBBResult = ctzResult; 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; From 8782f2d3520bac07692119214a3ecde900a2ea53 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Feb 2023 00:48:26 +0000 Subject: [PATCH 016/231] modularized count into cnt.sv; passes lint --- pipelined/src/ieu/cnt.sv | 84 ++++++++++++++++++++++++++++++++++++++++ pipelined/src/ieu/zbb.sv | 67 ++++---------------------------- 2 files changed, 91 insertions(+), 60 deletions(-) create mode 100644 pipelined/src/ieu/cnt.sv diff --git a/pipelined/src/ieu/cnt.sv b/pipelined/src/ieu/cnt.sv new file mode 100644 index 000000000..84a30fc57 --- /dev/null +++ b/pipelined/src/ieu/cnt.sv @@ -0,0 +1,84 @@ + +/////////////////////////////////////////// +// cnt.sv +// +// Written: Kevin Kim +// Created: 4 February 2023 +// Modified: +// +// Purpose: Count Instruction Submodule +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module cnt #(parameter WIDTH = 32) ( + input logic [WIDTH-1:0] A, // Operand + input logic W64, // Indicates word operation + output logic [WIDTH-1:0] clzResult, // leading zeros result + output logic [WIDTH-1:0] ctzResult, // trailing zeros result + output logic [WIDTH-1:0] cpopResult);// population count result + //count instructions + logic [WIDTH-1:0] clzA, clzB; + logic [WIDTH-1:0] clzwA, clzwB; + logic [WIDTH-1:0] ctzA, ctzB; + logic [WIDTH-1:0] ctzwA, ctzwB; + logic [WIDTH-1:0] cpopwA, cpopA; + logic [WIDTH-1:0] cpopwB, cpopB; + + //in both rv64, rv32 + assign clzA = A; + bitreverse #(WIDTH) brtz(.a(A), .b(ctzA)); + + //only in rv64 + if (WIDTH==64) begin + assign clzwA = {A[31:0],{32{1'b1}}}; + bitreverse #(WIDTH) brtzw(.a({{32{1'b1}},A[31:0]}), .b(ctzwA)); + assign cpopwA = {{32{1'b0}},A}; + + end + else begin + assign clzwA = 32'b0; + assign ctzwA = 32'b0; + assign cpopwA = 32'b0; + end + + //NOTE: Can be simplified to a single lzc with a 4-select mux. We are currently producing all cz results and selecting from those later. + //NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later. + lzc #(WIDTH) lzc(.num(clzA), .ZeroCnt(clzB)); + lzc #(WIDTH) lzwc(.num(clzwA), .ZeroCnt(clzwB)); + lzc #(WIDTH) tzc(.num(ctzA), .ZeroCnt(ctzB)); + lzc #(WIDTH) tzwc(.num(ctzwA), .ZeroCnt(ctzwB)); + + popcnt #(WIDTH) popcntw(.num(cpopwA), .PopCnt(cpopwB)); + popcnt #(WIDTH) popcnt(.num(cpopA), .PopCnt(cpopB)); + + if (WIDTH==64) begin + assign clzResult = W64 ? clzwB : clzB; + assign ctzResult = W64 ? ctzwB : ctzB; + assign cpopResult = W64 ? cpopwB : cpopB; + end + else begin + assign clzResult = clzB; + assign ctzResult = ctzB; + assign cpopResult = cpopB; + end +endmodule \ No newline at end of file diff --git a/pipelined/src/ieu/zbb.sv b/pipelined/src/ieu/zbb.sv index 1c10cdcc7..e3803e176 100644 --- a/pipelined/src/ieu/zbb.sv +++ b/pipelined/src/ieu/zbb.sv @@ -34,70 +34,17 @@ module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] Funct3, // Indicates operation to perform input logic [6:0] Funct7, // Indicates operation to perform - input logic [6:0] W64, // Indicates word operation - output logic [WIDTH-1:0] ZBBResult); // ZBC result - - - //count instructions - logic [WIDTH-1:0] czResult; - logic [WIDTH-1:0] clzResult; //leading zeros result - logic [WIDTH-1:0] ctzResult; //trailing zeros result - logic [WIDTH-1:0] cpopResult; //population count result - logic [WIDTH-1:0] clzA, clzB; - logic [WIDTH-1:0] clzwA, clzwB; - logic [WIDTH-1:0] ctzA, ctzB; - logic [WIDTH-1:0] ctzwA, ctzwB; - logic [WIDTH-1:0] cpopwA, cpopA; - logic [WIDTH-1:0] cpopwB, cpopB; - - //in both rv64, rv32 - assign clzA = A; - bitreverse #(WIDTH) brtz(.a(A), .b(ctzA)); - - //only in rv64 - if (WIDTH==64) begin - assign clzwA = {A[31:0],{32{1'b1}}}; - bitreverse #(WIDTH) brtzw(.a({{32{1'b1}},A[31:0]}), .b(ctzwA)); - assign cpopwA = {{32{1'b0}},A}; - - end - else begin - assign clzwA = 32'b0; - assign ctzwA = 32'b0; - assign cpopwA = 32'b0; - end - - //NOTE: Can be simplified to a single lzc with a 4-select mux. We are currently producing all cz results and selecting from those later. - //NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later. - lzc #(WIDTH) lzc(.num(clzA), .ZeroCnt(clzB)); - lzc #(WIDTH) lzwc(.num(clzwA), .ZeroCnt(clzwB)); - lzc #(WIDTH) tzc(.num(ctzA), .ZeroCnt(ctzB)); - lzc #(WIDTH) tzwc(.num(ctzwA), .ZeroCnt(ctzwB)); - - popcnt #(WIDTH) popcntw(.num(cpopwA), .PopCnt(cpopwB)); - popcnt #(WIDTH) popcnt(.num(cpopA), .PopCnt(cpopB)); - - if (WIDTH==64) begin - assign clzResult = W64 ? clzwB : clzB; - assign ctzResult = W64 ? ctzwB : ctzB; - assign cpopResult = W64 ? cpopwB : cpopB; - end - else begin - assign clzResult = clzB; - assign ctzResult = ctzB; - assign cpopResult = cpopB; - end - - - - - - - + input logic W64, // Indicates word operation + output logic [WIDTH-1:0] ZBBResult); // ZBB result + //count results + logic [WIDTH-1:0] clzResult; // leading zeros result + logic [WIDTH-1:0] ctzResult; // trailing zeros result + logic [WIDTH-1:0] cpopResult; // population count result + cnt cnt(.A(A), .W64(W64), .clzResult(clzResult), .ctzResult(ctzResult), .cpopResult(cpopResult)); //byte instructions logic [WIDTH-1:0] OrcBResult; From b87127743543b6a63282e8072134675bbad6a45a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Feb 2023 01:04:39 +0000 Subject: [PATCH 017/231] modularized byte instruction handling into byte.sv; passes lint --- pipelined/src/ieu/byte.sv | 44 +++++++++++++++++++++++++++++++++++++++ pipelined/src/ieu/zbb.sv | 11 +++------- 2 files changed, 47 insertions(+), 8 deletions(-) create mode 100644 pipelined/src/ieu/byte.sv diff --git a/pipelined/src/ieu/byte.sv b/pipelined/src/ieu/byte.sv new file mode 100644 index 000000000..17ab652f2 --- /dev/null +++ b/pipelined/src/ieu/byte.sv @@ -0,0 +1,44 @@ +/////////////////////////////////////////// +// clmul.sv +// +// Written: Kevin Kim +// Created: 1 February 2023 +// Modified: +// +// Purpose: Carry-Less multiplication top-level unit +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module byteUnit #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, // Operands + output logic [WIDTH-1:0] OrcBResult, // OrcB result + output logic [WIDTH-1:0] Rev8Result); // Rev8 result + + genvar i; + + for (i=0;i Date: Sun, 5 Feb 2023 16:37:32 +0000 Subject: [PATCH 018/231] began sign/zero extend --- pipelined/src/ieu/ext.sv | 44 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 pipelined/src/ieu/ext.sv diff --git a/pipelined/src/ieu/ext.sv b/pipelined/src/ieu/ext.sv new file mode 100644 index 000000000..c546d2c4e --- /dev/null +++ b/pipelined/src/ieu/ext.sv @@ -0,0 +1,44 @@ + +/////////////////////////////////////////// +// cnt.sv +// +// Written: Kevin Kim +// Created: 4 February 2023 +// Modified: +// +// Purpose: Sign/Zero Extension Submodule +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module ext #(parameter WIDTH = 32) ( + input logic [WIDTH-1:0] A, // Operand + input logic W64, // Indicates word operation + output logic [WIDTH-1:0] sexthResult, // sign extend halfword result + output logic [WIDTH-1:0] sextbResult, // sign extend byte result + output logic [WIDTH-1:0] zexthResult); // zero extend halfword result + + assign sexthResult = {{(XLEN-16){A[15]}},A[15:0]}; + assign zexthResult = {{(XLEN-16){1'b0}},A[15:0]}; + assign sextbResult = {{(XLEN-8){A[7]}},A[7:0]}; + +endmodule \ No newline at end of file From a81a48007ec1a8409dc1525ee068a977df255626 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Feb 2023 16:50:13 +0000 Subject: [PATCH 019/231] zbb handles sign --- pipelined/src/ieu/ext.sv | 7 +++---- pipelined/src/ieu/zbb.sv | 30 +++++++++++++++++++----------- 2 files changed, 22 insertions(+), 15 deletions(-) diff --git a/pipelined/src/ieu/ext.sv b/pipelined/src/ieu/ext.sv index c546d2c4e..c9f845e76 100644 --- a/pipelined/src/ieu/ext.sv +++ b/pipelined/src/ieu/ext.sv @@ -32,13 +32,12 @@ module ext #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] A, // Operand - input logic W64, // Indicates word operation output logic [WIDTH-1:0] sexthResult, // sign extend halfword result output logic [WIDTH-1:0] sextbResult, // sign extend byte result output logic [WIDTH-1:0] zexthResult); // zero extend halfword result - assign sexthResult = {{(XLEN-16){A[15]}},A[15:0]}; - assign zexthResult = {{(XLEN-16){1'b0}},A[15:0]}; - assign sextbResult = {{(XLEN-8){A[7]}},A[7:0]}; + assign sexthResult = {{(WIDTH-16){A[15]}},A[15:0]}; + assign zexthResult = {{(WIDTH-16){1'b0}},A[15:0]}; + assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]}; endmodule \ No newline at end of file diff --git a/pipelined/src/ieu/zbb.sv b/pipelined/src/ieu/zbb.sv index 860fd2c42..caaa19852 100644 --- a/pipelined/src/ieu/zbb.sv +++ b/pipelined/src/ieu/zbb.sv @@ -31,26 +31,31 @@ `include "wally-config.vh" module zbb #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands - input logic [2:0] Funct3, // Indicates operation to perform - input logic [6:0] Funct7, // Indicates operation to perform - input logic W64, // Indicates word operation - output logic [WIDTH-1:0] ZBBResult); // ZBB result + input logic [WIDTH-1:0] A, B, // Operands + input logic [2:0] Funct3, // Indicates operation to perform + input logic [6:0] Funct7, // Indicates operation to perform + input logic W64, // Indicates word operation + output logic [WIDTH-1:0] ZBBResult); // ZBB result - //count results - logic [WIDTH-1:0] clzResult; // leading zeros result - logic [WIDTH-1:0] ctzResult; // trailing zeros result - logic [WIDTH-1:0] cpopResult; // population count result + // count results + logic [WIDTH-1:0] clzResult; // leading zeros result + logic [WIDTH-1:0] ctzResult; // trailing zeros result + logic [WIDTH-1:0] cpopResult; // population count result - //byte results + // byte results logic [WIDTH-1:0] OrcBResult; logic [WIDTH-1:0] Rev8Result; - cnt cnt(.A(A), .W64(W64), .clzResult(clzResult), .ctzResult(ctzResult), .cpopResult(cpopResult)); + // sign/zero extend results + logic [WIDTH-1:0] sexthResult; // sign extend halfword result + logic [WIDTH-1:0] sextbResult; // sign extend byte result + logic [WIDTH-1:0] zexthResult; // zero extend halfword result + cnt cnt(.A(A), .W64(W64), .clzResult(clzResult), .ctzResult(ctzResult), .cpopResult(cpopResult)); byteUnit bu(.A(A), .OrcBResult(OrcBResult), .Rev8Result(Rev8Result)); + ext ext(.A(A), .sexthResult(sexthResult), .sextbResult(sextbResult), .zexthResult(zexthResult)); //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin @@ -63,6 +68,9 @@ module zbb #(parameter WIDTH=32) ( 15'b0110000_001_00001: ZBBResult = ctzResult; 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; + 15'b0000100_100_00000: ZBBResult = zexthResult; + 15'b0110000_001_00100: ZBBResult = sextbResult; + 15'b0110000_001_00101: ZBBResult = sexthResult; endcase end From be4d80a725e1fd4fb16d27a2e667812decf0e976 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 6 Feb 2023 17:55:37 +0000 Subject: [PATCH 020/231] modified shifter to configure for Zbb and handle rotates - alu handles rotates --- pipelined/src/ieu/alu.sv | 13 +++++- pipelined/src/ieu/shifter.sv | 79 ++++++++++++++++++++++++++++++++---- 2 files changed, 82 insertions(+), 10 deletions(-) diff --git a/pipelined/src/ieu/alu.sv b/pipelined/src/ieu/alu.sv index 1d472268c..e10591c19 100644 --- a/pipelined/src/ieu/alu.sv +++ b/pipelined/src/ieu/alu.sv @@ -48,6 +48,7 @@ module alu #(parameter WIDTH=32) ( logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B logic InvB; // Is Inverted Operand Instruction (ZBB) + logic Rotate; // Is rotate operation // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; @@ -74,6 +75,16 @@ module alu #(parameter WIDTH=32) ( default: InvB = 1'b0; endcase + casez ({Funct7, Funct3}) + 10'b0110000_101: Rotate = 1'b1; + 10'b011000?_101: Rotate = 1'b1; + 10'b000010?_001: Rotate = 1'b0; + 10'b0110000_001: Rotate = 1'b1; + 10'b0110000_101: Rotate = 1'b1; + 10'b0110000_001: Rotate = 1'b1; + 10'b0110000_101: Rotate = 1'b1; + default: Rotate = 1'b0; + endcase end else begin assign CondShiftA = A; @@ -85,7 +96,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts - shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift)); + shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Rotate(Rotate), .Y(Shift)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign diff --git a/pipelined/src/ieu/shifter.sv b/pipelined/src/ieu/shifter.sv index 77e4dab38..15c7b411e 100644 --- a/pipelined/src/ieu/shifter.sv +++ b/pipelined/src/ieu/shifter.sv @@ -1,9 +1,9 @@ /////////////////////////////////////////// // shifter.sv // -// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu +// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu // Created: 9 January 2021 -// Modified: +// Modified: 6 February 2023 // // Purpose: RISC-V 32/64 bit shifter // @@ -30,18 +30,18 @@ `include "wally-config.vh" module shifter ( - input logic [`XLEN-1:0] A, // Source - input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Arith, W64, // Shift right, arithmetic, RV64 W-type shift - output logic [`XLEN-1:0] Y); // Shifted result + input logic [`XLEN-1:0] A, // Source + input logic [`LOG_XLEN-1:0] Amt, // Shift amount + input logic Right, Arith, W64, Rotate, // Shift right, arithmetic, RV64 W-type shift + output logic [`XLEN-1:0] Y); // Shifted result - logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] amttrunc, offset; // Shift amount adjusted for RV64, right-shift amount + logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits + logic [`LOG_XLEN-1:0] amttrunc, offset; // Shift amount adjusted for RV64, right-shift amount // Handle left and right shifts with a funnel shifter. // For RV32, only 32-bit shifts are needed. // For RV64, 32- and 64-bit shifts are needed, with sign extension. - + /* // Funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) if (`XLEN==32) begin:shifter // RV32 always_comb // funnel mux @@ -65,6 +65,67 @@ module shifter ( end assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end + */ + + if (`ZBB_SUPPORTED) begin: rotFunnel // HANDLES ROTATE + if (`XLEN==32) begin:shifter // RV32 + always_comb // funnel mux + if (Right) + if (Rotate) z = {A[30:0], A[31:0]}; //ror (rv32) + else + if (Arith) z = {{31{A[31]}}, A}; + else z = {31'b0, A}; + else + if (Rotate) z = {A[31:0], A[31:1]}; //rol (rv32) + else z = {A, 31'b0}; + assign amttrunc = Amt; // shift amount + end else begin:shifter // RV64 + always_comb // funnel mux + if (W64) begin // 32-bit shifts + if (Right) + if (Rotate) z = {{64'b0},A[30:0],A[31:0]}; //rorw + else + if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; + else z = {95'b0, A[31:0]}; + else + if (Rotate) z = {{64'b0},A[31:0],A[31:1]}; //rolw + else z = {32'b0, A[31:0], 63'b0}; + end else begin + if (Right) + if (Rotate) z = {A[62:0], A[63:0]}; //ror + else + if (Arith) z = {{63{A[63]}}, A}; + else z = {63'b0, A}; + else + if (Rotate) z = {A[63:0], A[63:1]}; //rol + else z = {A, 63'b0}; + end + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + end else begin: norotFunnel + if (`XLEN==32) begin:shifter // RV32 + always_comb // funnel mux + if (Right) + if (Arith) z = {{31{A[31]}}, A}; + else z = {31'b0, A}; + else z = {A, 31'b0}; + assign amttrunc = Amt; // shift amount + end else begin:shifter // RV64 + always_comb // funnel mux + if (W64) begin // 32-bit shifts + if (Right) + if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; + else z = {95'b0, A[31:0]}; + else z = {32'b0, A[31:0], 63'b0}; + end else begin + if (Right) + if (Arith) z = {{63{A[63]}}, A}; + else z = {63'b0, A}; + else z = {A, 63'b0}; + end + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + end // Opposite offset for right shifts assign offset = Right ? amttrunc : ~amttrunc; From 4bf0886129e927139130db1c843557c8505643f8 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 8 Feb 2023 13:57:09 +0000 Subject: [PATCH 021/231] moved files into bmu folder --- src/ieu/{ => bmu}/bitreverse.sv | 0 src/ieu/{ => bmu}/byte.sv | 0 src/ieu/{ => bmu}/clmul.sv | 0 src/ieu/{ => bmu}/cnt.sv | 0 src/ieu/{ => bmu}/ext.sv | 0 src/{generic => ieu/bmu}/popcnt.sv | 0 src/ieu/{ => bmu}/zbb.sv | 0 src/ieu/{ => bmu}/zbc.sv | 0 src/ieu/{ => bmu}/zbs.sv | 0 9 files changed, 0 insertions(+), 0 deletions(-) rename src/ieu/{ => bmu}/bitreverse.sv (100%) rename src/ieu/{ => bmu}/byte.sv (100%) rename src/ieu/{ => bmu}/clmul.sv (100%) rename src/ieu/{ => bmu}/cnt.sv (100%) rename src/ieu/{ => bmu}/ext.sv (100%) rename src/{generic => ieu/bmu}/popcnt.sv (100%) rename src/ieu/{ => bmu}/zbb.sv (100%) rename src/ieu/{ => bmu}/zbc.sv (100%) rename src/ieu/{ => bmu}/zbs.sv (100%) diff --git a/src/ieu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv similarity index 100% rename from src/ieu/bitreverse.sv rename to src/ieu/bmu/bitreverse.sv diff --git a/src/ieu/byte.sv b/src/ieu/bmu/byte.sv similarity index 100% rename from src/ieu/byte.sv rename to src/ieu/bmu/byte.sv diff --git a/src/ieu/clmul.sv b/src/ieu/bmu/clmul.sv similarity index 100% rename from src/ieu/clmul.sv rename to src/ieu/bmu/clmul.sv diff --git a/src/ieu/cnt.sv b/src/ieu/bmu/cnt.sv similarity index 100% rename from src/ieu/cnt.sv rename to src/ieu/bmu/cnt.sv diff --git a/src/ieu/ext.sv b/src/ieu/bmu/ext.sv similarity index 100% rename from src/ieu/ext.sv rename to src/ieu/bmu/ext.sv diff --git a/src/generic/popcnt.sv b/src/ieu/bmu/popcnt.sv similarity index 100% rename from src/generic/popcnt.sv rename to src/ieu/bmu/popcnt.sv diff --git a/src/ieu/zbb.sv b/src/ieu/bmu/zbb.sv similarity index 100% rename from src/ieu/zbb.sv rename to src/ieu/bmu/zbb.sv diff --git a/src/ieu/zbc.sv b/src/ieu/bmu/zbc.sv similarity index 100% rename from src/ieu/zbc.sv rename to src/ieu/bmu/zbc.sv diff --git a/src/ieu/zbs.sv b/src/ieu/bmu/zbs.sv similarity index 100% rename from src/ieu/zbs.sv rename to src/ieu/bmu/zbs.sv From 5b5f9a2784cd2e5ee6c1cbfff8308fe9115729f6 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 9 Feb 2023 16:45:22 +0000 Subject: [PATCH 022/231] modified cnt for zbb to mux inputs --- src/ieu/bmu/cnt.sv | 66 ++++++++++++++++++++++------------------------ 1 file changed, 31 insertions(+), 35 deletions(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 84a30fc57..b0c44e06a 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -31,54 +31,50 @@ `include "wally-config.vh" module cnt #(parameter WIDTH = 32) ( - input logic [WIDTH-1:0] A, // Operand + input logic [WIDTH-1:0] A, B, // Operands input logic W64, // Indicates word operation - output logic [WIDTH-1:0] clzResult, // leading zeros result - output logic [WIDTH-1:0] ctzResult, // trailing zeros result + output logic [WIDTH-1:0] czResult, // count zeros result output logic [WIDTH-1:0] cpopResult);// population count result + //count instructions - logic [WIDTH-1:0] clzA, clzB; - logic [WIDTH-1:0] clzwA, clzwB; - logic [WIDTH-1:0] ctzA, ctzB; - logic [WIDTH-1:0] ctzwA, ctzwB; - logic [WIDTH-1:0] cpopwA, cpopA; - logic [WIDTH-1:0] cpopwB, cpopB; + logic [WIDTH-1:0] lzcA, popcntA; + logic [WIDTH-1:0] revA; //in both rv64, rv32 - assign clzA = A; - bitreverse #(WIDTH) brtz(.a(A), .b(ctzA)); + bitreverse #(WIDTH) brtz(.a(A), .b(revA)); //only in rv64 if (WIDTH==64) begin - assign clzwA = {A[31:0],{32{1'b1}}}; - bitreverse #(WIDTH) brtzw(.a({{32{1'b1}},A[31:0]}), .b(ctzwA)); - assign cpopwA = {{32{1'b0}},A}; + //NOTE: signal widths can be decreased + always_comb begin + //clz input select mux + case({B,W64}) + 5'b00000_0: lzcA = A; //clz + 5'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw + 5'b00001_0: lzcA = revA; //ctz + 5'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw + endcase + //cpop select mux + case ({B,W64}) + 5'b00010_0: popcntA = A; + 5'b00010_1: popcntA = {{32{1'b0}}, A[31:0]}; + endcase + end end else begin - assign clzwA = 32'b0; - assign ctzwA = 32'b0; - assign cpopwA = 32'b0; + assign popcntA = A; + always_comb begin + //clz input slect mux + case(B) + 5'b00000: lzcA = A; + 5'b00001: lzcA = revA; + endcase + end end - //NOTE: Can be simplified to a single lzc with a 4-select mux. We are currently producing all cz results and selecting from those later. //NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later. - lzc #(WIDTH) lzc(.num(clzA), .ZeroCnt(clzB)); - lzc #(WIDTH) lzwc(.num(clzwA), .ZeroCnt(clzwB)); - lzc #(WIDTH) tzc(.num(ctzA), .ZeroCnt(ctzB)); - lzc #(WIDTH) tzwc(.num(ctzwA), .ZeroCnt(ctzwB)); + lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult)); + popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult)); - popcnt #(WIDTH) popcntw(.num(cpopwA), .PopCnt(cpopwB)); - popcnt #(WIDTH) popcnt(.num(cpopA), .PopCnt(cpopB)); - - if (WIDTH==64) begin - assign clzResult = W64 ? clzwB : clzB; - assign ctzResult = W64 ? ctzwB : ctzB; - assign cpopResult = W64 ? cpopwB : cpopB; - end - else begin - assign clzResult = clzB; - assign ctzResult = ctzB; - assign cpopResult = cpopB; - end endmodule \ No newline at end of file From 17bd001057dd54e848f6151a16d7a7c11a31df11 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 9 Feb 2023 16:45:37 +0000 Subject: [PATCH 023/231] modified zbb to account for cnt module change --- src/ieu/bmu/zbb.sv | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index caaa19852..98996f3b8 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -40,8 +40,7 @@ module zbb #(parameter WIDTH=32) ( // count results - logic [WIDTH-1:0] clzResult; // leading zeros result - logic [WIDTH-1:0] ctzResult; // trailing zeros result + logic [WIDTH-1:0] czResult; // count zeros result (lzc or tzc) logic [WIDTH-1:0] cpopResult; // population count result // byte results @@ -53,7 +52,7 @@ module zbb #(parameter WIDTH=32) ( logic [WIDTH-1:0] sextbResult; // sign extend byte result logic [WIDTH-1:0] zexthResult; // zero extend halfword result - cnt cnt(.A(A), .W64(W64), .clzResult(clzResult), .ctzResult(ctzResult), .cpopResult(cpopResult)); + cnt cnt(.A(A), .B(B), .W64(W64), .czResult(czResult), .cpopResult(cpopResult)); byteUnit bu(.A(A), .OrcBResult(OrcBResult), .Rev8Result(Rev8Result)); ext ext(.A(A), .sexthResult(sexthResult), .sextbResult(sextbResult), .zexthResult(zexthResult)); @@ -63,9 +62,9 @@ module zbb #(parameter WIDTH=32) ( 15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; - 15'b0110000_001_00000: ZBBResult = clzResult; + 15'b0110000_001_00000: ZBBResult = czResult; 15'b0110000_001_00010: ZBBResult = cpopResult; - 15'b0110000_001_00001: ZBBResult = ctzResult; + 15'b0110000_001_00001: ZBBResult = czResult; 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0000100_100_00000: ZBBResult = zexthResult; From 76a8f2d3d3a8aa364b189c0ce6f11b5dd008d062 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 9 Feb 2023 19:07:22 +0000 Subject: [PATCH 024/231] added W64 zbb input signal in alu --- src/ieu/alu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index e10591c19..15a19f558 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -131,7 +131,7 @@ module alu #(parameter WIDTH=32) ( if (`ZBB_SUPPORTED) - zbb zbb(.A, .B, .Funct7, .Funct3, .ZBBResult); + zbb zbb(.A, .B, .Funct3, .Funct7, .W64, .ZBBResult); else assign ZBBResult = 0; // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits From f58a2b70a0b2fc847fd1d637e9d74a95e8adece7 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 9 Feb 2023 19:18:54 +0000 Subject: [PATCH 025/231] Include Funct7 in execute - Modifed datapath to support funct7 in execute - Modified controller to pass on Funct7 - all lints pass --- src/ieu/controller.sv | 7 ++++--- src/ieu/datapath.sv | 3 ++- src/ieu/ieu.sv | 5 +++-- 3 files changed, 9 insertions(+), 6 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 1819de17c..95b5efe85 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -48,6 +48,7 @@ module controller( output logic ALUResultSrcE, // Selects result to pass on to Memory stage output logic MemReadE, CSRReadE, // Instruction reads memory, reads a CSR (needed for Hazard unit) output logic [2:0] Funct3E, // Instruction's funct3 field + output logic [6:0] Funct7E, // Instruction's funct7 field output logic IntDivE, // Integer divide output logic MDUE, // MDU (multiply/divide) operatio output logic W64E, // RV64 W-type operation @@ -214,9 +215,9 @@ module controller( flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(28) controlregE(clk, reset, FlushE, ~StallE, - {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, - {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); + flopenrc #(35) controlregE(clk, reset, FlushE, ~StallE, + {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, + {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index e1202bb90..f715a5d5d 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -9,6 +9,7 @@ module datapath ( input logic [`XLEN-1:0] PCE, // PC in Execute stage input logic [`XLEN-1:0] PCLinkE, // PC + 4 (of instruction in Execute stage) input logic [2:0] Funct3E, // Funct3 field of instruction in Execute stage + input logic [6:0] Funct7E, // Funct7 field of instruction in Execute stage input logic StallE, FlushE, // Stall, flush Execute stage input logic [1:0] ForwardAE, ForwardBE, // Forward ALU operands from later stages input logic [2:0] ALUControlE, // Indicate operation ALU performs @@ -80,7 +81,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct7E, Funct3E, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 681bd9826..02eebe0a1 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -74,6 +74,7 @@ module ieu ( logic [2:0] ImmSrcD; // Select type of immediate extension logic [1:0] FlagsE; // Comparison flags ({eq, lt}) + logic [6:0] Funct7E; // Instruction's funct7 field in execute stage logic [2:0] ALUControlE; // ALU control indicates function to perform logic ALUSrcAE, ALUSrcBE; // ALU source operands logic [2:0] ResultSrcW; // Selects result in Writeback stage @@ -95,14 +96,14 @@ module ieu ( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, - .Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, + .Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD); datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, - .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, + .ALUControlE, .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, From 76593cb2828317b343ac5a2d0f7c2ef3cc665547 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 10 Feb 2023 10:35:19 -0800 Subject: [PATCH 026/231] Added necessary files to make bit make and run bit manipulation tests as part of regression --- config/rv64gc/wally-config.vh | 8 +- sim/sim-wally-batch | 2 +- testbench/testbench.sv | 1 + testbench/tests.vh | 1437 ++++++++++--------- tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py | 13 + tests/riscof/spike/spike_rv64gc_isa.yaml | 4 +- 6 files changed, 763 insertions(+), 702 deletions(-) create mode 100644 tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh index c3dd87295..c0ee1d5ec 100644 --- a/config/rv64gc/wally-config.vh +++ b/config/rv64gc/wally-config.vh @@ -145,10 +145,10 @@ `define DIVCOPIES 32'h4 // bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 +`define ZBA_SUPPORTED 1 +`define ZBB_SUPPORTED 1 +`define ZBC_SUPPORTED 1 +`define ZBS_SUPPORTED 1 // Memory synthesis configuration `define USE_SRAM 0 diff --git a/sim/sim-wally-batch b/sim/sim-wally-batch index 46c35c75c..95fc677c6 100755 --- a/sim/sim-wally-batch +++ b/sim/sim-wally-batch @@ -1 +1 @@ -vsim -c -do "do wally-batch.do rv32gc wally32priv" +vsim -c -do "do wally-batch.do rv64gc arch64b" diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 329d4c605..d10fed364 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -105,6 +105,7 @@ logic [3:0] dummy; "coremark": tests = coremark; "fpga": tests = fpga; "ahb" : tests = ahb; + "arch64b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch64b; endcase end else begin // RV32 case (TEST) diff --git a/testbench/tests.vh b/testbench/tests.vh index 3f9417b5f..5bf239ade 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -98,741 +98,741 @@ string tvpaths[] = '{ string imperas32f[] = '{ `IMPERASTEST, - "rv32i_m/F/FSQRT-S-DYN-RDN-01", - "rv32i_m/F/FADD-S-DYN-RDN-01", - "rv32i_m/F/FADD-S-DYN-RMM-01", - "rv32i_m/F/FADD-S-DYN-RNE-01", - "rv32i_m/F/FADD-S-DYN-RTZ-01", - "rv32i_m/F/FADD-S-DYN-RUP-01", - "rv32i_m/F/FADD-S-RDN-01", - "rv32i_m/F/FADD-S-RMM-01", - "rv32i_m/F/FADD-S-RNE-01", - "rv32i_m/F/FADD-S-RTZ-01", - "rv32i_m/F/FADD-S-RUP-01", - "rv32i_m/F/FCLASS-S-01", - "rv32i_m/F/FCVT-S-W-DYN-RDN-01", - "rv32i_m/F/FCVT-S-W-DYN-RMM-01", - "rv32i_m/F/FCVT-S-W-DYN-RNE-01", - "rv32i_m/F/FCVT-S-W-DYN-RTZ-01", - "rv32i_m/F/FCVT-S-W-DYN-RUP-01", - "rv32i_m/F/FCVT-S-W-RDN-01", - "rv32i_m/F/FCVT-S-W-RMM-01", - "rv32i_m/F/FCVT-S-W-RNE-01", - "rv32i_m/F/FCVT-S-W-RTZ-01", - "rv32i_m/F/FCVT-S-W-RUP-01", - "rv32i_m/F/FCVT-S-WU-DYN-RDN-01", - "rv32i_m/F/FCVT-S-WU-DYN-RMM-01", - "rv32i_m/F/FCVT-S-WU-DYN-RNE-01", - "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01", - "rv32i_m/F/FCVT-S-WU-DYN-RUP-01", - "rv32i_m/F/FCVT-S-WU-RDN-01", - "rv32i_m/F/FCVT-S-WU-RMM-01", - "rv32i_m/F/FCVT-S-WU-RNE-01", - "rv32i_m/F/FCVT-S-WU-RTZ-01", - "rv32i_m/F/FCVT-S-WU-RUP-01", - "rv32i_m/F/FCVT-W-S-DYN-RDN-01", - "rv32i_m/F/FCVT-W-S-DYN-RMM-01", - "rv32i_m/F/FCVT-W-S-DYN-RNE-01", - "rv32i_m/F/FCVT-W-S-DYN-RTZ-01", - "rv32i_m/F/FCVT-W-S-DYN-RUP-01", - "rv32i_m/F/FCVT-W-S-RDN-01", - "rv32i_m/F/FCVT-W-S-RMM-01", - "rv32i_m/F/FCVT-W-S-RNE-01", - "rv32i_m/F/FCVT-W-S-RTZ-01", - "rv32i_m/F/FCVT-W-S-RUP-01", - "rv32i_m/F/FCVT-WU-S-DYN-RDN-01", - "rv32i_m/F/FCVT-WU-S-DYN-RMM-01", - "rv32i_m/F/FCVT-WU-S-DYN-RNE-01", - "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01", - "rv32i_m/F/FCVT-WU-S-DYN-RUP-01", - "rv32i_m/F/FCVT-WU-S-RDN-01", - "rv32i_m/F/FCVT-WU-S-RMM-01", - "rv32i_m/F/FCVT-WU-S-RNE-01", - "rv32i_m/F/FCVT-WU-S-RTZ-01", - "rv32i_m/F/FCVT-WU-S-RUP-01", - "rv32i_m/F/FDIV-S-DYN-RDN-01", - "rv32i_m/F/FDIV-S-DYN-RMM-01", - "rv32i_m/F/FDIV-S-DYN-RNE-01", - "rv32i_m/F/FDIV-S-DYN-RTZ-01", - "rv32i_m/F/FDIV-S-DYN-RUP-01", - "rv32i_m/F/FDIV-S-RDN-01", - "rv32i_m/F/FDIV-S-RMM-01", - "rv32i_m/F/FDIV-S-RNE-01", - "rv32i_m/F/FDIV-S-RTZ-01", - "rv32i_m/F/FDIV-S-RUP-01", - "rv32i_m/F/FEQ-S-01", - "rv32i_m/F/FLE-S-01", - "rv32i_m/F/FLT-S-01", - "rv32i_m/F/FLW-01", - "rv32i_m/F/FMADD-S-DYN-RDN-01", - "rv32i_m/F/FMADD-S-DYN-RMM-01", - "rv32i_m/F/FMADD-S-DYN-RNE-01", - "rv32i_m/F/FMADD-S-DYN-RTZ-01", - "rv32i_m/F/FMADD-S-DYN-RUP-01", - "rv32i_m/F/FMADD-S-RDN-01", - "rv32i_m/F/FMADD-S-RMM-01", - "rv32i_m/F/FMADD-S-RNE-01", - "rv32i_m/F/FMADD-S-RTZ-01", - "rv32i_m/F/FMADD-S-RUP-01", - "rv32i_m/F/FMAX-S-01", - "rv32i_m/F/FMIN-S-01", - "rv32i_m/F/FMSUB-S-DYN-RDN-01", - "rv32i_m/F/FMSUB-S-DYN-RMM-01", - "rv32i_m/F/FMSUB-S-DYN-RNE-01", - "rv32i_m/F/FMSUB-S-DYN-RTZ-01", - "rv32i_m/F/FMSUB-S-DYN-RUP-01", - "rv32i_m/F/FMSUB-S-RDN-01", - "rv32i_m/F/FMSUB-S-RMM-01", - "rv32i_m/F/FMSUB-S-RNE-01", - "rv32i_m/F/FMSUB-S-RTZ-01", - "rv32i_m/F/FMSUB-S-RUP-01", - "rv32i_m/F/FMUL-S-DYN-RDN-01", - "rv32i_m/F/FMUL-S-DYN-RMM-01", - "rv32i_m/F/FMUL-S-DYN-RNE-01", - "rv32i_m/F/FMUL-S-DYN-RTZ-01", - "rv32i_m/F/FMUL-S-DYN-RUP-01", - "rv32i_m/F/FMUL-S-RDN-01", - "rv32i_m/F/FMUL-S-RMM-01", - "rv32i_m/F/FMUL-S-RNE-01", - "rv32i_m/F/FMUL-S-RTZ-01", - "rv32i_m/F/FMUL-S-RUP-01", - "rv32i_m/F/FMV-W-X-01", - "rv32i_m/F/FMV-X-W-01", - "rv32i_m/F/FNMADD-S-DYN-RDN-01", - "rv32i_m/F/FNMADD-S-DYN-RMM-01", - "rv32i_m/F/FNMADD-S-DYN-RNE-01", - "rv32i_m/F/FNMADD-S-DYN-RTZ-01", - "rv32i_m/F/FNMADD-S-DYN-RUP-01", - "rv32i_m/F/FNMADD-S-RDN-01", - "rv32i_m/F/FNMADD-S-RMM-01", - "rv32i_m/F/FNMADD-S-RNE-01", - "rv32i_m/F/FNMADD-S-RTZ-01", - "rv32i_m/F/FNMADD-S-RUP-01", - "rv32i_m/F/FNMSUB-S-DYN-RDN-01", - "rv32i_m/F/FNMSUB-S-DYN-RMM-01", - "rv32i_m/F/FNMSUB-S-DYN-RNE-01", - "rv32i_m/F/FNMSUB-S-DYN-RTZ-01", - "rv32i_m/F/FNMSUB-S-DYN-RUP-01", - "rv32i_m/F/FNMSUB-S-RDN-01", - "rv32i_m/F/FNMSUB-S-RMM-01", - "rv32i_m/F/FNMSUB-S-RNE-01", - "rv32i_m/F/FNMSUB-S-RTZ-01", - "rv32i_m/F/FNMSUB-S-RUP-01", - "rv32i_m/F/FSGNJN-S-01", - "rv32i_m/F/FSGNJ-S-01", - "rv32i_m/F/FSGNJX-S-01", - "rv32i_m/F/FSQRT-S-DYN-RDN-01", - "rv32i_m/F/FSQRT-S-DYN-RMM-01", - "rv32i_m/F/FSQRT-S-DYN-RNE-01", - "rv32i_m/F/FSQRT-S-DYN-RTZ-01", - "rv32i_m/F/FSQRT-S-DYN-RUP-01", - "rv32i_m/F/FSQRT-S-RDN-01", - "rv32i_m/F/FSQRT-S-RMM-01", - "rv32i_m/F/FSQRT-S-RNE-01", - "rv32i_m/F/FSQRT-S-RTZ-01", - "rv32i_m/F/FSQRT-S-RUP-01", - "rv32i_m/F/FSUB-S-DYN-RDN-01", - "rv32i_m/F/FSUB-S-DYN-RMM-01", - "rv32i_m/F/FSUB-S-DYN-RNE-01", - "rv32i_m/F/FSUB-S-DYN-RTZ-01", - "rv32i_m/F/FSUB-S-DYN-RUP-01", - "rv32i_m/F/FSUB-S-RDN-01", - "rv32i_m/F/FSUB-S-RMM-01", - "rv32i_m/F/FSUB-S-RNE-01", - "rv32i_m/F/FSUB-S-RTZ-01", - "rv32i_m/F/FSUB-S-RUP-01", - "rv32i_m/F/FSW-01" + "rv32i_m/F/FSQRT-S-DYN-RDN-01.S", + "rv32i_m/F/FADD-S-DYN-RDN-01.S", + "rv32i_m/F/FADD-S-DYN-RMM-01.S", + "rv32i_m/F/FADD-S-DYN-RNE-01.S", + "rv32i_m/F/FADD-S-DYN-RTZ-01.S", + "rv32i_m/F/FADD-S-DYN-RUP-01.S", + "rv32i_m/F/FADD-S-RDN-01.S", + "rv32i_m/F/FADD-S-RMM-01.S", + "rv32i_m/F/FADD-S-RNE-01.S", + "rv32i_m/F/FADD-S-RTZ-01.S", + "rv32i_m/F/FADD-S-RUP-01.S", + "rv32i_m/F/FCLASS-S-01.S", + "rv32i_m/F/FCVT-S-W-DYN-RDN-01.S", + "rv32i_m/F/FCVT-S-W-DYN-RMM-01.S", + "rv32i_m/F/FCVT-S-W-DYN-RNE-01.S", + "rv32i_m/F/FCVT-S-W-DYN-RTZ-01.S", + "rv32i_m/F/FCVT-S-W-DYN-RUP-01.S", + "rv32i_m/F/FCVT-S-W-RDN-01.S", + "rv32i_m/F/FCVT-S-W-RMM-01.S", + "rv32i_m/F/FCVT-S-W-RNE-01.S", + "rv32i_m/F/FCVT-S-W-RTZ-01.S", + "rv32i_m/F/FCVT-S-W-RUP-01.S", + "rv32i_m/F/FCVT-S-WU-DYN-RDN-01.S", + "rv32i_m/F/FCVT-S-WU-DYN-RMM-01.S", + "rv32i_m/F/FCVT-S-WU-DYN-RNE-01.S", + "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01.S", + "rv32i_m/F/FCVT-S-WU-DYN-RUP-01.S", + "rv32i_m/F/FCVT-S-WU-RDN-01.S", + "rv32i_m/F/FCVT-S-WU-RMM-01.S", + "rv32i_m/F/FCVT-S-WU-RNE-01.S", + "rv32i_m/F/FCVT-S-WU-RTZ-01.S", + "rv32i_m/F/FCVT-S-WU-RUP-01.S", + "rv32i_m/F/FCVT-W-S-DYN-RDN-01.S", + "rv32i_m/F/FCVT-W-S-DYN-RMM-01.S", + "rv32i_m/F/FCVT-W-S-DYN-RNE-01.S", + "rv32i_m/F/FCVT-W-S-DYN-RTZ-01.S", + "rv32i_m/F/FCVT-W-S-DYN-RUP-01.S", + "rv32i_m/F/FCVT-W-S-RDN-01.S", + "rv32i_m/F/FCVT-W-S-RMM-01.S", + "rv32i_m/F/FCVT-W-S-RNE-01.S", + "rv32i_m/F/FCVT-W-S-RTZ-01.S", + "rv32i_m/F/FCVT-W-S-RUP-01.S", + "rv32i_m/F/FCVT-WU-S-DYN-RDN-01.S", + "rv32i_m/F/FCVT-WU-S-DYN-RMM-01.S", + "rv32i_m/F/FCVT-WU-S-DYN-RNE-01.S", + "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01.S", + "rv32i_m/F/FCVT-WU-S-DYN-RUP-01.S", + "rv32i_m/F/FCVT-WU-S-RDN-01.S", + "rv32i_m/F/FCVT-WU-S-RMM-01.S", + "rv32i_m/F/FCVT-WU-S-RNE-01.S", + "rv32i_m/F/FCVT-WU-S-RTZ-01.S", + "rv32i_m/F/FCVT-WU-S-RUP-01.S", + "rv32i_m/F/FDIV-S-DYN-RDN-01.S", + "rv32i_m/F/FDIV-S-DYN-RMM-01.S", + "rv32i_m/F/FDIV-S-DYN-RNE-01.S", + "rv32i_m/F/FDIV-S-DYN-RTZ-01.S", + "rv32i_m/F/FDIV-S-DYN-RUP-01.S", + "rv32i_m/F/FDIV-S-RDN-01.S", + "rv32i_m/F/FDIV-S-RMM-01.S", + "rv32i_m/F/FDIV-S-RNE-01.S", + "rv32i_m/F/FDIV-S-RTZ-01.S", + "rv32i_m/F/FDIV-S-RUP-01.S", + "rv32i_m/F/FEQ-S-01.S", + "rv32i_m/F/FLE-S-01.S", + "rv32i_m/F/FLT-S-01.S", + "rv32i_m/F/FLW-01.S", + "rv32i_m/F/FMADD-S-DYN-RDN-01.S", + "rv32i_m/F/FMADD-S-DYN-RMM-01.S", + "rv32i_m/F/FMADD-S-DYN-RNE-01.S", + "rv32i_m/F/FMADD-S-DYN-RTZ-01.S", + "rv32i_m/F/FMADD-S-DYN-RUP-01.S", + "rv32i_m/F/FMADD-S-RDN-01.S", + "rv32i_m/F/FMADD-S-RMM-01.S", + "rv32i_m/F/FMADD-S-RNE-01.S", + "rv32i_m/F/FMADD-S-RTZ-01.S", + "rv32i_m/F/FMADD-S-RUP-01.S", + "rv32i_m/F/FMAX-S-01.S", + "rv32i_m/F/FMIN-S-01.S", + "rv32i_m/F/FMSUB-S-DYN-RDN-01.S", + "rv32i_m/F/FMSUB-S-DYN-RMM-01.S", + "rv32i_m/F/FMSUB-S-DYN-RNE-01.S", + "rv32i_m/F/FMSUB-S-DYN-RTZ-01.S", + "rv32i_m/F/FMSUB-S-DYN-RUP-01.S", + "rv32i_m/F/FMSUB-S-RDN-01.S", + "rv32i_m/F/FMSUB-S-RMM-01.S", + "rv32i_m/F/FMSUB-S-RNE-01.S", + "rv32i_m/F/FMSUB-S-RTZ-01.S", + "rv32i_m/F/FMSUB-S-RUP-01.S", + "rv32i_m/F/FMUL-S-DYN-RDN-01.S", + "rv32i_m/F/FMUL-S-DYN-RMM-01.S", + "rv32i_m/F/FMUL-S-DYN-RNE-01.S", + "rv32i_m/F/FMUL-S-DYN-RTZ-01.S", + "rv32i_m/F/FMUL-S-DYN-RUP-01.S", + "rv32i_m/F/FMUL-S-RDN-01.S", + "rv32i_m/F/FMUL-S-RMM-01.S", + "rv32i_m/F/FMUL-S-RNE-01.S", + "rv32i_m/F/FMUL-S-RTZ-01.S", + "rv32i_m/F/FMUL-S-RUP-01.S", + "rv32i_m/F/FMV-W-X-01.S", + "rv32i_m/F/FMV-X-W-01.S", + "rv32i_m/F/FNMADD-S-DYN-RDN-01.S", + "rv32i_m/F/FNMADD-S-DYN-RMM-01.S", + "rv32i_m/F/FNMADD-S-DYN-RNE-01.S", + "rv32i_m/F/FNMADD-S-DYN-RTZ-01.S", + "rv32i_m/F/FNMADD-S-DYN-RUP-01.S", + "rv32i_m/F/FNMADD-S-RDN-01.S", + "rv32i_m/F/FNMADD-S-RMM-01.S", + "rv32i_m/F/FNMADD-S-RNE-01.S", + "rv32i_m/F/FNMADD-S-RTZ-01.S", + "rv32i_m/F/FNMADD-S-RUP-01.S", + "rv32i_m/F/FNMSUB-S-DYN-RDN-01.S", + "rv32i_m/F/FNMSUB-S-DYN-RMM-01.S", + "rv32i_m/F/FNMSUB-S-DYN-RNE-01.S", + "rv32i_m/F/FNMSUB-S-DYN-RTZ-01.S", + "rv32i_m/F/FNMSUB-S-DYN-RUP-01.S", + "rv32i_m/F/FNMSUB-S-RDN-01.S", + "rv32i_m/F/FNMSUB-S-RMM-01.S", + "rv32i_m/F/FNMSUB-S-RNE-01.S", + "rv32i_m/F/FNMSUB-S-RTZ-01.S", + "rv32i_m/F/FNMSUB-S-RUP-01.S", + "rv32i_m/F/FSGNJN-S-01.S", + "rv32i_m/F/FSGNJ-S-01.S", + "rv32i_m/F/FSGNJX-S-01.S", + "rv32i_m/F/FSQRT-S-DYN-RDN-01.S", + "rv32i_m/F/FSQRT-S-DYN-RMM-01.S", + "rv32i_m/F/FSQRT-S-DYN-RNE-01.S", + "rv32i_m/F/FSQRT-S-DYN-RTZ-01.S", + "rv32i_m/F/FSQRT-S-DYN-RUP-01.S", + "rv32i_m/F/FSQRT-S-RDN-01.S", + "rv32i_m/F/FSQRT-S-RMM-01.S", + "rv32i_m/F/FSQRT-S-RNE-01.S", + "rv32i_m/F/FSQRT-S-RTZ-01.S", + "rv32i_m/F/FSQRT-S-RUP-01.S", + "rv32i_m/F/FSUB-S-DYN-RDN-01.S", + "rv32i_m/F/FSUB-S-DYN-RMM-01.S", + "rv32i_m/F/FSUB-S-DYN-RNE-01.S", + "rv32i_m/F/FSUB-S-DYN-RTZ-01.S", + "rv32i_m/F/FSUB-S-DYN-RUP-01.S", + "rv32i_m/F/FSUB-S-RDN-01.S", + "rv32i_m/F/FSUB-S-RMM-01.S", + "rv32i_m/F/FSUB-S-RNE-01.S", + "rv32i_m/F/FSUB-S-RTZ-01.S", + "rv32i_m/F/FSUB-S-RUP-01.S", + "rv32i_m/F/FSW-01.S" }; string imperas64f[] = '{ `IMPERASTEST, - "rv64i_m/F/FADD-S-DYN-RDN-01", - "rv64i_m/F/FADD-S-DYN-RMM-01", - "rv64i_m/F/FADD-S-DYN-RNE-01", - "rv64i_m/F/FADD-S-DYN-RTZ-01", - "rv64i_m/F/FADD-S-DYN-RUP-01", - "rv64i_m/F/FADD-S-RDN-01", - "rv64i_m/F/FADD-S-RMM-01", - "rv64i_m/F/FADD-S-RNE-01", - "rv64i_m/F/FADD-S-RTZ-01", - "rv64i_m/F/FADD-S-RUP-01", - "rv64i_m/F/FCLASS-S-01", - "rv64i_m/F/FCVT-L-S-DYN-RDN-01", - "rv64i_m/F/FCVT-L-S-DYN-RMM-01", - "rv64i_m/F/FCVT-L-S-DYN-RNE-01", - "rv64i_m/F/FCVT-L-S-DYN-RTZ-01", - "rv64i_m/F/FCVT-L-S-DYN-RUP-01", - "rv64i_m/F/FCVT-L-S-RDN-01", - "rv64i_m/F/FCVT-L-S-RMM-01", - "rv64i_m/F/FCVT-L-S-RNE-01", - "rv64i_m/F/FCVT-L-S-RTZ-01", - "rv64i_m/F/FCVT-L-S-RUP-01", - "rv64i_m/F/FCVT-LU-S-DYN-RDN-01", - "rv64i_m/F/FCVT-LU-S-DYN-RMM-01", - "rv64i_m/F/FCVT-LU-S-DYN-RNE-01", - "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01", - "rv64i_m/F/FCVT-LU-S-DYN-RUP-01", - "rv64i_m/F/FCVT-LU-S-RDN-01", - "rv64i_m/F/FCVT-LU-S-RMM-01", - "rv64i_m/F/FCVT-LU-S-RNE-01", - "rv64i_m/F/FCVT-LU-S-RTZ-01", - "rv64i_m/F/FCVT-LU-S-RUP-01", - "rv64i_m/F/FCVT-S-L-DYN-RDN-01", - "rv64i_m/F/FCVT-S-L-DYN-RMM-01", - "rv64i_m/F/FCVT-S-L-DYN-RNE-01", - "rv64i_m/F/FCVT-S-L-DYN-RTZ-01", - "rv64i_m/F/FCVT-S-L-DYN-RUP-01", - "rv64i_m/F/FCVT-S-L-RDN-01", - "rv64i_m/F/FCVT-S-L-RMM-01", - "rv64i_m/F/FCVT-S-L-RNE-01", - "rv64i_m/F/FCVT-S-L-RTZ-01", - "rv64i_m/F/FCVT-S-L-RUP-01", - "rv64i_m/F/FCVT-S-LU-DYN-RDN-01", - "rv64i_m/F/FCVT-S-LU-DYN-RMM-01", - "rv64i_m/F/FCVT-S-LU-DYN-RNE-01", - "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01", - "rv64i_m/F/FCVT-S-LU-DYN-RUP-01", - "rv64i_m/F/FCVT-S-LU-RDN-01", - "rv64i_m/F/FCVT-S-LU-RMM-01", - "rv64i_m/F/FCVT-S-LU-RNE-01", - "rv64i_m/F/FCVT-S-LU-RTZ-01", - "rv64i_m/F/FCVT-S-LU-RUP-01", - "rv64i_m/F/FCVT-S-W-DYN-RDN-01", - "rv64i_m/F/FCVT-S-W-DYN-RMM-01", - "rv64i_m/F/FCVT-S-W-DYN-RNE-01", - "rv64i_m/F/FCVT-S-W-DYN-RTZ-01", - "rv64i_m/F/FCVT-S-W-DYN-RUP-01", - "rv64i_m/F/FCVT-S-W-RDN-01", - "rv64i_m/F/FCVT-S-W-RMM-01", - "rv64i_m/F/FCVT-S-W-RNE-01", - "rv64i_m/F/FCVT-S-W-RTZ-01", - "rv64i_m/F/FCVT-S-W-RUP-01", - "rv64i_m/F/FCVT-S-WU-DYN-RDN-01", - "rv64i_m/F/FCVT-S-WU-DYN-RMM-01", - "rv64i_m/F/FCVT-S-WU-DYN-RNE-01", - "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01", - "rv64i_m/F/FCVT-S-WU-DYN-RUP-01", - "rv64i_m/F/FCVT-S-WU-RDN-01", - "rv64i_m/F/FCVT-S-WU-RMM-01", - "rv64i_m/F/FCVT-S-WU-RNE-01", - "rv64i_m/F/FCVT-S-WU-RTZ-01", - "rv64i_m/F/FCVT-S-WU-RUP-01", - "rv64i_m/F/FCVT-W-S-DYN-RDN-01", - "rv64i_m/F/FCVT-W-S-DYN-RMM-01", - "rv64i_m/F/FCVT-W-S-DYN-RNE-01", - "rv64i_m/F/FCVT-W-S-DYN-RTZ-01", - "rv64i_m/F/FCVT-W-S-DYN-RUP-01", - "rv64i_m/F/FCVT-W-S-RDN-01", - "rv64i_m/F/FCVT-W-S-RMM-01", - "rv64i_m/F/FCVT-W-S-RNE-01", - "rv64i_m/F/FCVT-W-S-RTZ-01", - "rv64i_m/F/FCVT-W-S-RUP-01", - "rv64i_m/F/FCVT-WU-S-DYN-RDN-01", - "rv64i_m/F/FCVT-WU-S-DYN-RMM-01", - "rv64i_m/F/FCVT-WU-S-DYN-RNE-01", - "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01", - "rv64i_m/F/FCVT-WU-S-DYN-RUP-01", - "rv64i_m/F/FCVT-WU-S-RDN-01", - "rv64i_m/F/FCVT-WU-S-RMM-01", - "rv64i_m/F/FCVT-WU-S-RNE-01", - "rv64i_m/F/FCVT-WU-S-RTZ-01", - "rv64i_m/F/FCVT-WU-S-RUP-01", - "rv64i_m/F/FDIV-S-DYN-RDN-01", - "rv64i_m/F/FDIV-S-DYN-RMM-01", - "rv64i_m/F/FDIV-S-DYN-RNE-01", - "rv64i_m/F/FDIV-S-DYN-RTZ-01", - "rv64i_m/F/FDIV-S-DYN-RUP-01", - "rv64i_m/F/FDIV-S-RDN-01", - "rv64i_m/F/FDIV-S-RMM-01", - "rv64i_m/F/FDIV-S-RNE-01", - "rv64i_m/F/FDIV-S-RTZ-01", - "rv64i_m/F/FDIV-S-RUP-01", - "rv64i_m/F/FEQ-S-01", - "rv64i_m/F/FLE-S-01", - "rv64i_m/F/FLT-S-01", - "rv64i_m/F/FLW-01", - "rv64i_m/F/FMADD-S-DYN-RDN-01", - "rv64i_m/F/FMADD-S-DYN-RMM-01", - "rv64i_m/F/FMADD-S-DYN-RNE-01", - "rv64i_m/F/FMADD-S-DYN-RTZ-01", - "rv64i_m/F/FMADD-S-DYN-RUP-01", - "rv64i_m/F/FMADD-S-RDN-01", - "rv64i_m/F/FMADD-S-RMM-01", - "rv64i_m/F/FMADD-S-RNE-01", - "rv64i_m/F/FMADD-S-RTZ-01", - "rv64i_m/F/FMADD-S-RUP-01", - "rv64i_m/F/FMAX-S-01", - "rv64i_m/F/FMIN-S-01", - "rv64i_m/F/FMSUB-S-DYN-RDN-01", - "rv64i_m/F/FMSUB-S-DYN-RMM-01", - "rv64i_m/F/FMSUB-S-DYN-RNE-01", - "rv64i_m/F/FMSUB-S-DYN-RTZ-01", - "rv64i_m/F/FMSUB-S-DYN-RUP-01", - "rv64i_m/F/FMSUB-S-RDN-01", - "rv64i_m/F/FMSUB-S-RMM-01", - "rv64i_m/F/FMSUB-S-RNE-01", - "rv64i_m/F/FMSUB-S-RTZ-01", - "rv64i_m/F/FMSUB-S-RUP-01", - "rv64i_m/F/FMUL-S-DYN-RDN-01", - "rv64i_m/F/FMUL-S-DYN-RMM-01", - "rv64i_m/F/FMUL-S-DYN-RNE-01", - "rv64i_m/F/FMUL-S-DYN-RTZ-01", - "rv64i_m/F/FMUL-S-DYN-RUP-01", - "rv64i_m/F/FMUL-S-RDN-01", - "rv64i_m/F/FMUL-S-RMM-01", - "rv64i_m/F/FMUL-S-RNE-01", - "rv64i_m/F/FMUL-S-RTZ-01", - "rv64i_m/F/FMUL-S-RUP-01", - "rv64i_m/F/FMV-W-X-01", - "rv64i_m/F/FMV-X-W-01", - "rv64i_m/F/FNMADD-S-DYN-RDN-01", - "rv64i_m/F/FNMADD-S-DYN-RMM-01", - "rv64i_m/F/FNMADD-S-DYN-RNE-01", - "rv64i_m/F/FNMADD-S-DYN-RTZ-01", - "rv64i_m/F/FNMADD-S-DYN-RUP-01", - "rv64i_m/F/FNMADD-S-RDN-01", - "rv64i_m/F/FNMADD-S-RMM-01", - "rv64i_m/F/FNMADD-S-RNE-01", - "rv64i_m/F/FNMADD-S-RTZ-01", - "rv64i_m/F/FNMADD-S-RUP-01", - "rv64i_m/F/FNMSUB-S-DYN-RDN-01", - "rv64i_m/F/FNMSUB-S-DYN-RMM-01", - "rv64i_m/F/FNMSUB-S-DYN-RNE-01", - "rv64i_m/F/FNMSUB-S-DYN-RTZ-01", - "rv64i_m/F/FNMSUB-S-DYN-RUP-01", - "rv64i_m/F/FNMSUB-S-RDN-01", - "rv64i_m/F/FNMSUB-S-RMM-01", - "rv64i_m/F/FNMSUB-S-RNE-01", - "rv64i_m/F/FNMSUB-S-RTZ-01", - "rv64i_m/F/FNMSUB-S-RUP-01", - "rv64i_m/F/FSGNJN-S-01", - "rv64i_m/F/FSGNJ-S-01", - "rv64i_m/F/FSGNJX-S-01", - "rv64i_m/F/FSQRT-S-DYN-RDN-01", - "rv64i_m/F/FSQRT-S-DYN-RMM-01", - "rv64i_m/F/FSQRT-S-DYN-RNE-01", - "rv64i_m/F/FSQRT-S-DYN-RTZ-01", - "rv64i_m/F/FSQRT-S-DYN-RUP-01", - "rv64i_m/F/FSQRT-S-RDN-01", - "rv64i_m/F/FSQRT-S-RMM-01", - "rv64i_m/F/FSQRT-S-RNE-01", - "rv64i_m/F/FSQRT-S-RTZ-01", - "rv64i_m/F/FSQRT-S-RUP-01", - "rv64i_m/F/FSUB-S-DYN-RDN-01", - "rv64i_m/F/FSUB-S-DYN-RMM-01", - "rv64i_m/F/FSUB-S-DYN-RNE-01", - "rv64i_m/F/FSUB-S-DYN-RTZ-01", - "rv64i_m/F/FSUB-S-DYN-RUP-01", - "rv64i_m/F/FSUB-S-RDN-01", - "rv64i_m/F/FSUB-S-RMM-01", - "rv64i_m/F/FSUB-S-RNE-01", - "rv64i_m/F/FSUB-S-RTZ-01", - "rv64i_m/F/FSUB-S-RUP-01", - "rv64i_m/F/FSW-01" + "rv64i_m/F/FADD-S-DYN-RDN-01.S", + "rv64i_m/F/FADD-S-DYN-RMM-01.S", + "rv64i_m/F/FADD-S-DYN-RNE-01.S", + "rv64i_m/F/FADD-S-DYN-RTZ-01.S", + "rv64i_m/F/FADD-S-DYN-RUP-01.S", + "rv64i_m/F/FADD-S-RDN-01.S", + "rv64i_m/F/FADD-S-RMM-01.S", + "rv64i_m/F/FADD-S-RNE-01.S", + "rv64i_m/F/FADD-S-RTZ-01.S", + "rv64i_m/F/FADD-S-RUP-01.S", + "rv64i_m/F/FCLASS-S-01.S", + "rv64i_m/F/FCVT-L-S-DYN-RDN-01.S", + "rv64i_m/F/FCVT-L-S-DYN-RMM-01.S", + "rv64i_m/F/FCVT-L-S-DYN-RNE-01.S", + "rv64i_m/F/FCVT-L-S-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-L-S-DYN-RUP-01.S", + "rv64i_m/F/FCVT-L-S-RDN-01.S", + "rv64i_m/F/FCVT-L-S-RMM-01.S", + "rv64i_m/F/FCVT-L-S-RNE-01.S", + "rv64i_m/F/FCVT-L-S-RTZ-01.S", + "rv64i_m/F/FCVT-L-S-RUP-01.S", + "rv64i_m/F/FCVT-LU-S-DYN-RDN-01.S", + "rv64i_m/F/FCVT-LU-S-DYN-RMM-01.S", + "rv64i_m/F/FCVT-LU-S-DYN-RNE-01.S", + "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-LU-S-DYN-RUP-01.S", + "rv64i_m/F/FCVT-LU-S-RDN-01.S", + "rv64i_m/F/FCVT-LU-S-RMM-01.S", + "rv64i_m/F/FCVT-LU-S-RNE-01.S", + "rv64i_m/F/FCVT-LU-S-RTZ-01.S", + "rv64i_m/F/FCVT-LU-S-RUP-01.S", + "rv64i_m/F/FCVT-S-L-DYN-RDN-01.S", + "rv64i_m/F/FCVT-S-L-DYN-RMM-01.S", + "rv64i_m/F/FCVT-S-L-DYN-RNE-01.S", + "rv64i_m/F/FCVT-S-L-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-S-L-DYN-RUP-01.S", + "rv64i_m/F/FCVT-S-L-RDN-01.S", + "rv64i_m/F/FCVT-S-L-RMM-01.S", + "rv64i_m/F/FCVT-S-L-RNE-01.S", + "rv64i_m/F/FCVT-S-L-RTZ-01.S", + "rv64i_m/F/FCVT-S-L-RUP-01.S", + "rv64i_m/F/FCVT-S-LU-DYN-RDN-01.S", + "rv64i_m/F/FCVT-S-LU-DYN-RMM-01.S", + "rv64i_m/F/FCVT-S-LU-DYN-RNE-01.S", + "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-S-LU-DYN-RUP-01.S", + "rv64i_m/F/FCVT-S-LU-RDN-01.S", + "rv64i_m/F/FCVT-S-LU-RMM-01.S", + "rv64i_m/F/FCVT-S-LU-RNE-01.S", + "rv64i_m/F/FCVT-S-LU-RTZ-01.S", + "rv64i_m/F/FCVT-S-LU-RUP-01.S", + "rv64i_m/F/FCVT-S-W-DYN-RDN-01.S", + "rv64i_m/F/FCVT-S-W-DYN-RMM-01.S", + "rv64i_m/F/FCVT-S-W-DYN-RNE-01.S", + "rv64i_m/F/FCVT-S-W-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-S-W-DYN-RUP-01.S", + "rv64i_m/F/FCVT-S-W-RDN-01.S", + "rv64i_m/F/FCVT-S-W-RMM-01.S", + "rv64i_m/F/FCVT-S-W-RNE-01.S", + "rv64i_m/F/FCVT-S-W-RTZ-01.S", + "rv64i_m/F/FCVT-S-W-RUP-01.S", + "rv64i_m/F/FCVT-S-WU-DYN-RDN-01.S", + "rv64i_m/F/FCVT-S-WU-DYN-RMM-01.S", + "rv64i_m/F/FCVT-S-WU-DYN-RNE-01.S", + "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-S-WU-DYN-RUP-01.S", + "rv64i_m/F/FCVT-S-WU-RDN-01.S", + "rv64i_m/F/FCVT-S-WU-RMM-01.S", + "rv64i_m/F/FCVT-S-WU-RNE-01.S", + "rv64i_m/F/FCVT-S-WU-RTZ-01.S", + "rv64i_m/F/FCVT-S-WU-RUP-01.S", + "rv64i_m/F/FCVT-W-S-DYN-RDN-01.S", + "rv64i_m/F/FCVT-W-S-DYN-RMM-01.S", + "rv64i_m/F/FCVT-W-S-DYN-RNE-01.S", + "rv64i_m/F/FCVT-W-S-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-W-S-DYN-RUP-01.S", + "rv64i_m/F/FCVT-W-S-RDN-01.S", + "rv64i_m/F/FCVT-W-S-RMM-01.S", + "rv64i_m/F/FCVT-W-S-RNE-01.S", + "rv64i_m/F/FCVT-W-S-RTZ-01.S", + "rv64i_m/F/FCVT-W-S-RUP-01.S", + "rv64i_m/F/FCVT-WU-S-DYN-RDN-01.S", + "rv64i_m/F/FCVT-WU-S-DYN-RMM-01.S", + "rv64i_m/F/FCVT-WU-S-DYN-RNE-01.S", + "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01.S", + "rv64i_m/F/FCVT-WU-S-DYN-RUP-01.S", + "rv64i_m/F/FCVT-WU-S-RDN-01.S", + "rv64i_m/F/FCVT-WU-S-RMM-01.S", + "rv64i_m/F/FCVT-WU-S-RNE-01.S", + "rv64i_m/F/FCVT-WU-S-RTZ-01.S", + "rv64i_m/F/FCVT-WU-S-RUP-01.S", + "rv64i_m/F/FDIV-S-DYN-RDN-01.S", + "rv64i_m/F/FDIV-S-DYN-RMM-01.S", + "rv64i_m/F/FDIV-S-DYN-RNE-01.S", + "rv64i_m/F/FDIV-S-DYN-RTZ-01.S", + "rv64i_m/F/FDIV-S-DYN-RUP-01.S", + "rv64i_m/F/FDIV-S-RDN-01.S", + "rv64i_m/F/FDIV-S-RMM-01.S", + "rv64i_m/F/FDIV-S-RNE-01.S", + "rv64i_m/F/FDIV-S-RTZ-01.S", + "rv64i_m/F/FDIV-S-RUP-01.S", + "rv64i_m/F/FEQ-S-01.S", + "rv64i_m/F/FLE-S-01.S", + "rv64i_m/F/FLT-S-01.S", + "rv64i_m/F/FLW-01.S", + "rv64i_m/F/FMADD-S-DYN-RDN-01.S", + "rv64i_m/F/FMADD-S-DYN-RMM-01.S", + "rv64i_m/F/FMADD-S-DYN-RNE-01.S", + "rv64i_m/F/FMADD-S-DYN-RTZ-01.S", + "rv64i_m/F/FMADD-S-DYN-RUP-01.S", + "rv64i_m/F/FMADD-S-RDN-01.S", + "rv64i_m/F/FMADD-S-RMM-01.S", + "rv64i_m/F/FMADD-S-RNE-01.S", + "rv64i_m/F/FMADD-S-RTZ-01.S", + "rv64i_m/F/FMADD-S-RUP-01.S", + "rv64i_m/F/FMAX-S-01.S", + "rv64i_m/F/FMIN-S-01.S", + "rv64i_m/F/FMSUB-S-DYN-RDN-01.S", + "rv64i_m/F/FMSUB-S-DYN-RMM-01.S", + "rv64i_m/F/FMSUB-S-DYN-RNE-01.S", + "rv64i_m/F/FMSUB-S-DYN-RTZ-01.S", + "rv64i_m/F/FMSUB-S-DYN-RUP-01.S", + "rv64i_m/F/FMSUB-S-RDN-01.S", + "rv64i_m/F/FMSUB-S-RMM-01.S", + "rv64i_m/F/FMSUB-S-RNE-01.S", + "rv64i_m/F/FMSUB-S-RTZ-01.S", + "rv64i_m/F/FMSUB-S-RUP-01.S", + "rv64i_m/F/FMUL-S-DYN-RDN-01.S", + "rv64i_m/F/FMUL-S-DYN-RMM-01.S", + "rv64i_m/F/FMUL-S-DYN-RNE-01.S", + "rv64i_m/F/FMUL-S-DYN-RTZ-01.S", + "rv64i_m/F/FMUL-S-DYN-RUP-01.S", + "rv64i_m/F/FMUL-S-RDN-01.S", + "rv64i_m/F/FMUL-S-RMM-01.S", + "rv64i_m/F/FMUL-S-RNE-01.S", + "rv64i_m/F/FMUL-S-RTZ-01.S", + "rv64i_m/F/FMUL-S-RUP-01.S", + "rv64i_m/F/FMV-W-X-01.S", + "rv64i_m/F/FMV-X-W-01.S", + "rv64i_m/F/FNMADD-S-DYN-RDN-01.S", + "rv64i_m/F/FNMADD-S-DYN-RMM-01.S", + "rv64i_m/F/FNMADD-S-DYN-RNE-01.S", + "rv64i_m/F/FNMADD-S-DYN-RTZ-01.S", + "rv64i_m/F/FNMADD-S-DYN-RUP-01.S", + "rv64i_m/F/FNMADD-S-RDN-01.S", + "rv64i_m/F/FNMADD-S-RMM-01.S", + "rv64i_m/F/FNMADD-S-RNE-01.S", + "rv64i_m/F/FNMADD-S-RTZ-01.S", + "rv64i_m/F/FNMADD-S-RUP-01.S", + "rv64i_m/F/FNMSUB-S-DYN-RDN-01.S", + "rv64i_m/F/FNMSUB-S-DYN-RMM-01.S", + "rv64i_m/F/FNMSUB-S-DYN-RNE-01.S", + "rv64i_m/F/FNMSUB-S-DYN-RTZ-01.S", + "rv64i_m/F/FNMSUB-S-DYN-RUP-01.S", + "rv64i_m/F/FNMSUB-S-RDN-01.S", + "rv64i_m/F/FNMSUB-S-RMM-01.S", + "rv64i_m/F/FNMSUB-S-RNE-01.S", + "rv64i_m/F/FNMSUB-S-RTZ-01.S", + "rv64i_m/F/FNMSUB-S-RUP-01.S", + "rv64i_m/F/FSGNJN-S-01.S", + "rv64i_m/F/FSGNJ-S-01.S", + "rv64i_m/F/FSGNJX-S-01.S", + "rv64i_m/F/FSQRT-S-DYN-RDN-01.S", + "rv64i_m/F/FSQRT-S-DYN-RMM-01.S", + "rv64i_m/F/FSQRT-S-DYN-RNE-01.S", + "rv64i_m/F/FSQRT-S-DYN-RTZ-01.S", + "rv64i_m/F/FSQRT-S-DYN-RUP-01.S", + "rv64i_m/F/FSQRT-S-RDN-01.S", + "rv64i_m/F/FSQRT-S-RMM-01.S", + "rv64i_m/F/FSQRT-S-RNE-01.S", + "rv64i_m/F/FSQRT-S-RTZ-01.S", + "rv64i_m/F/FSQRT-S-RUP-01.S", + "rv64i_m/F/FSUB-S-DYN-RDN-01.S", + "rv64i_m/F/FSUB-S-DYN-RMM-01.S", + "rv64i_m/F/FSUB-S-DYN-RNE-01.S", + "rv64i_m/F/FSUB-S-DYN-RTZ-01.S", + "rv64i_m/F/FSUB-S-DYN-RUP-01.S", + "rv64i_m/F/FSUB-S-RDN-01.S", + "rv64i_m/F/FSUB-S-RMM-01.S", + "rv64i_m/F/FSUB-S-RNE-01.S", + "rv64i_m/F/FSUB-S-RTZ-01.S", + "rv64i_m/F/FSUB-S-RUP-01.S", + "rv64i_m/F/FSW-01.S" }; string imperas64d[] = '{ `IMPERASTEST, - "rv64i_m/D/FADD-D-DYN-RDN-01", - "rv64i_m/D/FADD-D-DYN-RMM-01", - "rv64i_m/D/FADD-D-DYN-RNE-01", - "rv64i_m/D/FADD-D-DYN-RTZ-01", - "rv64i_m/D/FADD-D-DYN-RUP-01", - "rv64i_m/D/FADD-D-RDN-01", - "rv64i_m/D/FADD-D-RMM-01", - "rv64i_m/D/FADD-D-RNE-01", - "rv64i_m/D/FADD-D-RTZ-01", - "rv64i_m/D/FADD-D-RUP-01", - "rv64i_m/D/FCLASS-D-01", - "rv64i_m/D/FCVT-D-L-DYN-RDN-01", - "rv64i_m/D/FCVT-D-L-DYN-RMM-01", - "rv64i_m/D/FCVT-D-L-DYN-RNE-01", - "rv64i_m/D/FCVT-D-L-DYN-RTZ-01", - "rv64i_m/D/FCVT-D-L-DYN-RUP-01", - "rv64i_m/D/FCVT-D-L-RDN-01", - "rv64i_m/D/FCVT-D-L-RMM-01", - "rv64i_m/D/FCVT-D-L-RNE-01", - "rv64i_m/D/FCVT-D-L-RTZ-01", - "rv64i_m/D/FCVT-D-L-RUP-01", - "rv64i_m/D/FCVT-D-LU-DYN-RDN-01", - "rv64i_m/D/FCVT-D-LU-DYN-RMM-01", - "rv64i_m/D/FCVT-D-LU-DYN-RNE-01", - "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01", - "rv64i_m/D/FCVT-D-LU-DYN-RUP-01", - "rv64i_m/D/FCVT-D-LU-RDN-01", - "rv64i_m/D/FCVT-D-LU-RMM-01", - "rv64i_m/D/FCVT-D-LU-RNE-01", - "rv64i_m/D/FCVT-D-LU-RTZ-01", - "rv64i_m/D/FCVT-D-LU-RUP-01", - "rv64i_m/D/FCVT-D-S-01", - "rv64i_m/D/FCVT-D-W-01", - "rv64i_m/D/FCVT-D-WU-01", - "rv64i_m/D/FCVT-L-D-DYN-RDN-01", - "rv64i_m/D/FCVT-L-D-DYN-RMM-01", - "rv64i_m/D/FCVT-L-D-DYN-RNE-01", - "rv64i_m/D/FCVT-L-D-DYN-RTZ-01", - "rv64i_m/D/FCVT-L-D-DYN-RUP-01", - "rv64i_m/D/FCVT-L-D-RDN-01", - "rv64i_m/D/FCVT-L-D-RMM-01", - "rv64i_m/D/FCVT-L-D-RNE-01", - "rv64i_m/D/FCVT-L-D-RTZ-01", - "rv64i_m/D/FCVT-L-D-RUP-01", - "rv64i_m/D/FCVT-LU-D-DYN-RDN-01", - "rv64i_m/D/FCVT-LU-D-DYN-RMM-01", - "rv64i_m/D/FCVT-LU-D-DYN-RNE-01", - "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01", - "rv64i_m/D/FCVT-LU-D-DYN-RUP-01", - "rv64i_m/D/FCVT-LU-D-RDN-01", - "rv64i_m/D/FCVT-LU-D-RMM-01", - "rv64i_m/D/FCVT-LU-D-RNE-01", - "rv64i_m/D/FCVT-LU-D-RTZ-01", - "rv64i_m/D/FCVT-LU-D-RUP-01", - "rv64i_m/D/FCVT-S-D-DYN-RDN-01", - "rv64i_m/D/FCVT-S-D-DYN-RMM-01", - "rv64i_m/D/FCVT-S-D-DYN-RNE-01", - "rv64i_m/D/FCVT-S-D-DYN-RTZ-01", - "rv64i_m/D/FCVT-S-D-DYN-RUP-01", - "rv64i_m/D/FCVT-S-D-RDN-01", - "rv64i_m/D/FCVT-S-D-RMM-01", - "rv64i_m/D/FCVT-S-D-RNE-01", - "rv64i_m/D/FCVT-S-D-RTZ-01", - "rv64i_m/D/FCVT-S-D-RUP-01", - "rv64i_m/D/FCVT-W-D-DYN-RDN-01", - "rv64i_m/D/FCVT-W-D-DYN-RMM-01", - "rv64i_m/D/FCVT-W-D-DYN-RNE-01", - "rv64i_m/D/FCVT-W-D-DYN-RTZ-01", - "rv64i_m/D/FCVT-W-D-DYN-RUP-01", - "rv64i_m/D/FCVT-W-D-RDN-01", - "rv64i_m/D/FCVT-W-D-RMM-01", - "rv64i_m/D/FCVT-W-D-RNE-01", - "rv64i_m/D/FCVT-W-D-RTZ-01", - "rv64i_m/D/FCVT-W-D-RUP-01", - "rv64i_m/D/FCVT-WU-D-DYN-RDN-01", - "rv64i_m/D/FCVT-WU-D-DYN-RMM-01", - "rv64i_m/D/FCVT-WU-D-DYN-RNE-01", - "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01", - "rv64i_m/D/FCVT-WU-D-DYN-RUP-01", - "rv64i_m/D/FCVT-WU-D-RDN-01", - "rv64i_m/D/FCVT-WU-D-RMM-01", - "rv64i_m/D/FCVT-WU-D-RNE-01", - "rv64i_m/D/FCVT-WU-D-RTZ-01", - "rv64i_m/D/FCVT-WU-D-RUP-01", - "rv64i_m/D/FDIV-D-DYN-RDN-01", - "rv64i_m/D/FDIV-D-DYN-RMM-01", - "rv64i_m/D/FDIV-D-DYN-RNE-01", - "rv64i_m/D/FDIV-D-DYN-RTZ-01", - "rv64i_m/D/FDIV-D-DYN-RUP-01", - "rv64i_m/D/FDIV-D-RDN-01", - "rv64i_m/D/FDIV-D-RMM-01", - "rv64i_m/D/FDIV-D-RNE-01", - "rv64i_m/D/FDIV-D-RTZ-01", - "rv64i_m/D/FDIV-D-RUP-01", - "rv64i_m/D/FEQ-D-01", - "rv64i_m/D/FLD-01", - "rv64i_m/D/FLE-D-01", - "rv64i_m/D/FLT-D-01", - "rv64i_m/D/FMADD-D-DYN-RDN-01", - "rv64i_m/D/FMADD-D-DYN-RMM-01", - "rv64i_m/D/FMADD-D-DYN-RNE-01", - "rv64i_m/D/FMADD-D-DYN-RTZ-01", - "rv64i_m/D/FMADD-D-DYN-RUP-01", - "rv64i_m/D/FMADD-D-RDN-01", - "rv64i_m/D/FMADD-D-RMM-01", - "rv64i_m/D/FMADD-D-RNE-01", - "rv64i_m/D/FMADD-D-RTZ-01", - "rv64i_m/D/FMADD-D-RUP-01", - "rv64i_m/D/FMAX-D-01", - "rv64i_m/D/FMIN-D-01", - "rv64i_m/D/FMSUB-D-DYN-RDN-01", - "rv64i_m/D/FMSUB-D-DYN-RMM-01", - "rv64i_m/D/FMSUB-D-DYN-RNE-01", - "rv64i_m/D/FMSUB-D-DYN-RTZ-01", - "rv64i_m/D/FMSUB-D-DYN-RUP-01", - "rv64i_m/D/FMSUB-D-RDN-01", - "rv64i_m/D/FMSUB-D-RMM-01", - "rv64i_m/D/FMSUB-D-RNE-01", - "rv64i_m/D/FMSUB-D-RTZ-01", - "rv64i_m/D/FMSUB-D-RUP-01", - "rv64i_m/D/FMUL-D-DYN-RDN-01", - "rv64i_m/D/FMUL-D-DYN-RMM-01", - "rv64i_m/D/FMUL-D-DYN-RNE-01", - "rv64i_m/D/FMUL-D-DYN-RTZ-01", - "rv64i_m/D/FMUL-D-DYN-RUP-01", - "rv64i_m/D/FMUL-D-RDN-01", - "rv64i_m/D/FMUL-D-RMM-01", - "rv64i_m/D/FMUL-D-RNE-01", - "rv64i_m/D/FMUL-D-RTZ-01", - "rv64i_m/D/FMUL-D-RUP-01", - "rv64i_m/D/FMV-D-X-01", - "rv64i_m/D/FMV-X-D-01", - "rv64i_m/D/FNMADD-D-DYN-RDN-01", - "rv64i_m/D/FNMADD-D-DYN-RMM-01", - "rv64i_m/D/FNMADD-D-DYN-RNE-01", - "rv64i_m/D/FNMADD-D-DYN-RTZ-01", - "rv64i_m/D/FNMADD-D-DYN-RUP-01", - "rv64i_m/D/FNMADD-D-RDN-01", - "rv64i_m/D/FNMADD-D-RMM-01", - "rv64i_m/D/FNMADD-D-RNE-01", - "rv64i_m/D/FNMADD-D-RTZ-01", - "rv64i_m/D/FNMADD-D-RUP-01", - "rv64i_m/D/FNMSUB-D-DYN-RDN-01", - "rv64i_m/D/FNMSUB-D-DYN-RMM-01", - "rv64i_m/D/FNMSUB-D-DYN-RNE-01", - "rv64i_m/D/FNMSUB-D-DYN-RTZ-01", - "rv64i_m/D/FNMSUB-D-DYN-RUP-01", - "rv64i_m/D/FNMSUB-D-RDN-01", - "rv64i_m/D/FNMSUB-D-RMM-01", - "rv64i_m/D/FNMSUB-D-RNE-01", - "rv64i_m/D/FNMSUB-D-RTZ-01", - "rv64i_m/D/FNMSUB-D-RUP-01", - "rv64i_m/D/FSD-01", - "rv64i_m/D/FSGNJ-D-01", - "rv64i_m/D/FSGNJN-D-01", - "rv64i_m/D/FSGNJX-D-01", - "rv64i_m/D/FSQRT-D-DYN-RDN-01", - "rv64i_m/D/FSQRT-D-DYN-RMM-01", - "rv64i_m/D/FSQRT-D-DYN-RNE-01", - "rv64i_m/D/FSQRT-D-DYN-RTZ-01", - "rv64i_m/D/FSQRT-D-DYN-RUP-01", - "rv64i_m/D/FSQRT-D-RDN-01", - "rv64i_m/D/FSQRT-D-RMM-01", - "rv64i_m/D/FSQRT-D-RNE-01", - "rv64i_m/D/FSQRT-D-RTZ-01", - "rv64i_m/D/FSQRT-D-RUP-01", - "rv64i_m/D/FSUB-D-DYN-RDN-01", - "rv64i_m/D/FSUB-D-DYN-RMM-01", - "rv64i_m/D/FSUB-D-DYN-RNE-01", - "rv64i_m/D/FSUB-D-DYN-RTZ-01", - "rv64i_m/D/FSUB-D-DYN-RUP-01", - "rv64i_m/D/FSUB-D-RDN-01", - "rv64i_m/D/FSUB-D-RMM-01", - "rv64i_m/D/FSUB-D-RNE-01", - "rv64i_m/D/FSUB-D-RTZ-01", - "rv64i_m/D/FSUB-D-RUP-01" + "rv64i_m/D/FADD-D-DYN-RDN-01.S", + "rv64i_m/D/FADD-D-DYN-RMM-01.S", + "rv64i_m/D/FADD-D-DYN-RNE-01.S", + "rv64i_m/D/FADD-D-DYN-RTZ-01.S", + "rv64i_m/D/FADD-D-DYN-RUP-01.S", + "rv64i_m/D/FADD-D-RDN-01.S", + "rv64i_m/D/FADD-D-RMM-01.S", + "rv64i_m/D/FADD-D-RNE-01.S", + "rv64i_m/D/FADD-D-RTZ-01.S", + "rv64i_m/D/FADD-D-RUP-01.S", + "rv64i_m/D/FCLASS-D-01.S", + "rv64i_m/D/FCVT-D-L-DYN-RDN-01.S", + "rv64i_m/D/FCVT-D-L-DYN-RMM-01.S", + "rv64i_m/D/FCVT-D-L-DYN-RNE-01.S", + "rv64i_m/D/FCVT-D-L-DYN-RTZ-01.S", + "rv64i_m/D/FCVT-D-L-DYN-RUP-01.S", + "rv64i_m/D/FCVT-D-L-RDN-01.S", + "rv64i_m/D/FCVT-D-L-RMM-01.S", + "rv64i_m/D/FCVT-D-L-RNE-01.S", + "rv64i_m/D/FCVT-D-L-RTZ-01.S", + "rv64i_m/D/FCVT-D-L-RUP-01.S", + "rv64i_m/D/FCVT-D-LU-DYN-RDN-01.S", + "rv64i_m/D/FCVT-D-LU-DYN-RMM-01.S", + "rv64i_m/D/FCVT-D-LU-DYN-RNE-01.S", + "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01.S", + "rv64i_m/D/FCVT-D-LU-DYN-RUP-01.S", + "rv64i_m/D/FCVT-D-LU-RDN-01.S", + "rv64i_m/D/FCVT-D-LU-RMM-01.S", + "rv64i_m/D/FCVT-D-LU-RNE-01.S", + "rv64i_m/D/FCVT-D-LU-RTZ-01.S", + "rv64i_m/D/FCVT-D-LU-RUP-01.S", + "rv64i_m/D/FCVT-D-S-01.S", + "rv64i_m/D/FCVT-D-W-01.S", + "rv64i_m/D/FCVT-D-WU-01.S", + "rv64i_m/D/FCVT-L-D-DYN-RDN-01.S", + "rv64i_m/D/FCVT-L-D-DYN-RMM-01.S", + "rv64i_m/D/FCVT-L-D-DYN-RNE-01.S", + "rv64i_m/D/FCVT-L-D-DYN-RTZ-01.S", + "rv64i_m/D/FCVT-L-D-DYN-RUP-01.S", + "rv64i_m/D/FCVT-L-D-RDN-01.S", + "rv64i_m/D/FCVT-L-D-RMM-01.S", + "rv64i_m/D/FCVT-L-D-RNE-01.S", + "rv64i_m/D/FCVT-L-D-RTZ-01.S", + "rv64i_m/D/FCVT-L-D-RUP-01.S", + "rv64i_m/D/FCVT-LU-D-DYN-RDN-01.S", + "rv64i_m/D/FCVT-LU-D-DYN-RMM-01.S", + "rv64i_m/D/FCVT-LU-D-DYN-RNE-01.S", + "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01.S", + "rv64i_m/D/FCVT-LU-D-DYN-RUP-01.S", + "rv64i_m/D/FCVT-LU-D-RDN-01.S", + "rv64i_m/D/FCVT-LU-D-RMM-01.S", + "rv64i_m/D/FCVT-LU-D-RNE-01.S", + "rv64i_m/D/FCVT-LU-D-RTZ-01.S", + "rv64i_m/D/FCVT-LU-D-RUP-01.S", + "rv64i_m/D/FCVT-S-D-DYN-RDN-01.S", + "rv64i_m/D/FCVT-S-D-DYN-RMM-01.S", + "rv64i_m/D/FCVT-S-D-DYN-RNE-01.S", + "rv64i_m/D/FCVT-S-D-DYN-RTZ-01.S", + "rv64i_m/D/FCVT-S-D-DYN-RUP-01.S", + "rv64i_m/D/FCVT-S-D-RDN-01.S", + "rv64i_m/D/FCVT-S-D-RMM-01.S", + "rv64i_m/D/FCVT-S-D-RNE-01.S", + "rv64i_m/D/FCVT-S-D-RTZ-01.S", + "rv64i_m/D/FCVT-S-D-RUP-01.S", + "rv64i_m/D/FCVT-W-D-DYN-RDN-01.S", + "rv64i_m/D/FCVT-W-D-DYN-RMM-01.S", + "rv64i_m/D/FCVT-W-D-DYN-RNE-01.S", + "rv64i_m/D/FCVT-W-D-DYN-RTZ-01.S", + "rv64i_m/D/FCVT-W-D-DYN-RUP-01.S", + "rv64i_m/D/FCVT-W-D-RDN-01.S", + "rv64i_m/D/FCVT-W-D-RMM-01.S", + "rv64i_m/D/FCVT-W-D-RNE-01.S", + "rv64i_m/D/FCVT-W-D-RTZ-01.S", + "rv64i_m/D/FCVT-W-D-RUP-01.S", + "rv64i_m/D/FCVT-WU-D-DYN-RDN-01.S", + "rv64i_m/D/FCVT-WU-D-DYN-RMM-01.S", + "rv64i_m/D/FCVT-WU-D-DYN-RNE-01.S", + "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01.S", + "rv64i_m/D/FCVT-WU-D-DYN-RUP-01.S", + "rv64i_m/D/FCVT-WU-D-RDN-01.S", + "rv64i_m/D/FCVT-WU-D-RMM-01.S", + "rv64i_m/D/FCVT-WU-D-RNE-01.S", + "rv64i_m/D/FCVT-WU-D-RTZ-01.S", + "rv64i_m/D/FCVT-WU-D-RUP-01.S", + "rv64i_m/D/FDIV-D-DYN-RDN-01.S", + "rv64i_m/D/FDIV-D-DYN-RMM-01.S", + "rv64i_m/D/FDIV-D-DYN-RNE-01.S", + "rv64i_m/D/FDIV-D-DYN-RTZ-01.S", + "rv64i_m/D/FDIV-D-DYN-RUP-01.S", + "rv64i_m/D/FDIV-D-RDN-01.S", + "rv64i_m/D/FDIV-D-RMM-01.S", + "rv64i_m/D/FDIV-D-RNE-01.S", + "rv64i_m/D/FDIV-D-RTZ-01.S", + "rv64i_m/D/FDIV-D-RUP-01.S", + "rv64i_m/D/FEQ-D-01.S", + "rv64i_m/D/FLD-01.S", + "rv64i_m/D/FLE-D-01.S", + "rv64i_m/D/FLT-D-01.S", + "rv64i_m/D/FMADD-D-DYN-RDN-01.S", + "rv64i_m/D/FMADD-D-DYN-RMM-01.S", + "rv64i_m/D/FMADD-D-DYN-RNE-01.S", + "rv64i_m/D/FMADD-D-DYN-RTZ-01.S", + "rv64i_m/D/FMADD-D-DYN-RUP-01.S", + "rv64i_m/D/FMADD-D-RDN-01.S", + "rv64i_m/D/FMADD-D-RMM-01.S", + "rv64i_m/D/FMADD-D-RNE-01.S", + "rv64i_m/D/FMADD-D-RTZ-01.S", + "rv64i_m/D/FMADD-D-RUP-01.S", + "rv64i_m/D/FMAX-D-01.S", + "rv64i_m/D/FMIN-D-01.S", + "rv64i_m/D/FMSUB-D-DYN-RDN-01.S", + "rv64i_m/D/FMSUB-D-DYN-RMM-01.S", + "rv64i_m/D/FMSUB-D-DYN-RNE-01.S", + "rv64i_m/D/FMSUB-D-DYN-RTZ-01.S", + "rv64i_m/D/FMSUB-D-DYN-RUP-01.S", + "rv64i_m/D/FMSUB-D-RDN-01.S", + "rv64i_m/D/FMSUB-D-RMM-01.S", + "rv64i_m/D/FMSUB-D-RNE-01.S", + "rv64i_m/D/FMSUB-D-RTZ-01.S", + "rv64i_m/D/FMSUB-D-RUP-01.S", + "rv64i_m/D/FMUL-D-DYN-RDN-01.S", + "rv64i_m/D/FMUL-D-DYN-RMM-01.S", + "rv64i_m/D/FMUL-D-DYN-RNE-01.S", + "rv64i_m/D/FMUL-D-DYN-RTZ-01.S", + "rv64i_m/D/FMUL-D-DYN-RUP-01.S", + "rv64i_m/D/FMUL-D-RDN-01.S", + "rv64i_m/D/FMUL-D-RMM-01.S", + "rv64i_m/D/FMUL-D-RNE-01.S", + "rv64i_m/D/FMUL-D-RTZ-01.S", + "rv64i_m/D/FMUL-D-RUP-01.S", + "rv64i_m/D/FMV-D-X-01.S", + "rv64i_m/D/FMV-X-D-01.S", + "rv64i_m/D/FNMADD-D-DYN-RDN-01.S", + "rv64i_m/D/FNMADD-D-DYN-RMM-01.S", + "rv64i_m/D/FNMADD-D-DYN-RNE-01.S", + "rv64i_m/D/FNMADD-D-DYN-RTZ-01.S", + "rv64i_m/D/FNMADD-D-DYN-RUP-01.S", + "rv64i_m/D/FNMADD-D-RDN-01.S", + "rv64i_m/D/FNMADD-D-RMM-01.S", + "rv64i_m/D/FNMADD-D-RNE-01.S", + "rv64i_m/D/FNMADD-D-RTZ-01.S", + "rv64i_m/D/FNMADD-D-RUP-01.S", + "rv64i_m/D/FNMSUB-D-DYN-RDN-01.S", + "rv64i_m/D/FNMSUB-D-DYN-RMM-01.S", + "rv64i_m/D/FNMSUB-D-DYN-RNE-01.S", + "rv64i_m/D/FNMSUB-D-DYN-RTZ-01.S", + "rv64i_m/D/FNMSUB-D-DYN-RUP-01.S", + "rv64i_m/D/FNMSUB-D-RDN-01.S", + "rv64i_m/D/FNMSUB-D-RMM-01.S", + "rv64i_m/D/FNMSUB-D-RNE-01.S", + "rv64i_m/D/FNMSUB-D-RTZ-01.S", + "rv64i_m/D/FNMSUB-D-RUP-01.S", + "rv64i_m/D/FSD-01.S", + "rv64i_m/D/FSGNJ-D-01.S", + "rv64i_m/D/FSGNJN-D-01.S", + "rv64i_m/D/FSGNJX-D-01.S", + "rv64i_m/D/FSQRT-D-DYN-RDN-01.S", + "rv64i_m/D/FSQRT-D-DYN-RMM-01.S", + "rv64i_m/D/FSQRT-D-DYN-RNE-01.S", + "rv64i_m/D/FSQRT-D-DYN-RTZ-01.S", + "rv64i_m/D/FSQRT-D-DYN-RUP-01.S", + "rv64i_m/D/FSQRT-D-RDN-01.S", + "rv64i_m/D/FSQRT-D-RMM-01.S", + "rv64i_m/D/FSQRT-D-RNE-01.S", + "rv64i_m/D/FSQRT-D-RTZ-01.S", + "rv64i_m/D/FSQRT-D-RUP-01.S", + "rv64i_m/D/FSUB-D-DYN-RDN-01.S", + "rv64i_m/D/FSUB-D-DYN-RMM-01.S", + "rv64i_m/D/FSUB-D-DYN-RNE-01.S", + "rv64i_m/D/FSUB-D-DYN-RTZ-01.S", + "rv64i_m/D/FSUB-D-DYN-RUP-01.S", + "rv64i_m/D/FSUB-D-RDN-01.S", + "rv64i_m/D/FSUB-D-RMM-01.S", + "rv64i_m/D/FSUB-D-RNE-01.S", + "rv64i_m/D/FSUB-D-RTZ-01.S", + "rv64i_m/D/FSUB-D-RUP-01.S" }; string imperas64m[] = '{ `IMPERASTEST, - "rv64i_m/M/DIV-01", - "rv64i_m/M/DIVU-01", - "rv64i_m/M/DIVUW-01", - "rv64i_m/M/DIVW-01", - "rv64i_m/M/MUL-01", - "rv64i_m/M/MULH-01", - "rv64i_m/M/MULHSU-01", - "rv64i_m/M/MULHU-01", - "rv64i_m/M/MULW-01", - "rv64i_m/M/REM-01", - "rv64i_m/M/REMU-01", - "rv64i_m/M/REMUW-01", - "rv64i_m/M/REMW-01" + "rv64i_m/M/DIV-01.S", + "rv64i_m/M/DIVU-01.S", + "rv64i_m/M/DIVUW-01.S", + "rv64i_m/M/DIVW-01.S", + "rv64i_m/M/MUL-01.S", + "rv64i_m/M/MULH-01.S", + "rv64i_m/M/MULHSU-01.S", + "rv64i_m/M/MULHU-01.S", + "rv64i_m/M/MULW-01.S", + "rv64i_m/M/REM-01.S", + "rv64i_m/M/REMU-01.S", + "rv64i_m/M/REMUW-01.S", + "rv64i_m/M/REMW-01.S" }; string imperas64c[] = '{ `IMPERASTEST, - "rv64i_m/C/C-ADD-01", - "rv64i_m/C/C-ADDI-01", - "rv64i_m/C/C-ADDI16SP-01", - "rv64i_m/C/C-ADDI4SPN-01", - "rv64i_m/C/C-ADDIW-01", - "rv64i_m/C/C-ADDW-01", - "rv64i_m/C/C-AND-01", - "rv64i_m/C/C-ANDI-01", - "rv64i_m/C/C-BEQZ-01", - "rv64i_m/C/C-BNEZ-01", - "rv64i_m/C/C-J-01", - "rv64i_m/C/C-JALR-01", - "rv64i_m/C/C-JR-01", - "rv64i_m/C/C-LD-01", - "rv64i_m/C/C-LDSP-01", - "rv64i_m/C/C-LI-01", - "rv64i_m/C/C-LUI-01", - "rv64i_m/C/C-LW-01", - "rv64i_m/C/C-LWSP-01", - "rv64i_m/C/C-MV-01", - "rv64i_m/C/C-OR-01", - "rv64i_m/C/C-SD-01", - "rv64i_m/C/C-SDSP-01", - "rv64i_m/C/C-SLLI-01", - "rv64i_m/C/C-SRAI-01", - "rv64i_m/C/C-SRLI-01", - "rv64i_m/C/C-SUB-01", - "rv64i_m/C/C-SUBW-01", - "rv64i_m/C/C-SW-01", - "rv64i_m/C/C-SWSP-01", - "rv64i_m/C/C-XOR-01", - "rv64i_m/C/I-C-EBREAK-01", - "rv64i_m/C/I-C-NOP-01" + "rv64i_m/C/C-ADD-01.S", + "rv64i_m/C/C-ADDI-01.S", + "rv64i_m/C/C-ADDI16SP-01.S", + "rv64i_m/C/C-ADDI4SPN-01.S", + "rv64i_m/C/C-ADDIW-01.S", + "rv64i_m/C/C-ADDW-01.S", + "rv64i_m/C/C-AND-01.S", + "rv64i_m/C/C-ANDI-01.S", + "rv64i_m/C/C-BEQZ-01.S", + "rv64i_m/C/C-BNEZ-01.S", + "rv64i_m/C/C-J-01.S", + "rv64i_m/C/C-JALR-01.S", + "rv64i_m/C/C-JR-01.S", + "rv64i_m/C/C-LD-01.S", + "rv64i_m/C/C-LDSP-01.S", + "rv64i_m/C/C-LI-01.S", + "rv64i_m/C/C-LUI-01.S", + "rv64i_m/C/C-LW-01.S", + "rv64i_m/C/C-LWSP-01.S", + "rv64i_m/C/C-MV-01.S", + "rv64i_m/C/C-OR-01.S", + "rv64i_m/C/C-SD-01.S", + "rv64i_m/C/C-SDSP-01.S", + "rv64i_m/C/C-SLLI-01.S", + "rv64i_m/C/C-SRAI-01.S", + "rv64i_m/C/C-SRLI-01.S", + "rv64i_m/C/C-SUB-01.S", + "rv64i_m/C/C-SUBW-01.S", + "rv64i_m/C/C-SW-01.S", + "rv64i_m/C/C-SWSP-01.S", + "rv64i_m/C/C-XOR-01.S", + "rv64i_m/C/I-C-EBREAK-01.S", + "rv64i_m/C/I-C-NOP-01.S" }; string imperas64iNOc[] = { `IMPERASTEST, - "rv64i_m/I/I-MISALIGN_JMP-01" + "rv64i_m/I/I-MISALIGN_JMP-01.S" }; string imperas64i[] = '{ `IMPERASTEST, - "rv64i_m/I/I-DELAY_SLOTS-01", - "rv64i_m/I/ADD-01", - "rv64i_m/I/ADDI-01", - "rv64i_m/I/ADDIW-01", - "rv64i_m/I/ADDW-01", - "rv64i_m/I/AND-01", - "rv64i_m/I/ANDI-01", - "rv64i_m/I/AUIPC-01", - "rv64i_m/I/BEQ-01", - "rv64i_m/I/BGE-01", - "rv64i_m/I/BGEU-01", - "rv64i_m/I/BLT-01", - "rv64i_m/I/BLTU-01", - "rv64i_m/I/BNE-01", - "rv64i_m/I/I-DELAY_SLOTS-01", - "rv64i_m/I/I-EBREAK-01", - "rv64i_m/I/I-ECALL-01", - "rv64i_m/I/I-ENDIANESS-01", - "rv64i_m/I/I-IO-01", -// "rv64i_m/I/I-MISALIGN_JMP-01", - "rv64i_m/I/I-MISALIGN_LDST-01", - "rv64i_m/I/I-NOP-01", - "rv64i_m/I/I-RF_size-01", - "rv64i_m/I/I-RF_width-01", - "rv64i_m/I/I-RF_x0-01", - "rv64i_m/I/JAL-01", - "rv64i_m/I/JALR-01", - "rv64i_m/I/LB-01", - "rv64i_m/I/LBU-01", - "rv64i_m/I/LD-01", - "rv64i_m/I/LH-01", - "rv64i_m/I/LHU-01", - "rv64i_m/I/LUI-01", - "rv64i_m/I/LW-01", - "rv64i_m/I/LWU-01", - "rv64i_m/I/OR-01", - "rv64i_m/I/ORI-01", - "rv64i_m/I/SB-01", - "rv64i_m/I/SD-01", - "rv64i_m/I/SH-01", - "rv64i_m/I/SLL-01", - "rv64i_m/I/SLLI-01", - "rv64i_m/I/SLLIW-01", - "rv64i_m/I/SLLW-01", - "rv64i_m/I/SLT-01", - "rv64i_m/I/SLTI-01", - "rv64i_m/I/SLTIU-01", - "rv64i_m/I/SLTU-01", - "rv64i_m/I/SRA-01", - "rv64i_m/I/SRAI-01", - "rv64i_m/I/SRAIW-01", - "rv64i_m/I/SRAW-01", - "rv64i_m/I/SRL-01", - "rv64i_m/I/SRLI-01", - "rv64i_m/I/SRLIW-01", - "rv64i_m/I/SRLW-01", - "rv64i_m/I/SUB-01", - "rv64i_m/I/SUBW-01", - "rv64i_m/I/SW-01", - "rv64i_m/I/XOR-01", - "rv64i_m/I/XORI-01" + "rv64i_m/I/I-DELAY_SLOTS-01.S", + "rv64i_m/I/ADD-01.S", + "rv64i_m/I/ADDI-01.S", + "rv64i_m/I/ADDIW-01.S", + "rv64i_m/I/ADDW-01.S", + "rv64i_m/I/AND-01.S", + "rv64i_m/I/ANDI-01.S", + "rv64i_m/I/AUIPC-01.S", + "rv64i_m/I/BEQ-01.S", + "rv64i_m/I/BGE-01.S", + "rv64i_m/I/BGEU-01.S", + "rv64i_m/I/BLT-01.S", + "rv64i_m/I/BLTU-01.S", + "rv64i_m/I/BNE-01.S", + "rv64i_m/I/I-DELAY_SLOTS-01.S", + "rv64i_m/I/I-EBREAK-01.S", + "rv64i_m/I/I-ECALL-01.S", + "rv64i_m/I/I-ENDIANESS-01.S", + "rv64i_m/I/I-IO-01.S", +// "rv64i_m/I/I-MISALIGN_JMP-01.S", + "rv64i_m/I/I-MISALIGN_LDST-01.S", + "rv64i_m/I/I-NOP-01.S", + "rv64i_m/I/I-RF_size-01.S", + "rv64i_m/I/I-RF_width-01.S", + "rv64i_m/I/I-RF_x0-01.S", + "rv64i_m/I/JAL-01.S", + "rv64i_m/I/JALR-01.S", + "rv64i_m/I/LB-01.S", + "rv64i_m/I/LBU-01.S", + "rv64i_m/I/LD-01.S", + "rv64i_m/I/LH-01.S", + "rv64i_m/I/LHU-01.S", + "rv64i_m/I/LUI-01.S", + "rv64i_m/I/LW-01.S", + "rv64i_m/I/LWU-01.S", + "rv64i_m/I/OR-01.S", + "rv64i_m/I/ORI-01.S", + "rv64i_m/I/SB-01.S", + "rv64i_m/I/SD-01.S", + "rv64i_m/I/SH-01.S", + "rv64i_m/I/SLL-01.S", + "rv64i_m/I/SLLI-01.S", + "rv64i_m/I/SLLIW-01.S", + "rv64i_m/I/SLLW-01.S", + "rv64i_m/I/SLT-01.S", + "rv64i_m/I/SLTI-01.S", + "rv64i_m/I/SLTIU-01.S", + "rv64i_m/I/SLTU-01.S", + "rv64i_m/I/SRA-01.S", + "rv64i_m/I/SRAI-01.S", + "rv64i_m/I/SRAIW-01.S", + "rv64i_m/I/SRAW-01.S", + "rv64i_m/I/SRL-01.S", + "rv64i_m/I/SRLI-01.S", + "rv64i_m/I/SRLIW-01.S", + "rv64i_m/I/SRLW-01.S", + "rv64i_m/I/SUB-01.S", + "rv64i_m/I/SUBW-01.S", + "rv64i_m/I/SW-01.S", + "rv64i_m/I/XOR-01.S", + "rv64i_m/I/XORI-01.S" }; string imperas32m[] = '{ `IMPERASTEST, - "rv32i_m/M/DIV-01", - "rv32i_m/M/DIVU-01", - "rv32i_m/M/MUL-01", - "rv32i_m/M/MULH-01", - "rv32i_m/M/MULHSU-01", - "rv32i_m/M/MULHU-01", - "rv32i_m/M/REM-01", - "rv32i_m/M/REMU-01" + "rv32i_m/M/DIV-01.S", + "rv32i_m/M/DIVU-01.S", + "rv32i_m/M/MUL-01.S", + "rv32i_m/M/MULH-01.S", + "rv32i_m/M/MULHSU-01.S", + "rv32i_m/M/MULHU-01.S", + "rv32i_m/M/REM-01.S", + "rv32i_m/M/REMU-01.S" }; string imperas32c[] = '{ `IMPERASTEST, - "rv32i_m/C/C-ADD-01", - "rv32i_m/C/C-ADDI-01", - "rv32i_m/C/C-ADDI16SP-01", - "rv32i_m/C/C-ADDI4SPN-01", - "rv32i_m/C/C-AND-01", - "rv32i_m/C/C-ANDI-01", - "rv32i_m/C/C-BEQZ-01", - "rv32i_m/C/C-BNEZ-01", - "rv32i_m/C/C-J-01", - "rv32i_m/C/C-JAL-01", - "rv32i_m/C/C-JALR-01", - "rv32i_m/C/C-JR-01", - "rv32i_m/C/C-LI-01", - "rv32i_m/C/C-LUI-01", - "rv32i_m/C/C-LW-01", - "rv32i_m/C/C-LWSP-01", - "rv32i_m/C/C-MV-01", - "rv32i_m/C/C-OR-01", - "rv32i_m/C/C-SLLI-01", - "rv32i_m/C/C-SRAI-01", - "rv32i_m/C/C-SRLI-01", - "rv32i_m/C/C-SUB-01", - "rv32i_m/C/C-SW-01", - "rv32i_m/C/C-SWSP-01", - "rv32i_m/C/C-XOR-01", - "rv32i_m/C/I-C-EBREAK-01", - "rv32i_m/C/I-C-NOP-01" + "rv32i_m/C/C-ADD-01.S", + "rv32i_m/C/C-ADDI-01.S", + "rv32i_m/C/C-ADDI16SP-01.S", + "rv32i_m/C/C-ADDI4SPN-01.S", + "rv32i_m/C/C-AND-01.S", + "rv32i_m/C/C-ANDI-01.S", + "rv32i_m/C/C-BEQZ-01.S", + "rv32i_m/C/C-BNEZ-01.S", + "rv32i_m/C/C-J-01.S", + "rv32i_m/C/C-JAL-01.S", + "rv32i_m/C/C-JALR-01.S", + "rv32i_m/C/C-JR-01.S", + "rv32i_m/C/C-LI-01.S", + "rv32i_m/C/C-LUI-01.S", + "rv32i_m/C/C-LW-01.S", + "rv32i_m/C/C-LWSP-01.S", + "rv32i_m/C/C-MV-01.S", + "rv32i_m/C/C-OR-01.S", + "rv32i_m/C/C-SLLI-01.S", + "rv32i_m/C/C-SRAI-01.S", + "rv32i_m/C/C-SRLI-01.S", + "rv32i_m/C/C-SUB-01.S", + "rv32i_m/C/C-SW-01.S", + "rv32i_m/C/C-SWSP-01.S", + "rv32i_m/C/C-XOR-01.S", + "rv32i_m/C/I-C-EBREAK-01.S", + "rv32i_m/C/I-C-NOP-01.S" }; string imperas32iNOc[] = { `IMPERASTEST, - "rv32i_m/I/I-MISALIGN_JMP-01" + "rv32i_m/I/I-MISALIGN_JMP-01.S" }; string imperas32i[] = { `IMPERASTEST, - "rv32i_m/I/ADD-01", - "rv32i_m/I/ADDI-01", - "rv32i_m/I/AND-01", - "rv32i_m/I/ANDI-01", - "rv32i_m/I/AUIPC-01", - "rv32i_m/I/BEQ-01", - "rv32i_m/I/BGE-01", - "rv32i_m/I/BGEU-01", - "rv32i_m/I/BLT-01", - "rv32i_m/I/BLTU-01", - "rv32i_m/I/BNE-01", - "rv32i_m/I/I-DELAY_SLOTS-01", - "rv32i_m/I/I-EBREAK-01", - "rv32i_m/I/I-ECALL-01", - "rv32i_m/I/I-ENDIANESS-01", - "rv32i_m/I/I-IO-01", -// "rv32i_m/I/I-MISALIGN_JMP-01", - "rv32i_m/I/I-MISALIGN_LDST-01", - "rv32i_m/I/I-NOP-01", - "rv32i_m/I/I-RF_size-01", - "rv32i_m/I/I-RF_width-01", - "rv32i_m/I/I-RF_x0-01", - "rv32i_m/I/JAL-01", - "rv32i_m/I/JALR-01", - "rv32i_m/I/LB-01", - "rv32i_m/I/LBU-01", - "rv32i_m/I/LH-01", - "rv32i_m/I/LHU-01", - "rv32i_m/I/LUI-01", - "rv32i_m/I/LW-01", - "rv32i_m/I/OR-01", - "rv32i_m/I/ORI-01", - "rv32i_m/I/SB-01", - "rv32i_m/I/SH-01", - "rv32i_m/I/SLL-01", - "rv32i_m/I/SLLI-01", - "rv32i_m/I/SLT-01", - "rv32i_m/I/SLTI-01", - "rv32i_m/I/SLTIU-01", - "rv32i_m/I/SLTU-01", - "rv32i_m/I/SRA-01", - "rv32i_m/I/SRAI-01", - "rv32i_m/I/SRL-01", - "rv32i_m/I/SRLI-01", - "rv32i_m/I/SUB-01", - "rv32i_m/I/SW-01", - "rv32i_m/I/XOR-01", - "rv32i_m/I/XORI-01" + "rv32i_m/I/ADD-01.S", + "rv32i_m/I/ADDI-01.S", + "rv32i_m/I/AND-01.S", + "rv32i_m/I/ANDI-01.S", + "rv32i_m/I/AUIPC-01.S", + "rv32i_m/I/BEQ-01.S", + "rv32i_m/I/BGE-01.S", + "rv32i_m/I/BGEU-01.S", + "rv32i_m/I/BLT-01.S", + "rv32i_m/I/BLTU-01.S", + "rv32i_m/I/BNE-01.S", + "rv32i_m/I/I-DELAY_SLOTS-01.S", + "rv32i_m/I/I-EBREAK-01.S", + "rv32i_m/I/I-ECALL-01.S", + "rv32i_m/I/I-ENDIANESS-01.S", + "rv32i_m/I/I-IO-01.S", +// "rv32i_m/I/I-MISALIGN_JMP-01.S", + "rv32i_m/I/I-MISALIGN_LDST-01.S", + "rv32i_m/I/I-NOP-01.S", + "rv32i_m/I/I-RF_size-01.S", + "rv32i_m/I/I-RF_width-01.S", + "rv32i_m/I/I-RF_x0-01.S", + "rv32i_m/I/JAL-01.S", + "rv32i_m/I/JALR-01.S", + "rv32i_m/I/LB-01.S", + "rv32i_m/I/LBU-01.S", + "rv32i_m/I/LH-01.S", + "rv32i_m/I/LHU-01.S", + "rv32i_m/I/LUI-01.S", + "rv32i_m/I/LW-01.S", + "rv32i_m/I/OR-01.S", + "rv32i_m/I/ORI-01.S", + "rv32i_m/I/SB-01.S", + "rv32i_m/I/SH-01.S", + "rv32i_m/I/SLL-01.S", + "rv32i_m/I/SLLI-01.S", + "rv32i_m/I/SLT-01.S", + "rv32i_m/I/SLTI-01.S", + "rv32i_m/I/SLTIU-01.S", + "rv32i_m/I/SLTU-01.S", + "rv32i_m/I/SRA-01.S", + "rv32i_m/I/SRAI-01.S", + "rv32i_m/I/SRL-01.S", + "rv32i_m/I/SRLI-01.S", + "rv32i_m/I/SUB-01.S", + "rv32i_m/I/SW-01.S", + "rv32i_m/I/XOR-01.S", + "rv32i_m/I/XORI-01.S" }; @@ -1326,6 +1326,53 @@ string imperas32f[] = '{ "rv64i_m/D/src/fssub.d_b8-01.S" }; +string arch64b[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/andn-01.S", + "rv64i_m/B/src/bclr-01.S", + "rv64i_m/B/src/bclri-01.S", + "rv64i_m/B/src/bext-01.S", + "rv64i_m/B/src/bexti-01.S", + "rv64i_m/B/src/binv-01.S", + "rv64i_m/B/src/binvi-01.S", + "rv64i_m/B/src/bset-01.S", + "rv64i_m/B/src/bseti-01.S", + "rv64i_m/B/src/clmul-01.S", + "rv64i_m/B/src/clmulh-01.S", + "rv64i_m/B/src/clmulr-01.S", + "rv64i_m/B/src/clz-01.S", + "rv64i_m/B/src/clzw-01.S", + "rv64i_m/B/src/cpop-01.S", + "rv64i_m/B/src/cpopw-01.S", + "rv64i_m/B/src/ctz-01.S", + "rv64i_m/B/src/ctzw-01.S", + "rv64i_m/B/src/max-01.S", + "rv64i_m/B/src/maxu-01.S", + "rv64i_m/B/src/min-01.S", + "rv64i_m/B/src/minu-01.S", + "rv64i_m/B/src/orcb_64-01.S", + "rv64i_m/B/src/orn-01.S", + "rv64i_m/B/src/rev8-01.S", + "rv64i_m/B/src/rol-01.S", + "rv64i_m/B/src/rolw-01.S", + "rv64i_m/B/src/ror-01.S", + "rv64i_m/B/src/rori-01.S", + "rv64i_m/B/src/roriw-01.S", + "rv64i_m/B/src/rorw-01.S", + "rv64i_m/B/src/sext.b-01.S", + "rv64i_m/B/src/sext.h-01.S", + "rv64i_m/B/src/sh1add-01.S", + "rv64i_m/B/src/sh1add.uw-01.S", + "rv64i_m/B/src/sh2add-01.S", + "rv64i_m/B/src/sh2add.uw-01.S", + "rv64i_m/B/src/sh3add-01.S", + "rv64i_m/B/src/sh3add.uw-01.S", + "rv64i_m/B/src/slli.uw-01.S", + "rv64i_m/B/src/xnor-01.S", + "rv64i_m/B/src/zext.h-01.S", + "rv64i_m/B/src/zext.h_64-01.S" +}; string arch32priv[] = '{ `RISCVARCHTEST, "rv32i_m/privilege/src/ebreak.S", diff --git a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py new file mode 100644 index 000000000..c9681aee1 --- /dev/null +++ b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py @@ -0,0 +1,13 @@ +import os + +os.chdir("/home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src") + +filenames = [] + +for testname in os.listdir(): + print( +f"""cd /home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/kmacsai-goren/cvw/tests/riscof/sail_cSim/env/link.ld -I /home/kmacsai-goren/cvw/tests/riscof/sail_cSim/env/ -I /home/kmacsai-goren/cvw/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 /home/kmacsai-goren/cvw/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature=/home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; +riscv64-unknown-elf-elf2hex --bit-width 64 --input /home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output /home/kmacsai-goren/cvw/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile +extractFunctionRadix.sh /home/kmacsai-goren/cvw/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump +""") + diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index 8037ad6f6..e6bfc72ef 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -1,7 +1,7 @@ hart_ids: [0] hart0: - ISA: RV64IMAFDCSUZicsr_Zifencei -# ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs +# ISA: RV64IMAFDCSUZicsr_Zifencei + ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] From f95038551fc31f62304525f3aa48f63ceb60cd73 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 10 Feb 2023 10:37:06 -0800 Subject: [PATCH 027/231] fixed small errors to get regression to run with bit manip supported. --- src/ieu/bmu/clmul.sv | 19 ++++++++----------- src/ieu/bmu/popcnt.sv | 10 +++++++--- src/ieu/bmu/zbs.sv | 2 +- 3 files changed, 16 insertions(+), 15 deletions(-) diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 5557283f9..a83d014a7 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -34,20 +34,17 @@ module clmul #(parameter WIDTH=32) ( output logic [WIDTH-1:0] ClmulResult); // ZBS result logic [WIDTH-1:0] pp [WIDTH-1:0]; //partial AND products + // Note: only generates the bottom WIDTH bits of the carryless multiply. + // To get the high bits or the reversed bits, the inputs can be shifted and reversed + // as they are in zbc where this is instantiated - genvar i,j; - for (i=1; i Date: Sat, 11 Feb 2023 00:30:56 +0000 Subject: [PATCH 028/231] changed python file to use WALLY env variable --- tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py index c9681aee1..78879962a 100644 --- a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py +++ b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py @@ -1,13 +1,15 @@ +#Kip Macsai-Goren and Kevin Kim import os -os.chdir("/home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src") +WALLY = os.getenv("WALLY") +os.chdir(f"{WALLY}/tests/riscof/riscof_work/rv64i_m/B/src") filenames = [] for testname in os.listdir(): print( -f"""cd /home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T /home/kmacsai-goren/cvw/tests/riscof/sail_cSim/env/link.ld -I /home/kmacsai-goren/cvw/tests/riscof/sail_cSim/env/ -I /home/kmacsai-goren/cvw/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 /home/kmacsai-goren/cvw/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature=/home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; -riscv64-unknown-elf-elf2hex --bit-width 64 --input /home/kmacsai-goren/cvw/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output /home/kmacsai-goren/cvw/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile -extractFunctionRadix.sh /home/kmacsai-goren/cvw/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump +f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; +riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile +extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump """) From 5fed4c2c8721fd492b770681fb54d24a3d9c40d6 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 11 Feb 2023 11:08:11 -0800 Subject: [PATCH 029/231] updated python script to generate bash file --- tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py index 78879962a..e7ec07d32 100644 --- a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py +++ b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py @@ -1,15 +1,19 @@ #Kip Macsai-Goren and Kevin Kim +#Purpose is to manually make the B extension tests import os +f = open("genBScript.sh", "w") WALLY = os.getenv("WALLY") os.chdir(f"{WALLY}/tests/riscof/riscof_work/rv64i_m/B/src") filenames = [] +lines = "" for testname in os.listdir(): - print( -f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; + lines = lines + f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump -""") +""" +f.write(lines) +f.close() From 4ca27d1475ad24423974cca65f8c3a0f0a26adfe Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 11 Feb 2023 12:14:00 -0800 Subject: [PATCH 030/231] edited rv64i convig to support bit manipulation --- config/rv64i/wally-config.vh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh index 90d7b4045..b865da263 100644 --- a/config/rv64i/wally-config.vh +++ b/config/rv64i/wally-config.vh @@ -145,10 +145,10 @@ `define DIVCOPIES 32'h4 // bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 +`define ZBA_SUPPORTED 1 +`define ZBB_SUPPORTED 1 +`define ZBC_SUPPORTED 1 +`define ZBS_SUPPORTED 1 // Memory synthesis configuration `define USE_SRAM 0 From 2fefc3019e7033ef4be1a4434c92ccc42739cdf5 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 11 Feb 2023 19:16:13 -0800 Subject: [PATCH 031/231] clmul passes lint --- src/ieu/bmu/clmul.sv | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index a83d014a7..3b7daadbd 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -37,14 +37,26 @@ module clmul #(parameter WIDTH=32) ( // Note: only generates the bottom WIDTH bits of the carryless multiply. // To get the high bits or the reversed bits, the inputs can be shifted and reversed // as they are in zbc where this is instantiated - + /* genvar i; for (i=0; i Date: Sat, 11 Feb 2023 19:19:38 -0800 Subject: [PATCH 032/231] popcnt passes lint --- src/ieu/bmu/popcnt.sv | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 57f8c9e39..456e07747 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -31,12 +31,18 @@ module popcnt #(parameter WIDTH = 32) ( logic [$clog2(WIDTH):0] sum; - always_comb begin + /*always_comb begin sum = 0; for (int i=0;i Date: Sat, 11 Feb 2023 20:22:42 -0800 Subject: [PATCH 033/231] fixed lints in cnt --- src/ieu/bmu/cnt.sv | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index b0c44e06a..dd72cd5de 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -48,25 +48,26 @@ module cnt #(parameter WIDTH = 32) ( //NOTE: signal widths can be decreased always_comb begin //clz input select mux - case({B,W64}) - 5'b00000_0: lzcA = A; //clz - 5'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw - 5'b00001_0: lzcA = revA; //ctz - 5'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw + case({B[4:0],W64}) + 6'b00000_0: lzcA = A; //clz + 6'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw + 6'b00001_0: lzcA = revA; //ctz + 6'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw endcase //cpop select mux - case ({B,W64}) - 5'b00010_0: popcntA = A; - 5'b00010_1: popcntA = {{32{1'b0}}, A[31:0]}; + case ({B[4:0],W64}) + 6'b00010_0: popcntA = A; + 6'b00010_1: popcntA = {{32{1'b0}}, A[31:0]}; endcase end end else begin + //rv32 assign popcntA = A; always_comb begin //clz input slect mux - case(B) + case(B[4:0]) 5'b00000: lzcA = A; 5'b00001: lzcA = revA; endcase From 016634d842d6a6f742485a49a84c22c908ea26aa Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 11 Feb 2023 20:25:34 -0800 Subject: [PATCH 034/231] fixed byte unit lints --- src/ieu/bmu/byte.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index 17ab652f2..6a076b7dc 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -38,7 +38,7 @@ module byteUnit #(parameter WIDTH=32) ( for (i=0;i Date: Sat, 11 Feb 2023 20:41:52 -0800 Subject: [PATCH 035/231] zbb, zbs, cnt lint fixes --- src/ieu/bmu/cnt.sv | 3 +++ src/ieu/bmu/zbb.sv | 4 +--- src/ieu/bmu/zbs.sv | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index dd72cd5de..430d2d382 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -53,12 +53,14 @@ module cnt #(parameter WIDTH = 32) ( 6'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw 6'b00001_0: lzcA = revA; //ctz 6'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw + default: lzcA = A; endcase //cpop select mux case ({B[4:0],W64}) 6'b00010_0: popcntA = A; 6'b00010_1: popcntA = {{32{1'b0}}, A[31:0]}; + default: popcntA = A; endcase end end @@ -70,6 +72,7 @@ module cnt #(parameter WIDTH = 32) ( case(B[4:0]) 5'b00000: lzcA = A; 5'b00001: lzcA = revA; + default: lzcA = A; endcase end end diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 98996f3b8..e469fcef7 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -58,15 +58,13 @@ module zbb #(parameter WIDTH=32) ( //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin - case ({Funct7, Funct3, B}) + case ({Funct7, Funct3, B[4:0]}) 15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0110000_001_00000: ZBBResult = czResult; 15'b0110000_001_00010: ZBBResult = cpopResult; 15'b0110000_001_00001: ZBBResult = czResult; - 15'b0110101_101_11000: ZBBResult = Rev8Result; - 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0000100_100_00000: ZBBResult = zexthResult; 15'b0110000_001_00100: ZBBResult = sextbResult; 15'b0110000_001_00101: ZBBResult = sexthResult; diff --git a/src/ieu/bmu/zbs.sv b/src/ieu/bmu/zbs.sv index 740c684ba..214d6e2c0 100644 --- a/src/ieu/bmu/zbs.sv +++ b/src/ieu/bmu/zbs.sv @@ -43,7 +43,7 @@ module zbs #(parameter WIDTH=32) ( assign InvResult = A ^ BMask; assign ClrResult = A & ~BMask; assign SetResult = A | BMask; - assign ExtResult = |(A & BMask); + assign ExtResult = {{(WIDTH-1){1'b0}},{|(A & BMask)}}; always_comb begin casez ({Funct7, Funct3}) From 67db085b24c9e9abb1dcd7be73cbc42dbbd6cbaa Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 11 Feb 2023 21:13:10 -0800 Subject: [PATCH 036/231] lint fixes --- src/ieu/alu.sv | 24 ++++++++++-------------- src/ieu/bmu/popcnt.sv | 12 +++--------- src/ieu/bmu/zbb.sv | 7 ++++--- 3 files changed, 17 insertions(+), 26 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 15a19f558..97cda8729 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -57,14 +57,14 @@ module alu #(parameter WIDTH=32) ( // Addition if (`ZBB_SUPPORTED) always_comb begin - case({Funct7, Funct3}) - 10'b0010000_010: CondShiftA = {A[WIDTH-1:1], {1'b0}}; //sh1add - 10'b0010000_100: CondShiftA = {A[WIDTH-1:2], {2'b00}}; //sh2add - 10'b0010000_110: CondShiftA = {A[WIDTH-1:3], {3'b000}}; //sh3add - 10'b0000100_000: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw - 10'b0010000_010: CondShiftA = {{31{1'b0}},A[31:0], {1'b0}}; //sh1add.uw - 10'b0010000_100: CondShiftA = {{30{1'b0}},A[31:0], {2'b0}}; //sh2add.uw - 10'b0010000_110: CondShiftA = {{29{1'b0}},A[31:0], {3'b0}}; //sh3add.uw + case({Funct7, Funct3, W64}) + 11'b0010000_010_0: CondShiftA = {A[WIDTH-1:1], {1'b0}}; //sh1add + 11'b0010000_100_0: CondShiftA = {A[WIDTH-1:2], {2'b00}}; //sh2add + 11'b0010000_110_0: CondShiftA = {A[WIDTH-1:3], {3'b000}}; //sh3add + 11'b0000100_000_1: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw + 11'b0010000_010_1: CondShiftA = {{31{1'b0}},A[31:0], {1'b0}}; //sh1add.uw + 11'b0010000_100_1: CondShiftA = {{30{1'b0}},A[31:0], {2'b0}}; //sh2add.uw + 11'b0010000_110_1: CondShiftA = {{29{1'b0}},A[31:0], {3'b0}}; //sh3add.uw default: CondShiftA = A; endcase @@ -76,13 +76,9 @@ module alu #(parameter WIDTH=32) ( endcase casez ({Funct7, Funct3}) - 10'b0110000_101: Rotate = 1'b1; 10'b011000?_101: Rotate = 1'b1; 10'b000010?_001: Rotate = 1'b0; 10'b0110000_001: Rotate = 1'b1; - 10'b0110000_101: Rotate = 1'b1; - 10'b0110000_001: Rotate = 1'b1; - 10'b0110000_101: Rotate = 1'b1; default: Rotate = 1'b0; endcase end @@ -126,12 +122,12 @@ module alu #(parameter WIDTH=32) ( endcase if (`ZBS_SUPPORTED) - zbs zbs(.A, .B, .Funct7, .Funct3, .ZBSResult); + zbs #(WIDTH) zbs(.A, .B, .Funct7, .Funct3, .ZBSResult); else assign ZBSResult = 0; if (`ZBB_SUPPORTED) - zbb zbb(.A, .B, .Funct3, .Funct7, .W64, .ZBBResult); + zbb #(WIDTH) zbb(.A, .B, .Funct3, .Funct7, .W64, .ZBBResult); else assign ZBBResult = 0; // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 456e07747..c82476a61 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -31,20 +31,14 @@ module popcnt #(parameter WIDTH = 32) ( logic [$clog2(WIDTH):0] sum; - /*always_comb begin + always_comb begin sum = 0; for (int i=0;i Date: Sat, 11 Feb 2023 21:22:33 -0800 Subject: [PATCH 037/231] simulation runs-- clmul doesn't pass lint with xor tree --- src/ieu/bmu/clmul.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 3b7daadbd..f1917f550 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -47,14 +47,16 @@ module clmul #(parameter WIDTH=32) ( */ genvar i,j; for (i=1; i Date: Mon, 13 Feb 2023 13:49:35 -0800 Subject: [PATCH 038/231] alu add.uw needs w64 to be false --- src/ieu/alu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 97cda8729..dd7b1bb10 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -61,7 +61,7 @@ module alu #(parameter WIDTH=32) ( 11'b0010000_010_0: CondShiftA = {A[WIDTH-1:1], {1'b0}}; //sh1add 11'b0010000_100_0: CondShiftA = {A[WIDTH-1:2], {2'b00}}; //sh2add 11'b0010000_110_0: CondShiftA = {A[WIDTH-1:3], {3'b000}}; //sh3add - 11'b0000100_000_1: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw + 11'b0000100_000_0: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw 11'b0010000_010_1: CondShiftA = {{31{1'b0}},A[31:0], {1'b0}}; //sh1add.uw 11'b0010000_100_1: CondShiftA = {{30{1'b0}},A[31:0], {2'b0}}; //sh2add.uw 11'b0010000_110_1: CondShiftA = {{29{1'b0}},A[31:0], {3'b0}}; //sh3add.uw From c9e6b9aeef67bb14adb6af44fb606b717e830885 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 13 Feb 2023 13:49:46 -0800 Subject: [PATCH 039/231] edited controller so that add.uw passes tests --- src/ieu/controller.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index c4afa86c1..4d8ba0c65 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -161,7 +161,10 @@ module controller( else if (Funct7D == 7'b0000001 & `M_SUPPORTED & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide else - ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction + if (Funct7D == 7'b0000100 & `ZBA_SUPPORTED) + ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // adduw + else + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction 7'b1100011: ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches 7'b1100111: ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr 7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal From ed6a0466ad07a5334244eec90c55fd2d8a50da62 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 13 Feb 2023 14:00:06 -0800 Subject: [PATCH 040/231] ALU configurability changes -stuff that was ZBA supported was in ZBB so I changed that --- src/ieu/alu.sv | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index dd7b1bb10..49ab54046 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -55,7 +55,7 @@ module alu #(parameter WIDTH=32) ( // Addition - if (`ZBB_SUPPORTED) + if (`ZBA_SUPPORTED) always_comb begin case({Funct7, Funct3, W64}) 11'b0010000_010_0: CondShiftA = {A[WIDTH-1:1], {1'b0}}; //sh1add @@ -67,7 +67,12 @@ module alu #(parameter WIDTH=32) ( 11'b0010000_110_1: CondShiftA = {{29{1'b0}},A[31:0], {3'b0}}; //sh3add.uw default: CondShiftA = A; endcase + else begin + assign CondShiftA = A; + end + if (`ZBB_SUPPORTED) + always_comb begin case ({Funct7,Funct3}) 10'b0100000_111: InvB = 1'b1; //andn 10'b0100000_110: InvB = 1'b1; //orn @@ -83,8 +88,8 @@ module alu #(parameter WIDTH=32) ( endcase end else begin - assign CondShiftA = A; - assign InvB = 1'b0; + InvB = 1'b0; + Rotate = 1'b0; end assign CondInvB = (SubArith | InvB) ? ~B : B; From 02a7dc45f0021d68c5adbf2f1aacd773aa557d44 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 13 Feb 2023 14:01:51 -0800 Subject: [PATCH 041/231] ALU lint fixes --- src/ieu/alu.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 49ab54046..911fc0873 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -67,6 +67,7 @@ module alu #(parameter WIDTH=32) ( 11'b0010000_110_1: CondShiftA = {{29{1'b0}},A[31:0], {3'b0}}; //sh3add.uw default: CondShiftA = A; endcase + end else begin assign CondShiftA = A; end @@ -88,8 +89,8 @@ module alu #(parameter WIDTH=32) ( endcase end else begin - InvB = 1'b0; - Rotate = 1'b0; + assign InvB = 1'b0; + assign Rotate = 1'b0; end assign CondInvB = (SubArith | InvB) ? ~B : B; From 2679f06a00bf6ae98ba70c278ce6ab4dbad1cddf Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 13 Feb 2023 16:36:17 -0800 Subject: [PATCH 042/231] Shadd instructions pass tests --- src/ieu/alu.sv | 21 +++++++++++++-------- src/ieu/controller.sv | 30 ++++++++++++++++++++---------- 2 files changed, 33 insertions(+), 18 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 911fc0873..7e06ee6e9 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -49,27 +49,32 @@ module alu #(parameter WIDTH=32) ( logic Asign, Bsign; // Sign bits of A, B logic InvB; // Is Inverted Operand Instruction (ZBB) logic Rotate; // Is rotate operation + logic ZbaAdd; // Is ZBA Add Operation // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; + + // Addition if (`ZBA_SUPPORTED) always_comb begin + ZbaAdd = (Funct7 == 7'b0010000 | Funct7 == 7'b0000100); case({Funct7, Funct3, W64}) - 11'b0010000_010_0: CondShiftA = {A[WIDTH-1:1], {1'b0}}; //sh1add - 11'b0010000_100_0: CondShiftA = {A[WIDTH-1:2], {2'b00}}; //sh2add - 11'b0010000_110_0: CondShiftA = {A[WIDTH-1:3], {3'b000}}; //sh3add - 11'b0000100_000_0: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw + 11'b0010000_010_0: CondShiftA = {A[WIDTH-2:0], {1'b0}}; //sh1add + 11'b0010000_100_0: CondShiftA = {A[WIDTH-3:0], {2'b00}}; //sh2add + 11'b0010000_110_0: CondShiftA = {A[WIDTH-4:0], {3'b000}}; //sh3add + 11'b0000100_000_1: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw 11'b0010000_010_1: CondShiftA = {{31{1'b0}},A[31:0], {1'b0}}; //sh1add.uw - 11'b0010000_100_1: CondShiftA = {{30{1'b0}},A[31:0], {2'b0}}; //sh2add.uw - 11'b0010000_110_1: CondShiftA = {{29{1'b0}},A[31:0], {3'b0}}; //sh3add.uw + 11'b0010000_100_1: CondShiftA = {{30{1'b0}},A[31:0], {2'b00}}; //sh2add.uw + 11'b0010000_110_1: CondShiftA = {{29{1'b0}},A[31:0], {3'b000}}; //sh3add.uw default: CondShiftA = A; endcase end else begin assign CondShiftA = A; + assign ZbaAdd = 0; end if (`ZBB_SUPPORTED) @@ -116,7 +121,7 @@ module alu #(parameter WIDTH=32) ( // Select appropriate ALU Result always_comb - if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) + if (~ALUOp | ZbaAdd) FullResult = Sum; // Always add for ALUOp = 0 (address generation) and ZBA else casez (Funct3) // Otherwise check Funct3 3'b000: FullResult = Sum; // add or sub 3'b?01: FullResult = Shift; // sll, sra, or srl @@ -137,7 +142,7 @@ module alu #(parameter WIDTH=32) ( else assign ZBBResult = 0; // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (WIDTH == 64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + if (WIDTH == 64) assign Result = (W64 & ~ZbaAdd) ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; else assign Result = FullResult; endmodule diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 4d8ba0c65..1188fe0a6 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -149,7 +149,7 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (Funct7D == 7'b0010000 & `ZBA_SUPPORTED)) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & `M_SUPPORTED) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide @@ -161,8 +161,8 @@ module controller( else if (Funct7D == 7'b0000001 & `M_SUPPORTED & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide else - if (Funct7D == 7'b0000100 & `ZBA_SUPPORTED) - ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // adduw + if ((Funct7D == 7'b0000100 | Funct7D == 7'b0010000) & `ZBA_SUPPORTED) + ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // adduw, sh1adduw, sh2adduw, sh3adduw else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction 7'b1100011: ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches @@ -193,13 +193,23 @@ module controller( assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001); assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i - // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra - assign sltD = (Funct3D == 3'b010); - assign sltuD = (Funct3D == 3'b011); - assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi - assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu - assign ALUControlD = {W64D, SubArithD, ALUOpD}; + if (`ZBA_SUPPORTED) begin + // ALU Decoding is more comprehensive when ZBA is supported + assign sltD = (Funct3D == 3'b010 & OpD == 7'b0010011); + assign sltuD = (Funct3D == 3'b011 & OpD == 7'b0010011); + assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi + assign sraD = (Funct3D == 3'b101 & Funct7D[5]); + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu + assign ALUControlD = {W64D, SubArithD, ALUOpD}; + end else begin + // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra + assign sltD = (Funct3D == 3'b010); + assign sltuD = (Funct3D == 3'b011); + assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi + assign sraD = (Funct3D == 3'b101 & Funct7D[5]); + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu + assign ALUControlD = {W64D, SubArithD, ALUOpD}; + end // Fences // Ordinary fence is presently a nop From 1364ac2a14a061807ce37d91d3a64df953ca64da Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 13 Feb 2023 16:57:05 -0800 Subject: [PATCH 043/231] controller handles bclr --- src/ieu/controller.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 1188fe0a6..c6879ffd9 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -149,7 +149,7 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (Funct7D == 7'b0010000 & `ZBA_SUPPORTED)) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (Funct7D == 7'b0010000 & `ZBA_SUPPORTED) | (Funct7D == 7'b0100100 & `ZBS_SUPPORTED)) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & `M_SUPPORTED) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide From bcea347370265b77793de43c2a2770a3a9a6c38e Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 13 Feb 2023 17:38:00 -0800 Subject: [PATCH 044/231] added ALU result select mux for B instructions --- src/ieu/alu.sv | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 7e06ee6e9..7b381a0fb 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -40,7 +40,7 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting or inverted operand instruction in ZBB, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. logic [WIDTH-1:0] ZBBResult, ZBSResult; - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult, CondShiftA; // Intermediate results + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult, CondShiftA, ALUResult; // Intermediate results logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction @@ -142,7 +142,21 @@ module alu #(parameter WIDTH=32) ( else assign ZBBResult = 0; // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (WIDTH == 64) assign Result = (W64 & ~ZbaAdd) ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; - else assign Result = FullResult; + if (WIDTH == 64) assign ALUResult = (W64 & ~ZbaAdd) ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + else assign ALUResult = FullResult; + + if (`ZBB_SUPPORTED | `ZBA_SUPPORTED | `ZBS_SUPPORTED | `ZBC_SUPPORTED) begin + always_comb + casez({Funct7}) + 7'b010010?: Result = ZBSResult; + 7'b001010?: Result = ZBSResult; + default: Result = ALUResult; + endcase + end else begin + assign Result = ALUResult; + end + + + endmodule From 4fed8d9196684fbd161cf1bbe8773c190bbf50ff Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 14 Feb 2023 10:40:29 -0800 Subject: [PATCH 045/231] added critical rsync command to python script and builds I-ext tests -rsync copies the stuff from riscof_work to work/riscv-arch-test - --- tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py | 21 ++++++++++++++++++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py index e7ec07d32..4a728a476 100644 --- a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py +++ b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py @@ -6,14 +6,29 @@ f = open("genBScript.sh", "w") WALLY = os.getenv("WALLY") os.chdir(f"{WALLY}/tests/riscof/riscof_work/rv64i_m/B/src") -filenames = [] lines = "" +#BUILDS B TESTS for testname in os.listdir(): lines = lines + f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; -riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile -extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump +rsync -a {WALLY}/tests/riscof/riscof_work/rv64i_m/ {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/ || echo "error suppressed"; +riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile; +extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump; """ + +os.chdir(f"{WALLY}/tests/riscof/riscof_work/rv64i_m/I/src") + +#BUILDS I TESTS +for testname in os.listdir(): + lines = lines + f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/I/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/I/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; +rsync -a {WALLY}/tests/riscof/riscof_work/rv64i_m/ {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/ || echo "error suppressed"; +riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/I/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/{testname}/ref/ref.elf.memfile; +extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/{testname}/ref/ref.elf.objdump; +""" + + + + f.write(lines) f.close() From 1a209aac21b0028bf7c3f71e8ad0db7e1f129bfe Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 14 Feb 2023 13:06:31 -0800 Subject: [PATCH 046/231] reverted back to I tests working --- src/ieu/alu.sv | 6 ++-- src/ieu/bmu/clmul.sv.bak | 64 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 67 insertions(+), 3 deletions(-) create mode 100644 src/ieu/bmu/clmul.sv.bak diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 97cda8729..daf60f23e 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -69,9 +69,9 @@ module alu #(parameter WIDTH=32) ( endcase case ({Funct7,Funct3}) - 10'b0100000_111: InvB = 1'b1; //andn - 10'b0100000_110: InvB = 1'b1; //orn - 10'b0100000_100: InvB = 1'b1; //xnor + 10'b0100000_111: InvB = 1'b0; //andn + 10'b0100000_110: InvB = 1'b0; //orn + 10'b0100000_100: InvB = 1'b0; //xnor default: InvB = 1'b0; endcase diff --git a/src/ieu/bmu/clmul.sv.bak b/src/ieu/bmu/clmul.sv.bak new file mode 100644 index 000000000..36f1dea21 --- /dev/null +++ b/src/ieu/bmu/clmul.sv.bak @@ -0,0 +1,64 @@ +/////////////////////////////////////////// +// clmul.sv +// +// Written: Kevin Kim and Kip Macsai-Goren +// Created: 1 February 2023 +// Modified: +// +// Purpose: Carry-Less multiplication top-level unit +// +// Documentation: RISC-V System on Chip Design Chapter *** +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module clmul #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, // Operands + output logic [WIDTH-1:0] ClmulResult); // ZBS result + + logic [WIDTH-1:0] pp [WIDTH-1:0]; //partial AND products + // Note: only generates the bottom WIDTH bits of the carryless multiply. + // To get the high bits or the reversed bits, the inputs can be shifted and reversed + // as they are in zbc where this is instantiated + /* + genvar i; + for (i=0; i Date: Tue, 14 Feb 2023 13:07:03 -0800 Subject: [PATCH 047/231] removed unncessary stuff --- src/ieu/bmu/clmul.sv.bak | 64 ---------------------------------------- 1 file changed, 64 deletions(-) delete mode 100644 src/ieu/bmu/clmul.sv.bak diff --git a/src/ieu/bmu/clmul.sv.bak b/src/ieu/bmu/clmul.sv.bak deleted file mode 100644 index 36f1dea21..000000000 --- a/src/ieu/bmu/clmul.sv.bak +++ /dev/null @@ -1,64 +0,0 @@ -/////////////////////////////////////////// -// clmul.sv -// -// Written: Kevin Kim and Kip Macsai-Goren -// Created: 1 February 2023 -// Modified: -// -// Purpose: Carry-Less multiplication top-level unit -// -// Documentation: RISC-V System on Chip Design Chapter *** -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module clmul #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands - output logic [WIDTH-1:0] ClmulResult); // ZBS result - - logic [WIDTH-1:0] pp [WIDTH-1:0]; //partial AND products - // Note: only generates the bottom WIDTH bits of the carryless multiply. - // To get the high bits or the reversed bits, the inputs can be shifted and reversed - // as they are in zbc where this is instantiated - /* - genvar i; - for (i=0; i Date: Sat, 11 Feb 2023 21:22:33 -0800 Subject: [PATCH 048/231] git --- src/ieu/alu.sv | 109 ++++++++---------------------------------- src/ieu/controller.sv | 39 +++++---------- 2 files changed, 32 insertions(+), 116 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index ddead9738..6c52432d9 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -32,78 +32,31 @@ module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform - input logic [6:0] Funct7, + input logic [6:0] Funct7, // Funct7 from execute stage input logic [2:0] Funct3, // With ALUControl, indicates operation to perform output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands - // CondInvB = ~B when subtracting or inverted operand instruction in ZBB, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. + // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] ZBBResult, ZBSResult; - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult, CondShiftA, ALUResult; // Intermediate results + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult; // Intermediate results logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction logic SubArith; // Performing subtraction or arithmetic right shift logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B - logic InvB; // Is Inverted Operand Instruction (ZBB) - logic Rotate; // Is rotate operation - logic ZbaAdd; // Is ZBA Add Operation + logic rotate; // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; - - - // Addition - if (`ZBA_SUPPORTED) - always_comb begin - ZbaAdd = (Funct7 == 7'b0010000 | Funct7 == 7'b0000100); - case({Funct7, Funct3, W64}) - 11'b0010000_010_0: CondShiftA = {A[WIDTH-2:0], {1'b0}}; //sh1add - 11'b0010000_100_0: CondShiftA = {A[WIDTH-3:0], {2'b00}}; //sh2add - 11'b0010000_110_0: CondShiftA = {A[WIDTH-4:0], {3'b000}}; //sh3add - 11'b0000100_000_1: CondShiftA = {{32{1'b0}}, A[31:0]}; //add.uw - 11'b0010000_010_1: CondShiftA = {{31{1'b0}},A[31:0], {1'b0}}; //sh1add.uw - 11'b0010000_100_1: CondShiftA = {{30{1'b0}},A[31:0], {2'b00}}; //sh2add.uw - 11'b0010000_110_1: CondShiftA = {{29{1'b0}},A[31:0], {3'b000}}; //sh3add.uw - default: CondShiftA = A; - endcase - end - else begin - assign CondShiftA = A; - assign ZbaAdd = 0; - end - - if (`ZBB_SUPPORTED) - always_comb begin - case ({Funct7,Funct3}) - 10'b0100000_111: InvB = 1'b0; //andn - 10'b0100000_110: InvB = 1'b0; //orn - 10'b0100000_100: InvB = 1'b0; //xnor - default: InvB = 1'b0; - endcase - - casez ({Funct7, Funct3}) - 10'b011000?_101: Rotate = 1'b1; - 10'b000010?_001: Rotate = 1'b0; - 10'b0110000_001: Rotate = 1'b1; - default: Rotate = 1'b0; - endcase - end - else begin - assign InvB = 1'b0; - assign Rotate = 1'b0; - end - - assign CondInvB = (SubArith | InvB) ? ~B : B; - - assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; + assign CondInvB = SubArith ? ~B : B; + assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts - shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Rotate(Rotate), .Y(Shift)); + shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(rotate)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign @@ -121,42 +74,18 @@ module alu #(parameter WIDTH=32) ( // Select appropriate ALU Result always_comb - if (~ALUOp | ZbaAdd) FullResult = Sum; // Always add for ALUOp = 0 (address generation) and ZBA - else casez (Funct3) // Otherwise check Funct3 - 3'b000: FullResult = Sum; // add or sub - 3'b?01: FullResult = Shift; // sll, sra, or srl - 3'b010: FullResult = SLT; // slt - 3'b011: FullResult = SLTU; // sltu - 3'b100: FullResult = A ^ CondInvB; // xor - 3'b110: FullResult = A | CondInvB; // or - 3'b111: FullResult = A & CondInvB; // and + if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) + else casez (Funct3) // Otherwise check Funct3 + 3'b000: FullResult = Sum; // add or sub + 3'b?01: FullResult = Shift; // sll, sra, or srl + 3'b010: FullResult = SLT; // slt + 3'b011: FullResult = SLTU; // sltu + 3'b100: FullResult = A ^ B; // xor + 3'b110: FullResult = A | B; // or + 3'b111: FullResult = A & B; // and endcase - if (`ZBS_SUPPORTED) - zbs #(WIDTH) zbs(.A, .B, .Funct7, .Funct3, .ZBSResult); - else assign ZBSResult = 0; - - - if (`ZBB_SUPPORTED) - zbb #(WIDTH) zbb(.A, .B, .Funct3, .Funct7, .W64, .ZBBResult); - else assign ZBBResult = 0; - // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (WIDTH == 64) assign ALUResult = (W64 & ~ZbaAdd) ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; - else assign ALUResult = FullResult; - - if (`ZBB_SUPPORTED | `ZBA_SUPPORTED | `ZBS_SUPPORTED | `ZBC_SUPPORTED) begin - always_comb - casez({Funct7}) - 7'b010010?: Result = ZBSResult; - 7'b001010?: Result = ZBSResult; - default: Result = ALUResult; - endcase - end else begin - assign Result = ALUResult; - end - - - -endmodule - + if (WIDTH == 64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + else assign Result = FullResult; +endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index c6879ffd9..aff094820 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -149,7 +149,7 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (Funct7D == 7'b0010000 & `ZBA_SUPPORTED) | (Funct7D == 7'b0100100 & `ZBS_SUPPORTED)) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & `M_SUPPORTED) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide @@ -161,10 +161,7 @@ module controller( else if (Funct7D == 7'b0000001 & `M_SUPPORTED & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide else - if ((Funct7D == 7'b0000100 | Funct7D == 7'b0010000) & `ZBA_SUPPORTED) - ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // adduw, sh1adduw, sh2adduw, sh3adduw - else - ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction + ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction 7'b1100011: ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches 7'b1100111: ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr 7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal @@ -193,23 +190,13 @@ module controller( assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001); assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i - if (`ZBA_SUPPORTED) begin - // ALU Decoding is more comprehensive when ZBA is supported - assign sltD = (Funct3D == 3'b010 & OpD == 7'b0010011); - assign sltuD = (Funct3D == 3'b011 & OpD == 7'b0010011); - assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi - assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu - assign ALUControlD = {W64D, SubArithD, ALUOpD}; - end else begin - // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra - assign sltD = (Funct3D == 3'b010); - assign sltuD = (Funct3D == 3'b011); - assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi - assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu - assign ALUControlD = {W64D, SubArithD, ALUOpD}; - end + // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra + assign sltD = (Funct3D == 3'b010); + assign sltuD = (Funct3D == 3'b011); + assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi + assign sraD = (Funct3D == 3'b101 & Funct7D[5]); + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu + assign ALUControlD = {W64D, SubArithD, ALUOpD}; // Fences // Ordinary fence is presently a nop @@ -228,9 +215,9 @@ module controller( flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(35) controlregE(clk, reset, FlushE, ~StallE, - {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, - {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); + flopenrc #(28) controlregE(clk, reset, FlushE, ~StallE, + {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, + {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE @@ -264,4 +251,4 @@ module controller( // the synchronous DTIM cannot read immediately after write // a cache cannot read or write immediately after a write assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE_SUPPORTED)) | (|AtomicD)); -endmodule +endmodule \ No newline at end of file From 27817c5b1d8dfed76f16a99b3789476be68e3dd4 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 14 Feb 2023 16:06:10 -0800 Subject: [PATCH 049/231] controller passes funct7 from decode to execute --- src/ieu/controller.sv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index aff094820..5f6e33f1c 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -215,9 +215,9 @@ module controller( flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(28) controlregE(clk, reset, FlushE, ~StallE, - {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, - {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); + flopenrc #(35) controlregE(clk, reset, FlushE, ~StallE, + {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, + {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE From 2a58a863712835a87ce897809ef3953d47399c3d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 15 Feb 2023 09:13:10 -0800 Subject: [PATCH 050/231] added ALUResult Signal --- src/ieu/alu.sv | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 6c52432d9..9d945ef8c 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -39,13 +39,13 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult; // Intermediate results - logic Carry, Neg; // Flags: carry out, negative - logic LT, LTU; // Less than, Less than unsigned - logic W64; // RV64 W-type instruction - logic SubArith; // Performing subtraction or arithmetic right shift - logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops - logic Asign, Bsign; // Sign bits of A, B + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate results + logic Carry, Neg; // Flags: carry out, negative + logic LT, LTU; // Less than, Less than unsigned + logic W64; // RV64 W-type instruction + logic SubArith; // Performing subtraction or arithmetic right shift + logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops + logic Asign, Bsign; // Sign bits of A, B logic rotate; // Extract control signals from ALUControl. @@ -86,6 +86,10 @@ module alu #(parameter WIDTH=32) ( endcase // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (WIDTH == 64) assign Result = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; - else assign Result = FullResult; + if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + else assign ALUResult = FullResult; + + if (`ZBC_SUPPORTED) begin + + end else assign Result = ALUResult; endmodule \ No newline at end of file From 2eb8721843c4b99b98364275d2b0d7e813da9cea Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 15 Feb 2023 09:35:07 -0800 Subject: [PATCH 051/231] continued ZBC integration into ALU --- src/ieu/alu.sv | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 9d945ef8c..088eefb5c 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -39,7 +39,7 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate results + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult; // Intermediate results logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction @@ -90,6 +90,16 @@ module alu #(parameter WIDTH=32) ( else assign ALUResult = FullResult; if (`ZBC_SUPPORTED) begin - + zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); + end + + if (`ZBC_SUPPORTED) begin + always_comb + case ({Funct7, Funct3}) + 10'b0000101_001: Result = ZBCResult; + 10'b0000101_011: Result = ZBCResult; + 10'b0000101_010: Result = ZBCResult; + default: Result = ALUResult; + endcase end else assign Result = ALUResult; endmodule \ No newline at end of file From 8feeaa5e94ea932929ace311c1498ec8ca4457c0 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 15 Feb 2023 17:37:09 -0800 Subject: [PATCH 052/231] zbc and carry-less multiply work properly --- src/ieu/bmu/clmul.sv | 41 +++++++++++++++-------------------------- src/ieu/bmu/zbc.sv | 34 ++++++++++++++-------------------- 2 files changed, 29 insertions(+), 46 deletions(-) diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index f1917f550..280c3fbd7 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// clmul.sv +// clmul.sv (carry-less multiplier) // // Written: Kevin Kim and Kip Macsai-Goren // Created: 1 February 2023 @@ -30,35 +30,24 @@ `include "wally-config.vh" module clmul #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] A, B, // Operands output logic [WIDTH-1:0] ClmulResult); // ZBS result - logic [WIDTH-1:0] pp [WIDTH-1:0]; //partial AND products - // Note: only generates the bottom WIDTH bits of the carryless multiply. - // To get the high bits or the reversed bits, the inputs can be shifted and reversed - // as they are in zbc where this is instantiated - /* - genvar i; - for (i=0; i CLMUL -> MUX -> RESULT - //alternate could have CLMUL * 3 -> MUX -> MUX always_comb begin casez (Funct3) 3'b001: begin //clmul - X = A; - Y = B; + x = A; + y = B; end 3'b011: begin //clmulh - X = {RevA[WIDTH-2:0], {1'b0}}; - Y = {{1'b0}, RevB[WIDTH-2:0]}; + x = {RevA[WIDTH-2:0], {1'b0}}; + y = {{1'b0}, RevB[WIDTH-2:0]}; end 3'b010: begin //clmulr - X = {A[WIDTH-2:0], {1'b0}}; - Y = B; + x = RevA; + y = RevB; end default: begin - X = 0; - Y = 0; + x = 0; + y = 0; end endcase end - clmul clm(.A(X), .B(Y), .ClmulResult(ClmulResult)); - bitreverse brClmulResult(.a(ClmulResult), .b(RevClmulResult)); + clmul #(WIDTH) clm(.A(x), .B(y), .ClmulResult(ClmulResult)); + bitreverse #(WIDTH) brClmulResult(.a(ClmulResult), .b(RevClmulResult)); - assign ZBCResult = (Funct3 == 3'b011) ? RevClmulResult : ClmulResult; + assign ZBCResult = (Funct3 == 3'b011 || Funct3 == 3'b010) ? RevClmulResult : ClmulResult; endmodule \ No newline at end of file From cd13913f0720641f551859e164491f8d00cbb3cd Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 15 Feb 2023 17:38:12 -0800 Subject: [PATCH 053/231] controller forwards funct7 - started the bmu controll register --- src/ieu/controller.sv | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 5f6e33f1c..51f27ef74 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -149,7 +149,7 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (Funct7D == 7'b0000101 & `ZBC_SUPPORTED)) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & `M_SUPPORTED) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide @@ -215,9 +215,9 @@ module controller( flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(35) controlregE(clk, reset, FlushE, ~StallE, - {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, Funct7D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, - {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, Funct7E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); + flopenrc #(28) controlregE(clk, reset, FlushE, ~StallE, + {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, + {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE @@ -239,6 +239,9 @@ module controller( {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE}, {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM}); + // BMU control register + flopenrc#(7) controlregBMU(clk, reset, FlushM, ~StallM, {Funct7D}, {Funct7E}); + // Writeback stage pipeline control register flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW, {RegWriteM, ResultSrcM, IntDivM}, From 50f02624984697732de59b95f1c5ef8d2cb9f57b Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 15 Feb 2023 17:39:37 -0800 Subject: [PATCH 054/231] zbc configurability and select mux --- src/ieu/alu.sv | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 088eefb5c..3026765b2 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -89,11 +89,12 @@ module alu #(parameter WIDTH=32) ( if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; else assign ALUResult = FullResult; - if (`ZBC_SUPPORTED) begin + if (`ZBC_SUPPORTED) begin: zbc zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); - end + end else assign ZBCResult = 0; + - if (`ZBC_SUPPORTED) begin + if (`ZBC_SUPPORTED) begin : zbcdecoder always_comb case ({Funct7, Funct3}) 10'b0000101_001: Result = ZBCResult; From 921a32faf971aa7883dd7e685315f91dc40cc1da Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 15 Feb 2023 17:42:32 -0800 Subject: [PATCH 055/231] added comments to zbc units --- src/ieu/alu.sv | 2 ++ src/ieu/bmu/clmul.sv | 3 +-- src/ieu/bmu/zbc.sv | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 3026765b2..60bcf5528 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -89,11 +89,13 @@ module alu #(parameter WIDTH=32) ( if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; else assign ALUResult = FullResult; + //NOTE: This looks good and can be merged. if (`ZBC_SUPPORTED) begin: zbc zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); end else assign ZBCResult = 0; + //NOTE: Unoptimized, eventually want to look at ZBCop/ZBSop/ZBAop/ZBBop from decoder to select from a B instruction or the ALU if (`ZBC_SUPPORTED) begin : zbcdecoder always_comb case ({Funct7, Funct3}) diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 280c3fbd7..46893573c 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -33,8 +33,7 @@ module clmul #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands output logic [WIDTH-1:0] ClmulResult); // ZBS result - logic [(WIDTH*WIDTH)-1:0] s; - logic [WIDTH-1:0] intial; + logic [(WIDTH*WIDTH)-1:0] s; // intermediary signals for carry-less multiply integer i; integer j; diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 400aaf531..580cdacca 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -38,10 +38,10 @@ module zbc #(parameter WIDTH=32) ( logic [WIDTH-1:0] RevA, RevB; logic [WIDTH-1:0] x,y; - bitreverse #(WIDTH) brA(.a(A), .b(RevA)); bitreverse #(WIDTH) brB(.a(B), .b(RevB)); + //NOTE: Optimize this when doing decoder stuff. always_comb begin casez (Funct3) 3'b001: begin //clmul From f0c81247e45367d6f8f91bca3431b31645f5acb0 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 07:50:45 -0800 Subject: [PATCH 056/231] Added ALUSelect signal into datapath, ieu, controller --- src/ieu/controller.sv | 18 +++++++++++++----- src/ieu/datapath.sv | 3 ++- src/ieu/ieu.sv | 5 +++-- 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 51f27ef74..7e054b5d7 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -46,6 +46,7 @@ module controller( output logic [2:0] ALUControlE, // ALU operation to perform output logic ALUSrcAE, ALUSrcBE, // ALU operands output logic ALUResultSrcE, // Selects result to pass on to Memory stage + output logic [2:0] ALUSelectE, // ALU mux select signal output logic MemReadE, CSRReadE, // Instruction reads memory, reads a CSR (needed for Hazard unit) output logic [2:0] Funct3E, // Instruction's funct3 field output logic [6:0] Funct7E, // Instruction's funct7 field @@ -90,6 +91,7 @@ module controller( logic BranchD, BranchE; // Branch instruction logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) logic [2:0] ALUControlD; // Determines ALU operation + logic [2:0] ALUSelectD; // ALU mux select signal logic ALUSrcAD, ALUSrcBD; // ALU inputs logic ALUResultSrcD, W64D, MDUD; // ALU result, is RV64 W-type, is multiply/divide instruction logic CSRZeroSrcD; // Ignore setting and clearing zeros to CSR @@ -102,7 +104,7 @@ module controller( logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$ logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu - logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions + logic subD, sraD, sltD, sltuD, bextD; // Indicates if is one of these instructions logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; @@ -195,9 +197,18 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); // TRUE for R-type subtracts and sra, slt, sltu + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & bextD)); // TRUE for R-type subtracts and sra, slt, sltu assign ALUControlD = {W64D, SubArithD, ALUOpD}; + if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .bextD, .StallE, .FlushE, .Funct7E, .ALUSelectE); + end else begin: bitmanipi + assign ALUSelectD = Funct3D; + assign ALUSelectE = Funct3E; + assign bextD = 1'b0; + assign Funct7E = 7'b0; + end + // Fences // Ordinary fence is presently a nop // fence.i flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented @@ -239,9 +250,6 @@ module controller( {RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE}, {RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM}); - // BMU control register - flopenrc#(7) controlregBMU(clk, reset, FlushM, ~StallM, {Funct7D}, {Funct7E}); - // Writeback stage pipeline control register flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW, {RegWriteM, ResultSrcM, IntDivM}, diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index f715a5d5d..3cf12b37d 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -15,6 +15,7 @@ module datapath ( input logic [2:0] ALUControlE, // Indicate operation ALU performs input logic ALUSrcAE, ALUSrcBE, // ALU operands input logic ALUResultSrcE, // Selects result to pass on to Memory stage + input logic [2:0] ALUSelectE, // ALU mux select signal input logic JumpE, // Is a jump (j) instruction input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) @@ -81,7 +82,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct7E, Funct3E, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, Funct7E, Funct3E, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index f7a201527..b8ee90d0b 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -79,6 +79,7 @@ module ieu ( logic ALUSrcAE, ALUSrcBE; // ALU source operands logic [2:0] ResultSrcW; // Selects result in Writeback stage logic ALUResultSrcE; // Selects ALU result to pass on to Memory stage + logic [2:0] ALUSelectE; // ALU select mux signal logic SCE; // Store Conditional instruction logic FWriteIntM; // FPU writing to integer register file logic IntDivW; // Integer divide instruction @@ -95,7 +96,7 @@ module ieu ( controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, - .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, + .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, .Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, @@ -103,7 +104,7 @@ module ieu ( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, - .ALUControlE, .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE, + .ALUControlE, .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, From ff365de54a04fbd7ea7f6cdb3e6565a1dc38a23a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 07:50:59 -0800 Subject: [PATCH 057/231] added BMU controll --- src/ieu/bmu/bmuctrl.sv | 86 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 src/ieu/bmu/bmuctrl.sv diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv new file mode 100644 index 000000000..3b93cd140 --- /dev/null +++ b/src/ieu/bmu/bmuctrl.sv @@ -0,0 +1,86 @@ +/////////////////////////////////////////// +// controller.sv +// +// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu +// Created: 9 January 2021 +// Modified: +// +// Purpose: Top level controller module +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +// NOTE: DO we want to make this XLEN parameterized? +module bmuctrl( + input logic clk, reset, + // Decode stage control signals + input logic StallD, FlushD, // Stall, flush Decode stage + input logic [31:0] InstrD, // Instruction in Decode stage + output logic [2:0] ALUSelectD, // ALU Mux select signal + output logic bextD, // Indicates if bit extract instruction + // Execute stage control signals + input logic StallE, FlushE, // Stall, flush Execute stage + output logic [6:0] Funct7E, // Instruction's funct7 field (note: eventually want to get rid of this) + output logic [2:0] ALUSelectE +); + + logic [6:0] OpD; // Opcode in Decode stage + logic [2:0] Funct3D; // Funct3 field in Decode stage + logic [6:0] Funct7D; // Funct7 field in Decode stage + logic [4:0] Rs1D; // Rs1 source register in Decode stage + + `define BMUCTRLW 4 + + logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals + + + // Extract fields + assign OpD = InstrD[6:0]; + assign Funct3D = InstrD[14:12]; + assign Funct7D = InstrD[31:25]; + assign Rs1D = InstrD[19:15]; + + // Main Instruction Decoder + always_comb + casez({OpD, Funct7D, Funct3D}) + // ALUSelect_bextD + 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0; // bclri + 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_1; // bexti + 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0; // binvi + 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0; // bseti + 17'b0110011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0; // bclr + 17'b0110011_010010?_101: BMUControlsD = `BMUCTRLW'b101_1; // bext + 17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0; // binv + 17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0; // bset + 17'b0110011_0?00000_?01: BMUControlsD = `BMUCTRLW'b001_0; // sra, srl, sll + default: BMUControlsD = {Funct3D, {1'b0}};// not B instruction or shift + endcase + + // Unpack Control Signals + + assign {ALUSelectD,bextD} = BMUControlsD; + + + + // BMU Execute stage pipieline control register + flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {Funct7D, ALUSelectD}, {Funct7E, ALUSelectE}); +endmodule \ No newline at end of file From 5b341ac3a781b92d30c0f81bb2048528c783e1c1 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 07:51:10 -0800 Subject: [PATCH 058/231] alu handles ALU select instead of funct3 --- src/ieu/alu.sv | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 60bcf5528..2ef9df8ae 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -32,8 +32,9 @@ module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform - input logic [6:0] Funct7, // Funct7 from execute stage - input logic [2:0] Funct3, // With ALUControl, indicates operation to perform + input logic [2:0] ALUSelect, // ALU mux select signal + input logic [6:0] Funct7, // Funct7 from execute stage (we only need this for b instructions and should be optimized out later) + input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands @@ -46,7 +47,7 @@ module alu #(parameter WIDTH=32) ( logic SubArith; // Performing subtraction or arithmetic right shift logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B - logic rotate; + logic Rotate; // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; @@ -56,7 +57,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts - shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(rotate)); + shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(1'b0)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign @@ -75,7 +76,7 @@ module alu #(parameter WIDTH=32) ( // Select appropriate ALU Result always_comb if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) - else casez (Funct3) // Otherwise check Funct3 + else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect 3'b000: FullResult = Sum; // add or sub 3'b?01: FullResult = Shift; // sll, sra, or srl 3'b010: FullResult = SLT; // slt From 290fcd178968fd75b79ea89bed3165c4ed6786ce Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 07:51:28 -0800 Subject: [PATCH 059/231] comment formatting --- src/ieu/shifter.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 15c7b411e..e898edde6 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -32,7 +32,7 @@ module shifter ( input logic [`XLEN-1:0] A, // Source input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Arith, W64, Rotate, // Shift right, arithmetic, RV64 W-type shift + input logic Right, Arith, W64, Rotate, // Shift right, arithmetic, RV64 W-type shift output logic [`XLEN-1:0] Y); // Shifted result logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits From ab542a5bc3a52389510d8828a569846515e817d6 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 07:52:54 -0800 Subject: [PATCH 060/231] comments --- src/ieu/bmu/bmuctrl.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 3b93cd140..9f0e2b763 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -1,8 +1,8 @@ /////////////////////////////////////////// // controller.sv // -// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu -// Created: 9 January 2021 +// Written: Kevin Kim +// Created: 16 February 2023 // Modified: // // Purpose: Top level controller module From ada6023a413a48a2a8602f40abe75feaa0f2a52c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 07:53:14 -0800 Subject: [PATCH 061/231] comments --- src/ieu/bmu/bmuctrl.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 9f0e2b763..2b0bb63f9 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -5,7 +5,7 @@ // Created: 16 February 2023 // Modified: // -// Purpose: Top level controller module +// Purpose: Top level B instrution controller module // // Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) // From 44c9612a5c7d51205a7d97847b7b2e115e9682f2 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 08:21:55 -0800 Subject: [PATCH 062/231] added BSelect Signal - BSelect [3:0] is a one hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction --- src/ieu/alu.sv | 18 +++++++++++------- src/ieu/bmu/bmuctrl.sv | 33 +++++++++++++++++---------------- src/ieu/controller.sv | 9 +++++---- src/ieu/datapath.sv | 3 ++- src/ieu/ieu.sv | 5 +++-- 5 files changed, 38 insertions(+), 30 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 2ef9df8ae..e69335ce0 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -33,6 +33,7 @@ module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform input logic [2:0] ALUSelect, // ALU mux select signal + input logic [3:0] BSelect, // One-Hot encoding of ZBA_ZBB_ZBC_ZBS instruction input logic [6:0] Funct7, // Funct7 from execute stage (we only need this for b instructions and should be optimized out later) input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect output logic [WIDTH-1:0] Result, // ALU result @@ -40,15 +41,18 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult; // Intermediate results - logic Carry, Neg; // Flags: carry out, negative - logic LT, LTU; // Less than, Less than unsigned - logic W64; // RV64 W-type instruction - logic SubArith; // Performing subtraction or arithmetic right shift - logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops - logic Asign, Bsign; // Sign bits of A, B + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult, CondMaskB; // Intermediate results + logic Carry, Neg; // Flags: carry out, negative + logic LT, LTU; // Less than, Less than unsigned + logic W64; // RV64 W-type instruction + logic SubArith; // Performing subtraction or arithmetic right shift + logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops + logic Asign, Bsign; // Sign bits of A, B logic Rotate; + + decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], CondMaskB); + // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 2b0bb63f9..7c95f06c5 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -36,19 +36,20 @@ module bmuctrl( input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage output logic [2:0] ALUSelectD, // ALU Mux select signal - output logic bextD, // Indicates if bit extract instruction // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [6:0] Funct7E, // Instruction's funct7 field (note: eventually want to get rid of this) - output logic [2:0] ALUSelectE + output logic [2:0] ALUSelectE, + output logic [3:0] BSelectE // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding ); logic [6:0] OpD; // Opcode in Decode stage logic [2:0] Funct3D; // Funct3 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs1D; // Rs1 source register in Decode stage + logic [3:0] BSelectD; // Indicates if ZBA_ZBB_ZBC_ZBS instruction decode stage - `define BMUCTRLW 4 + `define BMUCTRLW 7 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -62,25 +63,25 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_bextD - 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0; // bclri - 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_1; // bexti - 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0; // binvi - 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0; // bseti - 17'b0110011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0; // bclr - 17'b0110011_010010?_101: BMUControlsD = `BMUCTRLW'b101_1; // bext - 17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0; // binv - 17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0; // bset - 17'b0110011_0?00000_?01: BMUControlsD = `BMUCTRLW'b001_0; // sra, srl, sll - default: BMUControlsD = {Funct3D, {1'b0}};// not B instruction or shift + // ALUSelect_zbsD + 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclri + 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001; // bexti + 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binvi + 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bseti + 17'b0110011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclr + 17'b0110011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001; // bext + 17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binv + 17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bset + 17'b0110011_0?00000_?01: BMUControlsD = `BMUCTRLW'b001_0001; // sra, srl, sll + default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,bextD} = BMUControlsD; + assign {ALUSelectD,BSelectD} = BMUControlsD; // BMU Execute stage pipieline control register - flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {Funct7D, ALUSelectD}, {Funct7E, ALUSelectE}); + flopenrc#(14) controlregBMU(clk, reset, FlushE, ~StallE, {Funct7D, ALUSelectD, BSelectD}, {Funct7E, ALUSelectE, BSelectE}); endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 7e054b5d7..0ed3d727e 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -56,6 +56,7 @@ module controller( output logic JumpE, // jump instruction output logic SCE, // Store Conditional instruction output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) + output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction // Memory stage control signals input logic StallM, FlushM, // Stall, flush Memory stage output logic [1:0] MemRWM, // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write @@ -104,7 +105,7 @@ module controller( logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$ logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu - logic subD, sraD, sltD, sltuD, bextD; // Indicates if is one of these instructions + logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; @@ -197,15 +198,15 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & bextD)); // TRUE for R-type subtracts and sra, slt, sltu + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & BSelectE[0] & ALUSelectD == 3'b101)); // TRUE for R-type subtracts and sra, slt, sltu, bext assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .bextD, .StallE, .FlushE, .Funct7E, .ALUSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .StallE, .FlushE, .Funct7E, .ALUSelectE, BSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; - assign bextD = 1'b0; + assign BSelectE = 4'b000; assign Funct7E = 7'b0; end diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 3cf12b37d..604eab8d0 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -18,6 +18,7 @@ module datapath ( input logic [2:0] ALUSelectE, // ALU mux select signal input logic JumpE, // Is a jump (j) instruction input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) + input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B @@ -82,7 +83,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, Funct7E, Funct3E, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, Funct7E, Funct3E, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index b8ee90d0b..ba1d8756c 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -83,6 +83,7 @@ module ieu ( logic SCE; // Store Conditional instruction logic FWriteIntM; // FPU writing to integer register file logic IntDivW; // Integer divide instruction + logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding // Forwarding signals logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers @@ -96,7 +97,7 @@ module ieu ( controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, - .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, + .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .BSelectE, .MemReadE, .CSRReadE, .Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, @@ -105,7 +106,7 @@ module ieu ( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .ALUControlE, .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, - .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, + .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); From 323d14f9d92d53eb279f53831a73eff9116cad87 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 08:22:13 -0800 Subject: [PATCH 063/231] added alu changes to previous commit --- src/ieu/alu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index e69335ce0..9311c1bc1 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -33,7 +33,7 @@ module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform input logic [2:0] ALUSelect, // ALU mux select signal - input logic [3:0] BSelect, // One-Hot encoding of ZBA_ZBB_ZBC_ZBS instruction + input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [6:0] Funct7, // Funct7 from execute stage (we only need this for b instructions and should be optimized out later) input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect output logic [WIDTH-1:0] Result, // ALU result From 07eaf146c2d5715bcd3d546b312bd40a18ecbd64 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 09:51:49 -0800 Subject: [PATCH 064/231] alu looks at BSelect, added BSelect one hot signal --- src/ieu/alu.sv | 61 ++++++++++++++++++++++++++++-------------- src/ieu/bmu/bmuctrl.sv | 3 ++- src/ieu/controller.sv | 7 ++--- 3 files changed, 47 insertions(+), 24 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 9311c1bc1..3bb6ba347 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -42,6 +42,7 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult, CondMaskB; // Intermediate results + logic [WIDTH-1:0] MaskB; logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction @@ -51,13 +52,16 @@ module alu #(parameter WIDTH=32) ( logic Rotate; - decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], CondMaskB); + if (`ZBS_SUPPORTED) begin: zbsdec + decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); + assign CondMaskB = (BSelect[0]) ? MaskB : B; + end else assign CondMaskB = B; // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; // Addition - assign CondInvB = SubArith ? ~B : B; + assign CondInvB = SubArith ? ~CondMaskB : CondMaskB; assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts @@ -78,17 +82,35 @@ module alu #(parameter WIDTH=32) ( assign SLTU = {{(WIDTH-1){1'b0}}, LTU}; // Select appropriate ALU Result - always_comb - if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) - else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect - 3'b000: FullResult = Sum; // add or sub - 3'b?01: FullResult = Shift; // sll, sra, or srl - 3'b010: FullResult = SLT; // slt - 3'b011: FullResult = SLTU; // sltu - 3'b100: FullResult = A ^ B; // xor - 3'b110: FullResult = A | B; // or - 3'b111: FullResult = A & B; // and - endcase + if (`ZBS_SUPPORTED) begin + always_comb + if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) + else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect + 3'b000: FullResult = Sum; // add or sub + 3'b001: FullResult = Shift; // sll, sra, or srl + 3'b010: FullResult = SLT; // slt + 3'b011: FullResult = SLTU; // sltu + 3'b100: FullResult = A ^ B; // xor, binv + 3'b110: FullResult = A | B; // or, bset + 3'b111: FullResult = A & B; // and, bclr + 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & B)}};// bext + endcase + end + else begin + always_comb + if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) + else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect + 3'b000: FullResult = Sum; // add or sub + 3'b?01: FullResult = Shift; // sll, sra, or srl + 3'b010: FullResult = SLT; // slt + 3'b011: FullResult = SLTU; // sltu + 3'b100: FullResult = A ^ B; // xor + 3'b110: FullResult = A | B; // or + 3'b111: FullResult = A & B; // and + endcase + + end + // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; @@ -99,15 +121,14 @@ module alu #(parameter WIDTH=32) ( zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); end else assign ZBCResult = 0; - //NOTE: Unoptimized, eventually want to look at ZBCop/ZBSop/ZBAop/ZBBop from decoder to select from a B instruction or the ALU - if (`ZBC_SUPPORTED) begin : zbcdecoder + if (`ZBC_SUPPORTED | `ZBS_SUPPORTED) begin : zbdecoder always_comb - case ({Funct7, Funct3}) - 10'b0000101_001: Result = ZBCResult; - 10'b0000101_011: Result = ZBCResult; - 10'b0000101_010: Result = ZBCResult; - default: Result = ALUResult; + case (BSelect) + //ZBA_ZBB_ZBC_ZBS + 4'b0001: Result = FullResult; + 4'b0010: Result = ZBCResult; + default: Result = ALUResult; endcase end else assign Result = ALUResult; endmodule \ No newline at end of file diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 7c95f06c5..8b051e731 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -36,6 +36,7 @@ module bmuctrl( input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage output logic [2:0] ALUSelectD, // ALU Mux select signal + output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [6:0] Funct7E, // Instruction's funct7 field (note: eventually want to get rid of this) @@ -47,7 +48,6 @@ module bmuctrl( logic [2:0] Funct3D; // Funct3 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs1D; // Rs1 source register in Decode stage - logic [3:0] BSelectD; // Indicates if ZBA_ZBB_ZBC_ZBS instruction decode stage `define BMUCTRLW 7 @@ -73,6 +73,7 @@ module bmuctrl( 17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binv 17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bset 17'b0110011_0?00000_?01: BMUControlsD = `BMUCTRLW'b001_0001; // sra, srl, sll + 17'b0110011_0000101_???: BMUControlsD = `BMUCTRLW'b001_0010; // ZBC instruction default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift endcase diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 0ed3d727e..e24a5e5fa 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -116,6 +116,7 @@ module controller( logic FenceD, FenceE, FenceM; // Fence instruction logic SFenceVmaD; // sfence.vma instruction logic IntDivM; // Integer divide instruction + logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage // Extract fields @@ -152,7 +153,7 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (Funct7D == 7'b0000101 & `ZBC_SUPPORTED)) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (BSelectD[1] | BSelectD[0])) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & `M_SUPPORTED) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide @@ -198,11 +199,11 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & BSelectE[0] & ALUSelectD == 3'b101)); // TRUE for R-type subtracts and sra, slt, sltu, bext + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & BSelectD[0] && (ALUSelectD == 3'b101 | ALUSelectD == 3'b111))); // TRUE for R-type subtracts and sra, slt, sltu, bext assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .StallE, .FlushE, .Funct7E, .ALUSelectE, BSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .StallE, .FlushE, .Funct7E, .ALUSelectE, .BSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; From 7344f3ef302a90a8d82aee5c8960de43abc010b4 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 17 Feb 2023 09:51:55 -0800 Subject: [PATCH 065/231] Modified arch64 tests to remove floating point and double tests from hanging make --- tests/riscof/Makefile | 6 +++--- tests/riscof/spike/spike_rv64gc_isa.yaml | 4 ++-- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index d963e4f0d..00b7c3ba9 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -8,8 +8,8 @@ wally_workdir = $(work)/wally-riscv-arch-test current_dir = $(shell pwd) #XLEN ?= 64 -#all: root wally32 wally64 -all: root arch32 wally32 wally32e arch64 wally64 +all: root arch64 +#all: root arch32 wally32 wally32e arch64 wally64 root: mkdir -p $(work_dir) @@ -25,7 +25,7 @@ arch32: rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv32i_m/ || echo "error suppressed" arch64: - riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser + riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser --no-dut-run rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed" # Also copy F and D tests to RV64 rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed" diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index e6bfc72ef..ad745f47b 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -1,12 +1,12 @@ hart_ids: [0] hart0: # ISA: RV64IMAFDCSUZicsr_Zifencei - ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs + ISA: RV64IMACSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] misa: - reset-val: 0x800000000014112D + reset-val: 0x8000000000141105 rv32: accessible: false rv64: From ea38e05773db22e848f7e3b03f590253f366d19e Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 17 Feb 2023 09:57:56 -0800 Subject: [PATCH 066/231] fixed makefile for 32 bit arch tests, restored original make for all others --- tests/riscof/Makefile | 6 +++--- tests/riscof/spike/spike_rv32gc_isa.yaml | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/riscof/Makefile b/tests/riscof/Makefile index 00b7c3ba9..24b499d11 100644 --- a/tests/riscof/Makefile +++ b/tests/riscof/Makefile @@ -8,8 +8,8 @@ wally_workdir = $(work)/wally-riscv-arch-test current_dir = $(shell pwd) #XLEN ?= 64 -all: root arch64 -#all: root arch32 wally32 wally32e arch64 wally64 +#all: root wally32 wally64 +all: root arch32 wally32 wally32e arch64 wally64 root: mkdir -p $(work_dir) @@ -25,7 +25,7 @@ arch32: rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv32i_m/ || echo "error suppressed" arch64: - riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser --no-dut-run + riscof run --work-dir=$(work_dir) --config=config64.ini --suite=$(arch_dir)/riscv-test-suite/ --env=$(arch_dir)/riscv-test-suite/env --no-browser rsync -a $(work_dir)/rv64i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed" # Also copy F and D tests to RV64 rsync -a $(work_dir)/rv32i_m/ $(arch_workdir)/rv64i_m/ || echo "error suppressed" diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index 478bbe56d..4a5935244 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,12 +1,12 @@ hart_ids: [0] hart0: - ISA: RV32IMAFDCZicsr_Zifencei -# ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs + #ISA: RV32IMAFDCZicsr_Zifencei + ISA: RV32IMACZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] misa: - reset-val: 0x4000112D + reset-val: 0x40001105 rv32: accessible: true mxl: From aba4eb80d45f7a83f778db9fd8089d75e3f1cdcb Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 11:02:07 -0800 Subject: [PATCH 067/231] alu bug fix - condmaskb piped in correctly instead of b --- src/ieu/alu.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 3bb6ba347..420cc0a3e 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -90,10 +90,10 @@ module alu #(parameter WIDTH=32) ( 3'b001: FullResult = Shift; // sll, sra, or srl 3'b010: FullResult = SLT; // slt 3'b011: FullResult = SLTU; // sltu - 3'b100: FullResult = A ^ B; // xor, binv - 3'b110: FullResult = A | B; // or, bset - 3'b111: FullResult = A & B; // and, bclr - 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & B)}};// bext + 3'b100: FullResult = A ^ CondMaskB; // xor, binv + 3'b110: FullResult = A | CondMaskB; // or, bset + 3'b111: FullResult = A & CondInvB; // and, bclr + 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}};// bext endcase end else begin From 370ff54875c159d95e084614d73ead69f74cdee6 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 11:16:29 -0800 Subject: [PATCH 068/231] bctrl bug fix - bctrl decodes shift immediate instructions properly --- src/ieu/bmu/bmuctrl.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 8b051e731..4e0f1efc7 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -72,7 +72,7 @@ module bmuctrl( 17'b0110011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001; // bext 17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binv 17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bset - 17'b0110011_0?00000_?01: BMUControlsD = `BMUCTRLW'b001_0001; // sra, srl, sll + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000; // sra, srai, srl, srli, sll, slli 17'b0110011_0000101_???: BMUControlsD = `BMUCTRLW'b001_0010; // ZBC instruction default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift endcase From a1570a88c90bedd38957ad4fd1a7fc723c45b4e7 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 12:54:08 -0800 Subject: [PATCH 069/231] bmuctrl checks for illegal zbs-style instructions --- src/ieu/bmu/bmuctrl.sv | 45 +++++++++++++++++++++++++++++++----------- 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 4e0f1efc7..4217f6431 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -63,18 +63,39 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_zbsD - 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclri - 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001; // bexti - 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binvi - 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bseti - 17'b0110011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclr - 17'b0110011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001; // bext - 17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binv - 17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000; // sra, srai, srl, srli, sll, slli - 17'b0110011_0000101_???: BMUControlsD = `BMUCTRLW'b001_0010; // ZBC instruction - default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift + // ALUSelect_BSelect + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclri + 17'b0010011_0100101_001: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b111_0001; // bclri (rv64) + else + BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001; // bexti + 17'b0010011_0100101_101: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b101_0001; // bexti (rv64) + else + BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001; // binvi + 17'b0010011_0110101_001: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b100_0001; // binvi (rv64) + else + BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001; // bseti + 17'b0010011_0010101_001: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b110_0001; // bseti + else + BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000; // sra, srai, srl, srli, sll, slli + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010; // ZBC instruction + 17'b0110011_0010000_?01: BMUControlsD = `BMUCTRLW'b001_1000; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add + 17'b0110011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add + default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift endcase // Unpack Control Signals From b09d942d6057ea92545ad00b19355abaa749c6e8 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 16:12:09 -0800 Subject: [PATCH 070/231] removed Funct7 in Execute Stage --- src/ieu/alu.sv | 1 - src/ieu/bmu/bmuctrl.sv | 3 +-- src/ieu/controller.sv | 4 +--- src/ieu/datapath.sv | 3 +-- src/ieu/ieu.sv | 5 ++--- 5 files changed, 5 insertions(+), 11 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 420cc0a3e..41891bd21 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -34,7 +34,6 @@ module alu #(parameter WIDTH=32) ( input logic [2:0] ALUControl, // With Funct3, indicates operation to perform input logic [2:0] ALUSelect, // ALU mux select signal input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction - input logic [6:0] Funct7, // Funct7 from execute stage (we only need this for b instructions and should be optimized out later) input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 4217f6431..8782d982b 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -39,7 +39,6 @@ module bmuctrl( output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage - output logic [6:0] Funct7E, // Instruction's funct7 field (note: eventually want to get rid of this) output logic [2:0] ALUSelectE, output logic [3:0] BSelectE // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding ); @@ -105,5 +104,5 @@ module bmuctrl( // BMU Execute stage pipieline control register - flopenrc#(14) controlregBMU(clk, reset, FlushE, ~StallE, {Funct7D, ALUSelectD, BSelectD}, {Funct7E, ALUSelectE, BSelectE}); + flopenrc#(7) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD}, {ALUSelectE, BSelectE}); endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index e24a5e5fa..6996b455f 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -49,7 +49,6 @@ module controller( output logic [2:0] ALUSelectE, // ALU mux select signal output logic MemReadE, CSRReadE, // Instruction reads memory, reads a CSR (needed for Hazard unit) output logic [2:0] Funct3E, // Instruction's funct3 field - output logic [6:0] Funct7E, // Instruction's funct7 field output logic IntDivE, // Integer divide output logic MDUE, // MDU (multiply/divide) operatio output logic W64E, // RV64 W-type operation @@ -203,12 +202,11 @@ module controller( assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .StallE, .FlushE, .Funct7E, .ALUSelectE, .BSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .StallE, .FlushE, .ALUSelectE, .BSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; assign BSelectE = 4'b000; - assign Funct7E = 7'b0; end // Fences diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 604eab8d0..b81e43ee7 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -9,7 +9,6 @@ module datapath ( input logic [`XLEN-1:0] PCE, // PC in Execute stage input logic [`XLEN-1:0] PCLinkE, // PC + 4 (of instruction in Execute stage) input logic [2:0] Funct3E, // Funct3 field of instruction in Execute stage - input logic [6:0] Funct7E, // Funct7 field of instruction in Execute stage input logic StallE, FlushE, // Stall, flush Execute stage input logic [1:0] ForwardAE, ForwardBE, // Forward ALU operands from later stages input logic [2:0] ALUControlE, // Indicate operation ALU performs @@ -83,7 +82,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, Funct7E, Funct3E, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, Funct3E, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index ba1d8756c..236178bc6 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -74,7 +74,6 @@ module ieu ( logic [2:0] ImmSrcD; // Select type of immediate extension logic [1:0] FlagsE; // Comparison flags ({eq, lt}) - logic [6:0] Funct7E; // Instruction's funct7 field in execute stage logic [2:0] ALUControlE; // ALU control indicates function to perform logic ALUSrcAE, ALUSrcBE; // ALU source operands logic [2:0] ResultSrcW; // Selects result in Writeback stage @@ -98,14 +97,14 @@ module ieu ( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .BSelectE, .MemReadE, .CSRReadE, - .Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, + .Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD); datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, - .ALUControlE, .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, + .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, From 01f3cc2838ebbf5219311adb70c34b9bb5bc50a6 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 16:44:16 -0800 Subject: [PATCH 071/231] controller supports ZBA instructions --- src/ieu/controller.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 6996b455f..cbc7ffdea 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -152,7 +152,7 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (BSelectD[1] | BSelectD[0])) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | ((`ZBC_SUPPORTED & BSelectD[1]) | (`ZBS_SUPPORTED & BSelectD[0]) | (`ZBA_SUPPORTED & BSelectD[3]))) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & `M_SUPPORTED) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide From 88d7c3b1f20d9afb3d6d4b98f094a170f485fccd Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 20:14:13 -0800 Subject: [PATCH 072/231] bmuctrl handles .uw instructions --- src/ieu/bmu/bmuctrl.sv | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 8782d982b..e25d8ffcf 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -93,7 +93,11 @@ module bmuctrl( 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000; // sh1add 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000; // sh2add 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add - 17'b0110011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000; // slli.uw default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift endcase From cad0973b6b7fd86f2dd2d8dee6c9c81c1f6ad7dd Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 20:14:47 -0800 Subject: [PATCH 073/231] more elegant ZBA logic in controller --- src/ieu/controller.sv | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index cbc7ffdea..192e16e40 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -105,6 +105,7 @@ module controller( logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions + logic bclrD, bextD; // Indicates if is one of these instructions logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; @@ -159,7 +160,7 @@ module controller( else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction 7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui - 7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000) & `XLEN == 64) + 7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (`ZBA_SUPPORTED & BSelectD[3])) & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i else if (Funct7D == 7'b0000001 & `M_SUPPORTED & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide @@ -193,12 +194,25 @@ module controller( assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001); assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i + if (`ZBA_SUPPORTED) begin + // ALU Decoding is more comprehensive when ZBA is supported. Only conflict with Funct3 is with slt instructionsb + assign sltD = (Funct3D == 3'b010 & (~BSelectD[3])); + end else begin + assign sltD = (Funct3D == 3'b010); + end + + if (`ZBS_SUPPORTED) begin + assign bclrD = (ALUSelectD == 3'b111 & BSelectD[0]); + assign bextD = (ALUSelectD == 3'b101 & BSelectD[0]); + end else begin + assign bclrD = 1'b0; + assign bextD = 1'b0; + end // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra - assign sltD = (Funct3D == 3'b010); - assign sltuD = (Funct3D == 3'b011); + assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & BSelectD[0] && (ALUSelectD == 3'b101 | ALUSelectD == 3'b111))); // TRUE for R-type subtracts and sra, slt, sltu, bext + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD))); // TRUE for R-type subtracts and sra, slt, sltu assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags @@ -206,7 +220,7 @@ module controller( end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; - assign BSelectE = 4'b000; + assign BSelectE = 4'b0000; end // Fences From 9af0ffe3a989d43f19c0dd295a4f6c5c04c5b5f4 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 20:15:12 -0800 Subject: [PATCH 074/231] added zero extend, pre-shift mux to ALU --- src/ieu/alu.sv | 28 ++++++++++++++++++++++++---- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 41891bd21..d880e6535 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -40,8 +40,11 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult, CondMaskB; // Intermediate results - logic [WIDTH-1:0] MaskB; + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult; // Intermediate results + logic [WIDTH-1:0] MaskB; // BitMask of B + logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux + logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux + logic [WIDTH-1:0] CondZextA; // Result of Zero Extend A select mux logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction @@ -56,12 +59,28 @@ module alu #(parameter WIDTH=32) ( assign CondMaskB = (BSelect[0]) ? MaskB : B; end else assign CondMaskB = B; + if (`ZBA_SUPPORTED) begin: zbamuxes + // Zero Extend Mux + if (WIDTH == 64) begin + assign CondZextA = (BSelect[3] & (W64 | Funct3[0])) ? {{(32){1'b0}}, A[31:0]} : A; //NOTE: do we move this mux select logic into the Decode Stage? + end else assign CondZextA = A; + + // Pre-Shift Mux + always_comb + case (Funct3[2:1] & {2{BSelect[3]}}) + 2'b00: CondShiftA = CondZextA; + 2'b01: CondShiftA = {CondZextA[WIDTH-2:0],{1'b0}}; // sh1add + 2'b10: CondShiftA = {CondZextA[WIDTH-3:0],{2'b00}}; // sh2add + 2'b11: CondShiftA = {CondZextA[WIDTH-4:0],{3'b000}}; // sh3add + endcase + end else assign CondShiftA = A; + // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; // Addition assign CondInvB = SubArith ? ~CondMaskB : CondMaskB; - assign {Carry, Sum} = A + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; + assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(1'b0)); @@ -120,13 +139,14 @@ module alu #(parameter WIDTH=32) ( zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); end else assign ZBCResult = 0; - //NOTE: Unoptimized, eventually want to look at ZBCop/ZBSop/ZBAop/ZBBop from decoder to select from a B instruction or the ALU + // Final Result B instruction select mux if (`ZBC_SUPPORTED | `ZBS_SUPPORTED) begin : zbdecoder always_comb case (BSelect) //ZBA_ZBB_ZBC_ZBS 4'b0001: Result = FullResult; 4'b0010: Result = ZBCResult; + 4'b1000: Result = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word. default: Result = ALUResult; endcase end else assign Result = ALUResult; From 5e7ed8804f903b15d6f766eec6b2c8fbbacb117b Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 21:57:19 -0800 Subject: [PATCH 075/231] bmuctrl supports some rotates --- src/ieu/bmu/bmuctrl.sv | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index e25d8ffcf..6d16036bb 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -98,6 +98,15 @@ module bmuctrl( 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add.uw 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000; // add.uw 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000; // slli.uw + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100; // rori (rv32) + 17'b0010011_0110001_101: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b001_0100; // rori (rv64) + else + BMUControlsD = `BMUCTRLW'b000_0000; //illegal instruction default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift endcase From 77fc40149f6a00770d732a3e952ce214d0b0e0f0 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 21:57:34 -0800 Subject: [PATCH 076/231] controller supports some rotates --- src/ieu/controller.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 192e16e40..9c48b26ec 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -153,14 +153,14 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | ((`ZBC_SUPPORTED & BSelectD[1]) | (`ZBS_SUPPORTED & BSelectD[0]) | (`ZBA_SUPPORTED & BSelectD[3]))) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | ((`ZBB_SUPPORTED & BSelectD[2]) | (`ZBC_SUPPORTED & BSelectD[1]) | (`ZBS_SUPPORTED & BSelectD[0]) | (`ZBA_SUPPORTED & BSelectD[3]))) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & `M_SUPPORTED) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction 7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui - 7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (`ZBA_SUPPORTED & BSelectD[3])) & `XLEN == 64) + 7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (`ZBA_SUPPORTED & BSelectD[3]) | (`ZBB_SUPPORTED & BSelectD[2])) & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i else if (Funct7D == 7'b0000001 & `M_SUPPORTED & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide From f85c1058ffa66551503440c834552fd759b0c3e1 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 21:58:26 -0800 Subject: [PATCH 077/231] shifter bug fix - roli not passing unless I keep the MSB (instead of inverting) of truncated offset --- src/ieu/shifter.sv | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index e898edde6..feb346ef1 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -36,7 +36,7 @@ module shifter ( output logic [`XLEN-1:0] Y); // Shifted result logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] amttrunc, offset; // Shift amount adjusted for RV64, right-shift amount + logic [`LOG_XLEN-1:0] amttrunc, offset, CondOffsetTrunc; // Shift amount adjusted for RV64, right-shift amount // Handle left and right shifts with a funnel shifter. // For RV32, only 32-bit shifts are needed. @@ -129,9 +129,11 @@ module shifter ( // Opposite offset for right shifts assign offset = Right ? amttrunc : ~amttrunc; + if (`XLEN == 64) assign CondOffsetTrunc = (W64 & Rotate) ? {{1'b0}, offset[4:0]} : offset; + else assign CondOffsetTrunc = offset; // Funnel operation - assign zshift = z >> offset; + assign zshift = z >> CondOffsetTrunc; assign Y = zshift[`XLEN-1:0]; endmodule From 2ccbde9d09932384bd02b15f04603b3c33cf0c1d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 17 Feb 2023 21:58:49 -0800 Subject: [PATCH 078/231] configured shifter in alu --- src/ieu/alu.sv | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index d880e6535..fa5df225f 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -75,6 +75,10 @@ module alu #(parameter WIDTH=32) ( endcase end else assign CondShiftA = A; + if (`ZBB_SUPPORTED) begin: rotatelogic + assign Rotate = BSelect[2] & (ALUSelect == 3'b001); //NOTE: Do we want to move this logic into the Decode Stage? + end else assign Rotate = 1'b0; + // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; @@ -83,7 +87,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts - shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(1'b0)); + shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(Rotate)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign From 5f56f72bb1877f7b715ed8058a960b0269cd7a31 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 16:26:16 -0800 Subject: [PATCH 079/231] bmuctrl handles roriw --- src/ieu/bmu/bmuctrl.sv | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 6d16036bb..816b5dc33 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -107,6 +107,11 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b001_0100; // rori (rv64) else BMUControlsD = `BMUCTRLW'b000_0000; //illegal instruction + 17'b0011011_0110000_101: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b001_0100; // roriw + else + BMUControlsD = `BMUCTRLW'b000_0000; //illegal instruction + default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift endcase From f18cd53dee23dacf64fec1f012c8b28e18aa506a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 19:44:14 -0800 Subject: [PATCH 080/231] began ZBB integration into ieu --- src/ieu/alu.sv | 7 +++- src/ieu/bmu/bmuctrl.sv | 92 ++++++++++++++++++++++-------------------- src/ieu/bmu/cnt.sv | 10 +++-- src/ieu/bmu/zbb.sv | 16 ++++---- src/ieu/controller.sv | 6 ++- src/ieu/datapath.sv | 3 +- src/ieu/ieu.sv | 7 ++-- 7 files changed, 80 insertions(+), 61 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index fa5df225f..696020593 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -34,13 +34,14 @@ module alu #(parameter WIDTH=32) ( input logic [2:0] ALUControl, // With Funct3, indicates operation to perform input logic [2:0] ALUSelect, // ALU mux select signal input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction + input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult; // Intermediate results + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult, ZBBResult; // Intermediate results logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux @@ -142,6 +143,10 @@ module alu #(parameter WIDTH=32) ( if (`ZBC_SUPPORTED) begin: zbc zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); end else assign ZBCResult = 0; + + if (`ZBB_SUPPORTED) begin: zbb + zbb #(WIDTH) ZBB(.A(A), .B(B), .W64(W64), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + end else assign ZBBResult = 0; // Final Result B instruction select mux if (`ZBC_SUPPORTED | `ZBS_SUPPORTED) begin : zbdecoder diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 816b5dc33..e7ddd14e5 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -37,18 +37,20 @@ module bmuctrl( input logic [31:0] InstrD, // Instruction in Decode stage output logic [2:0] ALUSelectD, // ALU Mux select signal output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage + output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectE, - output logic [3:0] BSelectE // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + output logic [2:0] ZBBSelectE // ZBB mux select signal ); logic [6:0] OpD; // Opcode in Decode stage logic [2:0] Funct3D; // Funct3 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage - logic [4:0] Rs1D; // Rs1 source register in Decode stage + logic [4:0] Rs2D; // Rs2 source register in Decode stage - `define BMUCTRLW 7 + `define BMUCTRLW 10 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -57,70 +59,74 @@ module bmuctrl( assign OpD = InstrD[6:0]; assign Funct3D = InstrD[14:12]; assign Funct7D = InstrD[31:25]; - assign Rs1D = InstrD[19:15]; + assign Rs2D = InstrD[24:20]; // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001; // bseti + BMUControlsD = `BMUCTRLW'b110_0001_000; // bseti else - BMUControlsD = `BMUCTRLW'b000_0000; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000; // sra, srai, srl, srli, sll, slli - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010; // ZBC instruction - 17'b0110011_0010000_?01: BMUControlsD = `BMUCTRLW'b001_1000; // slli.uw - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000; // slli.uw - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100; // rori (rv32) + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000; // sra, srai, srl, srli, sll, slli + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000; // ZBC instruction + 17'b0110011_0010000_?01: BMUControlsD = `BMUCTRLW'b001_1000_000; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000; // slli.uw + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000; //illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000; //illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0010011_0110000_001: if (Rs2D[2]) + BMUControlsD = `BMUCTRLW'b000_0100_000; // count instruction + else + BMUControlsD = `BMUCTRLW'b000_0100_100; // sign ext instruction - default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift + default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD} = BMUControlsD; // BMU Execute stage pipieline control register - flopenrc#(7) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD}, {ALUSelectE, BSelectE}); + flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD}, {ALUSelectE, BSelectE, ZBBSelectE}); endmodule \ No newline at end of file diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 430d2d382..a0bee4348 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -31,12 +31,14 @@ `include "wally-config.vh" module cnt #(parameter WIDTH = 32) ( - input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] A, B, // Operands input logic W64, // Indicates word operation - output logic [WIDTH-1:0] czResult, // count zeros result - output logic [WIDTH-1:0] cpopResult);// population count result + output logic [WIDTH-1:0] CntResult // count result +); //count instructions + logic [WIDTH-1:0] czResult; // count zeros result + logic [WIDTH-1:0] cpopResult; // population count result logic [WIDTH-1:0] lzcA, popcntA; logic [WIDTH-1:0] revA; @@ -81,4 +83,6 @@ module cnt #(parameter WIDTH = 32) ( lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult)); popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult)); + assign CntResult = (B[1]) ? cpopResult : czResult; + endmodule \ No newline at end of file diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 296d15d5b..58cfccc5c 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -32,16 +32,14 @@ module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands - input logic [2:0] Funct3, // Indicates operation to perform - input logic [6:0] Funct7, // Indicates operation to perform input logic W64, // Indicates word operation + input logic [2:0] ZBBSelect, // Indicates word operation output logic [WIDTH-1:0] ZBBResult); // ZBB result - // count results - logic [WIDTH-1:0] czResult; // count zeros result (lzc or tzc) - logic [WIDTH-1:0] cpopResult; // population count result + // count result + logic [WIDTH-1:0] CntResult; // byte results logic [WIDTH-1:0] OrcBResult; @@ -52,14 +50,14 @@ module zbb #(parameter WIDTH=32) ( logic [WIDTH-1:0] sextbResult; // sign extend byte result logic [WIDTH-1:0] zexthResult; // zero extend halfword result - cnt #(WIDTH) cnt(.A(A), .B(B), .W64(W64), .czResult(czResult), .cpopResult(cpopResult)); + cnt #(WIDTH) cnt(.A(A), .B(B), .W64(W64), .CntResult(CntResult)); byteUnit #(WIDTH) bu(.A(A), .OrcBResult(OrcBResult), .Rev8Result(Rev8Result)); ext #(WIDTH) ext(.A(A), .sexthResult(sexthResult), .sextbResult(sextbResult), .zexthResult(zexthResult)); //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin - case ({Funct7, Funct3, B[4:0]}) - 15'b0010100_101_00111: ZBBResult = OrcBResult; + case (ZBBSelect) + /*15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; 15'b0110000_001_00000: ZBBResult = czResult; @@ -67,7 +65,7 @@ module zbb #(parameter WIDTH=32) ( 15'b0110000_001_00001: ZBBResult = czResult; 15'b0000100_100_00000: ZBBResult = zexthResult; 15'b0110000_001_00100: ZBBResult = sextbResult; - 15'b0110000_001_00101: ZBBResult = sexthResult; + 15'b0110000_001_00101: ZBBResult = sexthResult;*/ default: ZBBResult = {(WIDTH){1'b0}}; endcase end diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 9c48b26ec..70d5f5987 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -56,6 +56,7 @@ module controller( output logic SCE, // Store Conditional instruction output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction + output logic [2:0] ZBBSelectE, // ZBB mux select signal in Execute stage // Memory stage control signals input logic StallM, FlushM, // Stall, flush Memory stage output logic [1:0] MemRWM, // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write @@ -117,6 +118,7 @@ module controller( logic SFenceVmaD; // sfence.vma instruction logic IntDivM; // Integer divide instruction logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage + logic [2:0] ZBBSelectD; // ZBB Mux Select Signal // Extract fields @@ -216,11 +218,13 @@ module controller( assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .StallE, .FlushE, .ALUSelectE, .BSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; assign BSelectE = 4'b0000; + assign BSelectD = 4'b0000; + assign ZBBSelectE = 3'b000; end // Fences diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index b81e43ee7..ff25309ff 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -18,6 +18,7 @@ module datapath ( input logic JumpE, // Is a jump (j) instruction input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction + input logic [2:0] ZBBSelectE, // ZBB mux select signal output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B @@ -82,7 +83,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, Funct3E, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 236178bc6..2a23dcd5a 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -82,7 +82,8 @@ module ieu ( logic SCE; // Store Conditional instruction logic FWriteIntM; // FPU writing to integer register file logic IntDivW; // Integer divide instruction - logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + logic [2:0] ZBBSelectE; // Forwarding signals logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers @@ -96,7 +97,7 @@ module ieu ( controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, - .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .BSelectE, .MemReadE, .CSRReadE, + .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .BSelectE, .ZBBSelectE, .MemReadE, .CSRReadE, .Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, @@ -105,7 +106,7 @@ module ieu ( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, - .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, + .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); From e4085764e70ad6a095e70af4acb4b96ca1796d51 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 19:50:36 -0800 Subject: [PATCH 081/231] removed redundant decode logic in bmuctrl --- src/ieu/bmu/bmuctrl.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index e7ddd14e5..0d56e3299 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -91,7 +91,6 @@ module bmuctrl( 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000; // bset 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000; // sra, srai, srl, srli, sll, slli 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000; // ZBC instruction - 17'b0110011_0010000_?01: BMUControlsD = `BMUCTRLW'b001_1000_000; // slli.uw 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh1add 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh2add 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add @@ -100,6 +99,7 @@ module bmuctrl( 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add.uw 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000; // add.uw 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000; // slli.uw + // ZBB 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111; // rol 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111; // rolw 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // ror From baff2c93626a68c2d1a9449c2de88b9381863823 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 19:56:54 -0800 Subject: [PATCH 082/231] rotate instructions now handled in ZBB unit --- src/ieu/alu.sv | 3 ++- src/ieu/bmu/zbb.sv | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 696020593..164a2810a 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -145,7 +145,7 @@ module alu #(parameter WIDTH=32) ( end else assign ZBCResult = 0; if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A(A), .B(B), .W64(W64), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(ALUResult), .W64(W64), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); end else assign ZBBResult = 0; // Final Result B instruction select mux @@ -156,6 +156,7 @@ module alu #(parameter WIDTH=32) ( 4'b0001: Result = FullResult; 4'b0010: Result = ZBCResult; 4'b1000: Result = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word. + 4'b0100: Result = ZBBResult; default: Result = ALUResult; endcase end else assign Result = ALUResult; diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 58cfccc5c..02591dd42 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -32,6 +32,7 @@ module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] ALUResult, // ALU Result input logic W64, // Indicates word operation input logic [2:0] ZBBSelect, // Indicates word operation output logic [WIDTH-1:0] ZBBResult); // ZBB result @@ -57,6 +58,7 @@ module zbb #(parameter WIDTH=32) ( //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin case (ZBBSelect) + 3'b111: ZBBResult = ALUResult; /*15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; From 446327215d7119f32d6decb2243459dfce8811ea Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 19:57:10 -0800 Subject: [PATCH 083/231] updated comments in bmuctrl --- src/ieu/bmu/bmuctrl.sv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 0d56e3299..0d3516a85 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -64,7 +64,8 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect + // ALUSelect_BSelect_ZBBSelect + // ZBS 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri (rv64) @@ -90,7 +91,9 @@ module bmuctrl( 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000; // binv 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000; // bset 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000; // sra, srai, srl, srli, sll, slli + // ZBC 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000; // ZBC instruction + // ZBA 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh1add 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh2add 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add From 543dc1e36a4f3e667fde0a8a3c122bbc028e69aa Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 20:11:50 -0800 Subject: [PATCH 084/231] fixed bmuctrl decode bug --- src/ieu/bmu/bmuctrl.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 0d3516a85..b45a13ff3 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -117,9 +117,10 @@ module bmuctrl( else BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_000; // count instruction + BMUControlsD = `BMUCTRLW'b000_0100_100; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_100; // sign ext instruction + BMUControlsD = `BMUCTRLW'b000_0100_000; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000; // count word instruction default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift endcase From ecfcad20a0f143bfae015f9870e3694cd917d252 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 20:12:17 -0800 Subject: [PATCH 085/231] zbb handles count instructions --- src/ieu/bmu/zbb.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 02591dd42..1be801f4b 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -58,7 +58,8 @@ module zbb #(parameter WIDTH=32) ( //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin case (ZBBSelect) - 3'b111: ZBBResult = ALUResult; + 3'b111: ZBBResult = ALUResult; // rotate + 3'b000: ZBBResult = CntResult; // count /*15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; From ad63699aac8434cd25d65d097de2fed4552e398d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 20:12:30 -0800 Subject: [PATCH 086/231] fixed ctlzw bug in count unit --- src/ieu/bmu/cnt.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index a0bee4348..540d5e910 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -54,7 +54,7 @@ module cnt #(parameter WIDTH = 32) ( 6'b00000_0: lzcA = A; //clz 6'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw 6'b00001_0: lzcA = revA; //ctz - 6'b00001_1: lzcA = {revA[31:0],{32{1'b1}}}; //ctzw + 6'b00001_1: lzcA = {revA[63:32],{32{1'b1}}}; //ctzw default: lzcA = A; endcase From 59e9c7c7476edfe2e16122d6a220e20a6e36507a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 20:32:40 -0800 Subject: [PATCH 087/231] added logic to handle sign/zero extend instructions --- src/ieu/bmu/bmuctrl.sv | 10 +++++++++- src/ieu/bmu/ext.sv | 16 ++++++++++++---- src/ieu/bmu/zbb.sv | 7 +++---- 3 files changed, 24 insertions(+), 9 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index b45a13ff3..ef021db0e 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -121,8 +121,16 @@ module bmuctrl( else BMUControlsD = `BMUCTRLW'b000_0100_000; // count instruction 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000; // count word instruction + 17'b0111011_0000100_100: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b000_0100_100; // zexth (rv64) + else + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0110011_0000100_100: if (`XLEN == 32) + BMUControlsD = `BMUCTRLW'b000_0100_100; // zexth (rv32) + else + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift + default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift endcase // Unpack Control Signals diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index c9f845e76..05cb24c01 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -31,13 +31,21 @@ `include "wally-config.vh" module ext #(parameter WIDTH = 32) ( - input logic [WIDTH-1:0] A, // Operand - output logic [WIDTH-1:0] sexthResult, // sign extend halfword result - output logic [WIDTH-1:0] sextbResult, // sign extend byte result - output logic [WIDTH-1:0] zexthResult); // zero extend halfword result + input logic [WIDTH-1:0] A, B, // Operands + output logic [WIDTH-1:0] ExtResult); // Extend Result + logic [WIDTH-1:0] sexthResult, zexthResult, sextbResult; assign sexthResult = {{(WIDTH-16){A[15]}},A[15:0]}; assign zexthResult = {{(WIDTH-16){1'b0}},A[15:0]}; assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]}; + + always_comb + case({B[2],B[0]}) + 2'b00: ExtResult = zexthResult; + 2'b10: ExtResult = sextbResult; + 2'b11: ExtResult = sexthResult; + default: ExtResult = 0; + endcase + endmodule \ No newline at end of file diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 1be801f4b..d5198d484 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -47,19 +47,18 @@ module zbb #(parameter WIDTH=32) ( logic [WIDTH-1:0] Rev8Result; // sign/zero extend results - logic [WIDTH-1:0] sexthResult; // sign extend halfword result - logic [WIDTH-1:0] sextbResult; // sign extend byte result - logic [WIDTH-1:0] zexthResult; // zero extend halfword result + logic [WIDTH-1:0] ExtResult; // sign/zero extend result cnt #(WIDTH) cnt(.A(A), .B(B), .W64(W64), .CntResult(CntResult)); byteUnit #(WIDTH) bu(.A(A), .OrcBResult(OrcBResult), .Rev8Result(Rev8Result)); - ext #(WIDTH) ext(.A(A), .sexthResult(sexthResult), .sextbResult(sextbResult), .zexthResult(zexthResult)); + ext #(WIDTH) ext(.A(A), .B(B), .ExtResult(ExtResult)); //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin case (ZBBSelect) 3'b111: ZBBResult = ALUResult; // rotate 3'b000: ZBBResult = CntResult; // count + 3'b100: ZBBResult = ExtResult; // sign/zero extend /*15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; From e7339902ae18cf5831e7b52cd3a78d85ad7026d2 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 20:57:07 -0800 Subject: [PATCH 088/231] alu and controllers handle andn, orn, xnor --- src/ieu/alu.sv | 4 ++-- src/ieu/bmu/bmuctrl.sv | 3 +++ src/ieu/bmu/zbb.sv | 2 +- src/ieu/controller.sv | 14 +++++++++++++- 4 files changed, 19 insertions(+), 4 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 164a2810a..97400f447 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -113,8 +113,8 @@ module alu #(parameter WIDTH=32) ( 3'b001: FullResult = Shift; // sll, sra, or srl 3'b010: FullResult = SLT; // slt 3'b011: FullResult = SLTU; // sltu - 3'b100: FullResult = A ^ CondMaskB; // xor, binv - 3'b110: FullResult = A | CondMaskB; // or, bset + 3'b100: FullResult = A ^ CondInvB; // xor, xnor, binv + 3'b110: FullResult = A | CondInvB; // or, orn, bset 3'b111: FullResult = A & CondInvB; // and, bclr 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}};// bext endcase diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index ef021db0e..abaf36558 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -129,6 +129,9 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b000_0100_100; // zexth (rv32) else BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111; // xnor default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift endcase diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index d5198d484..bacbef817 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -56,7 +56,7 @@ module zbb #(parameter WIDTH=32) ( //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin case (ZBBSelect) - 3'b111: ZBBResult = ALUResult; // rotate + 3'b111: ZBBResult = ALUResult; // rotates, andn, xnor, orn 3'b000: ZBBResult = CntResult; // count 3'b100: ZBBResult = ExtResult; // sign/zero extend /*15'b0010100_101_00111: ZBBResult = OrcBResult; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 70d5f5987..74d0e4f1e 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -107,6 +107,7 @@ module controller( logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions logic bclrD, bextD; // Indicates if is one of these instructions + logic andnD, ornD, xnorD; // Indicates if is one of these instructions logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; @@ -210,11 +211,22 @@ module controller( assign bclrD = 1'b0; assign bextD = 1'b0; end + + if (`ZBB_SUPPORTED) begin + assign andnD = (ALUSelectD == 3'b111 & BSelectD[2]); + assign ornD = (ALUSelectD == 3'b110 & BSelectD[2]); + assign xnorD = (ALUSelectD == 3'b100 & BSelectD[2]); + end else begin + assign andnD = 0; + assign ornD = 0; + assign xnorD = 0; + end + // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD))); // TRUE for R-type subtracts and sra, slt, sltu + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags From 2319661b101e618bab8e6c0ed89fe031b698a3db Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 18 Feb 2023 21:06:55 -0800 Subject: [PATCH 089/231] controlleres and zbb handle byte instructions --- src/ieu/bmu/bmuctrl.sv | 9 +++++++++ src/ieu/bmu/byte.sv | 8 +++++--- src/ieu/bmu/zbb.sv | 6 +++--- 3 files changed, 17 insertions(+), 6 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index abaf36558..ab275047b 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -132,6 +132,15 @@ module bmuctrl( 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111; // andn 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111; // orn 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111; // xnor + 17'b0010011_0110101_101: if (`XLEN == 64) + BMUControlsD = `BMUCTRLW'b000_0100_011; // rev8 (rv64) + else + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0010011_0110100_101: if (`XLEN == 32) + BMUControlsD = `BMUCTRLW'b000_0100_011; // rev8 (rv32) + else + BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011; // orc.b default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift endcase diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index 6a076b7dc..efd43d846 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -30,10 +30,10 @@ `include "wally-config.vh" module byteUnit #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, // Operands - output logic [WIDTH-1:0] OrcBResult, // OrcB result - output logic [WIDTH-1:0] Rev8Result); // Rev8 result + input logic [WIDTH-1:0] A, B, // Operands + output logic [WIDTH-1:0] ByteResult); // rev8, orcb result + logic [WIDTH-1:0] OrcBResult, Rev8Result; genvar i; for (i=0;i Date: Sat, 18 Feb 2023 22:12:55 -0800 Subject: [PATCH 090/231] B DONE (for now) - datapath passes along comparator flag to alu - controllers and zbb handle min/max instructions --- src/ieu/alu.sv | 3 ++- src/ieu/bmu/bmuctrl.sv | 4 ++++ src/ieu/bmu/zbb.sv | 11 +++++++++++ src/ieu/controller.sv | 13 ++++++++++++- src/ieu/datapath.sv | 2 +- 5 files changed, 30 insertions(+), 3 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 97400f447..0e7487eb7 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -36,6 +36,7 @@ module alu #(parameter WIDTH=32) ( input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect + input logic [1:0] CompFlags, // Comparator flags output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands @@ -145,7 +146,7 @@ module alu #(parameter WIDTH=32) ( end else assign ZBCResult = 0; if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(ALUResult), .W64(W64), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(ALUResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); end else assign ZBBResult = 0; // Final Result B instruction select mux diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index ab275047b..097ee27e8 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -141,6 +141,10 @@ module bmuctrl( else BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110; // minu default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift endcase diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 2342fe0c9..3289d13a4 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -34,6 +34,7 @@ module zbb #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [WIDTH-1:0] ALUResult, // ALU Result input logic W64, // Indicates word operation + input logic lt, // lt flag input logic [2:0] ZBBSelect, // Indicates word operation output logic [WIDTH-1:0] ZBBResult); // ZBB result @@ -41,6 +42,10 @@ module zbb #(parameter WIDTH=32) ( // count result logic [WIDTH-1:0] CntResult; + + // min,max result + logic [WIDTH-1:0] MaxResult; + logic [WIDTH-1:0] MinResult; // byte results logic [WIDTH-1:0] ByteResult; @@ -52,6 +57,10 @@ module zbb #(parameter WIDTH=32) ( byteUnit #(WIDTH) bu(.A(A), .B(B), .ByteResult(ByteResult)); ext #(WIDTH) ext(.A(A), .B(B), .ExtResult(ExtResult)); + + assign MaxResult = (lt) ? B : A; + assign MinResult = (lt) ? A : B; + //can replace with structural mux by looking at bit 4 in rs2 field always_comb begin case (ZBBSelect) @@ -59,6 +68,8 @@ module zbb #(parameter WIDTH=32) ( 3'b000: ZBBResult = CntResult; // count 3'b100: ZBBResult = ExtResult; // sign/zero extend 3'b011: ZBBResult = ByteResult; // byte instructions + 3'b110: ZBBResult = MinResult; // min, minu + 3'b101: ZBBResult = MaxResult; // max, maxu /*15'b0010100_101_00111: ZBBResult = OrcBResult; 15'b0110100_101_11000: ZBBResult = Rev8Result; 15'b0110101_101_11000: ZBBResult = Rev8Result; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 74d0e4f1e..d6e0c191a 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -108,6 +108,7 @@ module controller( logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions logic bclrD, bextD; // Indicates if is one of these instructions logic andnD, ornD, xnorD; // Indicates if is one of these instructions + logic maxE, maxuE, minE, minuE; // Indicates if is one of these instructions in Execute Stage logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; @@ -216,10 +217,19 @@ module controller( assign andnD = (ALUSelectD == 3'b111 & BSelectD[2]); assign ornD = (ALUSelectD == 3'b110 & BSelectD[2]); assign xnorD = (ALUSelectD == 3'b100 & BSelectD[2]); + // we only need these signals if we want to calculate a signedD flag in decode stage to pass to the comparator. + assign maxE = (Funct3E[1:0] == 2'b10 & BSelectE[2]); + assign maxuE = (Funct3E[1:0] == 2'b11 & BSelectE[2]); + assign minE = (Funct3E[1:0] == 2'b00 & BSelectE[2]); + assign minuE = (Funct3E[1:0] == 2'b01 & BSelectE[2]); end else begin assign andnD = 0; assign ornD = 0; assign xnorD = 0; + assign maxE = 0; + assign maxuE = 0; + assign minE = 0; + assign minuE = 0; end // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra @@ -263,7 +273,8 @@ module controller( // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE // Hence, only eq and lt flags are needed - assign BranchSignedE = ~(Funct3E[2:1] == 2'b11); + assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & ~BSelectE[2]) | (`ZBB_SUPPORTED & (maxE | minE)) ; + //assign BranchSignedE = ~(Funct3E[2:1] == 2'b11); assign {eqE, ltE} = FlagsE; mux2 #(1) branchflagmux(eqE, ltE, Funct3E[2], BranchFlagE); assign BranchTakenE = BranchFlagE ^ Funct3E[0]; diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index ff25309ff..d0f6f0397 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -83,7 +83,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); From 9d9de8f8dd2aeeefc18c873579fde867c859c094 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 20 Feb 2023 14:39:34 -0800 Subject: [PATCH 091/231] added arch32b tests (giving errors in sim however) --- config/rv32i/wally-config.vh | 8 +- testbench/testbench.sv | 1 + testbench/tests.vh | 251 ++++++++++++++++++++++++++++++----- 3 files changed, 223 insertions(+), 37 deletions(-) diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh index d400cebe9..f377468f4 100644 --- a/config/rv32i/wally-config.vh +++ b/config/rv32i/wally-config.vh @@ -144,10 +144,10 @@ `define DIVCOPIES 32'h4 // bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 +`define ZBA_SUPPORTED 1 +`define ZBB_SUPPORTED 1 +`define ZBC_SUPPORTED 1 +`define ZBS_SUPPORTED 1 // Memory synthesis configuration `define USE_SRAM 0 diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 681d6bb9a..463ab0c46 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -131,6 +131,7 @@ logic [3:0] dummy; "embench": tests = embench; "coremark": tests = coremark; "arch32ba": if (`ZBA_SUPPORTED) tests = arch32ba; + "arch32b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch32b; endcase end if (tests.size() == 0) begin diff --git a/testbench/tests.vh b/testbench/tests.vh index 5bf239ade..311a07415 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1326,10 +1326,103 @@ string imperas32f[] = '{ "rv64i_m/D/src/fssub.d_b8-01.S" }; + string arch64b[] = '{ `RISCVARCHTEST, - "rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/max-01.S", + "rv64i_m/B/src/maxu-01.S", + "rv64i_m/B/src/min-01.S", + "rv64i_m/B/src/minu-01.S", + "rv64i_m/B/src/orcb_64-01.S", + "rv64i_m/B/src/rev8-01.S", "rv64i_m/B/src/andn-01.S", + "rv64i_m/B/src/orn-01.S", + "rv64i_m/B/src/xnor-01.S", + "rv64i_m/B/src/zext.h-01.S", + "rv64i_m/B/src/sext.b-01.S", + "rv64i_m/B/src/sext.h-01.S", + "rv64i_m/B/src/clz-01.S", + "rv64i_m/B/src/clzw-01.S", + "rv64i_m/B/src/cpop-01.S", + "rv64i_m/B/src/cpopw-01.S", + "rv64i_m/B/src/ctz-01.S", + "rv64i_m/B/src/ctzw-01.S", + "rv64i_m/B/src/rolw-01.S", + "rv64i_m/B/src/ror-01.S", + "rv64i_m/B/src/rori-01.S", + "rv64i_m/B/src/roriw-01.S", + "rv64i_m/B/src/rorw-01.S", + "rv64i_m/B/src/rol-01.S", + "rv64i_m/B/src/slli.uw-01.S", + "rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/sh1add-01.S", + "rv64i_m/B/src/sh2add-01.S", + "rv64i_m/B/src/sh3add-01.S", + "rv64i_m/B/src/sh1add.uw-01.S", + "rv64i_m/B/src/sh2add.uw-01.S", + "rv64i_m/B/src/sh3add.uw-01.S", + "rv64i_m/I/src/add-01.S", + "rv64i_m/I/src/addi-01.S", + "rv64i_m/I/src/addiw-01.S", + "rv64i_m/I/src/addw-01.S", + "rv64i_m/I/src/and-01.S", + "rv64i_m/I/src/andi-01.S", + "rv64i_m/I/src/auipc-01.S", + "rv64i_m/I/src/beq-01.S", + "rv64i_m/I/src/bge-01.S", + "rv64i_m/I/src/bgeu-01.S", + "rv64i_m/I/src/blt-01.S", + "rv64i_m/I/src/bltu-01.S", + "rv64i_m/I/src/bne-01.S", + "rv64i_m/I/src/fence-01.S", + "rv64i_m/I/src/jal-01.S", + "rv64i_m/I/src/jalr-01.S", + "rv64i_m/I/src/lb-align-01.S", + "rv64i_m/I/src/lbu-align-01.S", + "rv64i_m/I/src/ld-align-01.S", + "rv64i_m/I/src/lh-align-01.S", + "rv64i_m/I/src/lhu-align-01.S", + "rv64i_m/I/src/lui-01.S", + "rv64i_m/I/src/lw-align-01.S", + "rv64i_m/I/src/lwu-align-01.S", + "rv64i_m/I/src/or-01.S", + "rv64i_m/I/src/ori-01.S", + "rv64i_m/I/src/sb-align-01.S", + "rv64i_m/I/src/sd-align-01.S", + "rv64i_m/I/src/sh-align-01.S", + "rv64i_m/I/src/sll-01.S", + "rv64i_m/I/src/slli-01.S", + "rv64i_m/I/src/slliw-01.S", + "rv64i_m/I/src/sllw-01.S", + "rv64i_m/I/src/slt-01.S", + "rv64i_m/I/src/slti-01.S", + "rv64i_m/I/src/sltiu-01.S", + "rv64i_m/I/src/sltu-01.S", + "rv64i_m/I/src/sra-01.S", + "rv64i_m/I/src/srai-01.S", + "rv64i_m/I/src/sraiw-01.S", + "rv64i_m/I/src/sraw-01.S", + "rv64i_m/I/src/srl-01.S", + "rv64i_m/I/src/srli-01.S", + "rv64i_m/I/src/srliw-01.S", + "rv64i_m/I/src/srlw-01.S", + "rv64i_m/I/src/sub-01.S", + "rv64i_m/I/src/subw-01.S", + "rv64i_m/I/src/sw-align-01.S", + "rv64i_m/I/src/xor-01.S", + "rv64i_m/I/src/xori-01.S", + "rv64i_m/B/src/clmul-01.S", + "rv64i_m/B/src/clmulh-01.S", + "rv64i_m/B/src/clmulr-01.S", + "rv64i_m/B/src/bclr-01.S", + "rv64i_m/B/src/bclri-01.S", + "rv64i_m/B/src/bext-01.S", + "rv64i_m/B/src/bexti-01.S", + "rv64i_m/B/src/binv-01.S", + "rv64i_m/B/src/binvi-01.S", + "rv64i_m/B/src/bset-01.S", + "rv64i_m/B/src/bseti-01.S" + /*"rv64i_m/B/src/add.uw-01.S", "rv64i_m/B/src/bclr-01.S", "rv64i_m/B/src/bclri-01.S", "rv64i_m/B/src/bext-01.S", @@ -1339,39 +1432,131 @@ string arch64b[] = '{ "rv64i_m/B/src/bset-01.S", "rv64i_m/B/src/bseti-01.S", "rv64i_m/B/src/clmul-01.S", - "rv64i_m/B/src/clmulh-01.S", - "rv64i_m/B/src/clmulr-01.S", - "rv64i_m/B/src/clz-01.S", - "rv64i_m/B/src/clzw-01.S", - "rv64i_m/B/src/cpop-01.S", - "rv64i_m/B/src/cpopw-01.S", - "rv64i_m/B/src/ctz-01.S", - "rv64i_m/B/src/ctzw-01.S", - "rv64i_m/B/src/max-01.S", - "rv64i_m/B/src/maxu-01.S", - "rv64i_m/B/src/min-01.S", - "rv64i_m/B/src/minu-01.S", - "rv64i_m/B/src/orcb_64-01.S", - "rv64i_m/B/src/orn-01.S", - "rv64i_m/B/src/rev8-01.S", + + + "rv64i_m/B/src/rol-01.S", - "rv64i_m/B/src/rolw-01.S", - "rv64i_m/B/src/ror-01.S", - "rv64i_m/B/src/rori-01.S", - "rv64i_m/B/src/roriw-01.S", - "rv64i_m/B/src/rorw-01.S", - "rv64i_m/B/src/sext.b-01.S", - "rv64i_m/B/src/sext.h-01.S", - "rv64i_m/B/src/sh1add-01.S", - "rv64i_m/B/src/sh1add.uw-01.S", - "rv64i_m/B/src/sh2add-01.S", - "rv64i_m/B/src/sh2add.uw-01.S", - "rv64i_m/B/src/sh3add-01.S", - "rv64i_m/B/src/sh3add.uw-01.S", - "rv64i_m/B/src/slli.uw-01.S", - "rv64i_m/B/src/xnor-01.S", - "rv64i_m/B/src/zext.h-01.S", - "rv64i_m/B/src/zext.h_64-01.S" + + + + + */ +}; + +string arch32b[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/max-01.S", + "rv32i_m/B/src/maxu-01.S", + "rv32i_m/B/src/min-01.S", + "rv32i_m/B/src/minu-01.S", + "rv32i_m/B/src/orcb_64-01.S", + "rv32i_m/B/src/rev8-01.S", + "rv32i_m/B/src/andn-01.S", + "rv32i_m/B/src/orn-01.S", + "rv32i_m/B/src/xnor-01.S", + "rv32i_m/B/src/zext.h-01.S", + "rv32i_m/B/src/sext.b-01.S", + "rv32i_m/B/src/sext.h-01.S", + "rv32i_m/B/src/clz-01.S", + "rv32i_m/B/src/clzw-01.S", + "rv32i_m/B/src/cpop-01.S", + "rv32i_m/B/src/cpopw-01.S", + "rv32i_m/B/src/ctz-01.S", + "rv32i_m/B/src/ctzw-01.S", + "rv32i_m/B/src/rolw-01.S", + "rv32i_m/B/src/ror-01.S", + "rv32i_m/B/src/rori-01.S", + "rv32i_m/B/src/roriw-01.S", + "rv32i_m/B/src/rorw-01.S", + "rv32i_m/B/src/rol-01.S", + "rv32i_m/B/src/slli.uw-01.S", + "rv32i_m/B/src/add.uw-01.S", + "rv32i_m/B/src/sh1add-01.S", + "rv32i_m/B/src/sh2add-01.S", + "rv32i_m/B/src/sh3add-01.S", + "rv32i_m/B/src/sh1add.uw-01.S", + "rv32i_m/B/src/sh2add.uw-01.S", + "rv32i_m/B/src/sh3add.uw-01.S", + "rv32i_m/I/src/add-01.S", + "rv32i_m/I/src/addi-01.S", + "rv32i_m/I/src/addiw-01.S", + "rv32i_m/I/src/addw-01.S", + "rv32i_m/I/src/and-01.S", + "rv32i_m/I/src/andi-01.S", + "rv32i_m/I/src/auipc-01.S", + "rv32i_m/I/src/beq-01.S", + "rv32i_m/I/src/bge-01.S", + "rv32i_m/I/src/bgeu-01.S", + "rv32i_m/I/src/blt-01.S", + "rv32i_m/I/src/bltu-01.S", + "rv32i_m/I/src/bne-01.S", + "rv32i_m/I/src/fence-01.S", + "rv32i_m/I/src/jal-01.S", + "rv32i_m/I/src/jalr-01.S", + "rv32i_m/I/src/lb-align-01.S", + "rv32i_m/I/src/lbu-align-01.S", + "rv32i_m/I/src/ld-align-01.S", + "rv32i_m/I/src/lh-align-01.S", + "rv32i_m/I/src/lhu-align-01.S", + "rv32i_m/I/src/lui-01.S", + "rv32i_m/I/src/lw-align-01.S", + "rv32i_m/I/src/lwu-align-01.S", + "rv32i_m/I/src/or-01.S", + "rv32i_m/I/src/ori-01.S", + "rv32i_m/I/src/sb-align-01.S", + "rv32i_m/I/src/sd-align-01.S", + "rv32i_m/I/src/sh-align-01.S", + "rv32i_m/I/src/sll-01.S", + "rv32i_m/I/src/slli-01.S", + "rv32i_m/I/src/slliw-01.S", + "rv32i_m/I/src/sllw-01.S", + "rv32i_m/I/src/slt-01.S", + "rv32i_m/I/src/slti-01.S", + "rv32i_m/I/src/sltiu-01.S", + "rv32i_m/I/src/sltu-01.S", + "rv32i_m/I/src/sra-01.S", + "rv32i_m/I/src/srai-01.S", + "rv32i_m/I/src/sraiw-01.S", + "rv32i_m/I/src/sraw-01.S", + "rv32i_m/I/src/srl-01.S", + "rv32i_m/I/src/srli-01.S", + "rv32i_m/I/src/srliw-01.S", + "rv32i_m/I/src/srlw-01.S", + "rv32i_m/I/src/sub-01.S", + "rv32i_m/I/src/subw-01.S", + "rv32i_m/I/src/sw-align-01.S", + "rv32i_m/I/src/xor-01.S", + "rv32i_m/I/src/xori-01.S", + "rv32i_m/B/src/clmul-01.S", + "rv32i_m/B/src/clmulh-01.S", + "rv32i_m/B/src/clmulr-01.S", + "rv32i_m/B/src/bclr-01.S", + "rv32i_m/B/src/bclri-01.S", + "rv32i_m/B/src/bext-01.S", + "rv32i_m/B/src/bexti-01.S", + "rv32i_m/B/src/binv-01.S", + "rv32i_m/B/src/binvi-01.S", + "rv32i_m/B/src/bset-01.S", + "rv32i_m/B/src/bseti-01.S" + /*"rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/bclr-01.S", + "rv64i_m/B/src/bclri-01.S", + "rv64i_m/B/src/bext-01.S", + "rv64i_m/B/src/bexti-01.S", + "rv64i_m/B/src/binv-01.S", + "rv64i_m/B/src/binvi-01.S", + "rv64i_m/B/src/bset-01.S", + "rv64i_m/B/src/bseti-01.S", + "rv64i_m/B/src/clmul-01.S", + + + + "rv64i_m/B/src/rol-01.S", + + + + + */ }; string arch32priv[] = '{ `RISCVARCHTEST, From e5bdb457981b431f63ddd6cdb11ed604fb575ec8 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 20 Feb 2023 18:05:37 -0800 Subject: [PATCH 092/231] removed incompatible rv32 tests out of arch32b tests list --- testbench/tests.vh | 54 ++++++++++++++-------------------------------- 1 file changed, 16 insertions(+), 38 deletions(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 311a07415..f894d58f8 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1445,42 +1445,40 @@ string arch64b[] = '{ string arch32b[] = '{ `RISCVARCHTEST, + "rv32i_m/B/src/clmul-01.S", + "rv32i_m/B/src/clmulh-01.S", + "rv32i_m/B/src/clmulr-01.S", + "rv32i_m/B/src/bclr-01.S", + "rv32i_m/B/src/bclri-01.S", + "rv32i_m/B/src/bext-01.S", + "rv32i_m/B/src/bexti-01.S", + "rv32i_m/B/src/binv-01.S", + "rv32i_m/B/src/binvi-01.S", + "rv32i_m/B/src/bset-01.S", + "rv32i_m/B/src/bseti-01.S", "rv32i_m/B/src/max-01.S", "rv32i_m/B/src/maxu-01.S", "rv32i_m/B/src/min-01.S", "rv32i_m/B/src/minu-01.S", - "rv32i_m/B/src/orcb_64-01.S", - "rv32i_m/B/src/rev8-01.S", + "rv32i_m/B/src/orcb_32-01.S", + "rv32i_m/B/src/rev8_32-01.S", "rv32i_m/B/src/andn-01.S", "rv32i_m/B/src/orn-01.S", "rv32i_m/B/src/xnor-01.S", - "rv32i_m/B/src/zext.h-01.S", + "rv32i_m/B/src/zext.h_32-01.S", "rv32i_m/B/src/sext.b-01.S", "rv32i_m/B/src/sext.h-01.S", "rv32i_m/B/src/clz-01.S", - "rv32i_m/B/src/clzw-01.S", "rv32i_m/B/src/cpop-01.S", - "rv32i_m/B/src/cpopw-01.S", "rv32i_m/B/src/ctz-01.S", - "rv32i_m/B/src/ctzw-01.S", - "rv32i_m/B/src/rolw-01.S", "rv32i_m/B/src/ror-01.S", "rv32i_m/B/src/rori-01.S", - "rv32i_m/B/src/roriw-01.S", - "rv32i_m/B/src/rorw-01.S", "rv32i_m/B/src/rol-01.S", - "rv32i_m/B/src/slli.uw-01.S", - "rv32i_m/B/src/add.uw-01.S", "rv32i_m/B/src/sh1add-01.S", "rv32i_m/B/src/sh2add-01.S", "rv32i_m/B/src/sh3add-01.S", - "rv32i_m/B/src/sh1add.uw-01.S", - "rv32i_m/B/src/sh2add.uw-01.S", - "rv32i_m/B/src/sh3add.uw-01.S", "rv32i_m/I/src/add-01.S", "rv32i_m/I/src/addi-01.S", - "rv32i_m/I/src/addiw-01.S", - "rv32i_m/I/src/addw-01.S", "rv32i_m/I/src/and-01.S", "rv32i_m/I/src/andi-01.S", "rv32i_m/I/src/auipc-01.S", @@ -1495,49 +1493,29 @@ string arch32b[] = '{ "rv32i_m/I/src/jalr-01.S", "rv32i_m/I/src/lb-align-01.S", "rv32i_m/I/src/lbu-align-01.S", - "rv32i_m/I/src/ld-align-01.S", "rv32i_m/I/src/lh-align-01.S", "rv32i_m/I/src/lhu-align-01.S", "rv32i_m/I/src/lui-01.S", "rv32i_m/I/src/lw-align-01.S", - "rv32i_m/I/src/lwu-align-01.S", "rv32i_m/I/src/or-01.S", "rv32i_m/I/src/ori-01.S", "rv32i_m/I/src/sb-align-01.S", - "rv32i_m/I/src/sd-align-01.S", "rv32i_m/I/src/sh-align-01.S", "rv32i_m/I/src/sll-01.S", "rv32i_m/I/src/slli-01.S", - "rv32i_m/I/src/slliw-01.S", - "rv32i_m/I/src/sllw-01.S", "rv32i_m/I/src/slt-01.S", "rv32i_m/I/src/slti-01.S", "rv32i_m/I/src/sltiu-01.S", "rv32i_m/I/src/sltu-01.S", "rv32i_m/I/src/sra-01.S", "rv32i_m/I/src/srai-01.S", - "rv32i_m/I/src/sraiw-01.S", - "rv32i_m/I/src/sraw-01.S", "rv32i_m/I/src/srl-01.S", "rv32i_m/I/src/srli-01.S", - "rv32i_m/I/src/srliw-01.S", - "rv32i_m/I/src/srlw-01.S", "rv32i_m/I/src/sub-01.S", - "rv32i_m/I/src/subw-01.S", "rv32i_m/I/src/sw-align-01.S", "rv32i_m/I/src/xor-01.S", - "rv32i_m/I/src/xori-01.S", - "rv32i_m/B/src/clmul-01.S", - "rv32i_m/B/src/clmulh-01.S", - "rv32i_m/B/src/clmulr-01.S", - "rv32i_m/B/src/bclr-01.S", - "rv32i_m/B/src/bclri-01.S", - "rv32i_m/B/src/bext-01.S", - "rv32i_m/B/src/bexti-01.S", - "rv32i_m/B/src/binv-01.S", - "rv32i_m/B/src/binvi-01.S", - "rv32i_m/B/src/bset-01.S", - "rv32i_m/B/src/bseti-01.S" + "rv32i_m/I/src/xori-01.S" + /*"rv64i_m/B/src/add.uw-01.S", "rv64i_m/B/src/bclr-01.S", "rv64i_m/B/src/bclri-01.S", From 35bd4f72196ca4602dcc0a7dd692dff0d1cad7ad Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 21 Feb 2023 11:52:05 -0800 Subject: [PATCH 093/231] added individual zb tests in tests.vh and testbench - also minor alu/controller configurability changes --- src/ieu/alu.sv | 4 +- src/ieu/controller.sv | 2 +- testbench/testbench.sv | 9 +- testbench/tests.vh | 285 +++++++++++++++++++++++++---------------- 4 files changed, 186 insertions(+), 114 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 0e7487eb7..b6e8d0b42 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -106,7 +106,7 @@ module alu #(parameter WIDTH=32) ( assign SLTU = {{(WIDTH-1){1'b0}}, LTU}; // Select appropriate ALU Result - if (`ZBS_SUPPORTED) begin + if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) begin always_comb if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect @@ -150,7 +150,7 @@ module alu #(parameter WIDTH=32) ( end else assign ZBBResult = 0; // Final Result B instruction select mux - if (`ZBC_SUPPORTED | `ZBS_SUPPORTED) begin : zbdecoder + if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : zbdecoder always_comb case (BSelect) //ZBA_ZBB_ZBC_ZBS diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index d6e0c191a..ff5bafa69 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -239,7 +239,7 @@ module controller( assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand assign ALUControlD = {W64D, SubArithD, ALUOpD}; - if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags + if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 463ab0c46..9126f09cf 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -105,6 +105,10 @@ logic [3:0] dummy; "coremark": tests = coremark; "fpga": tests = fpga; "ahb" : tests = ahb; + "arch64zba": if (`ZBA_SUPPORTED) tests = arch64zba; + "arch64zbb": if (`ZBB_SUPPORTED) tests = arch64zbb; + "arch64zbc": if (`ZBC_SUPPORTED) tests = arch64zbc; + "arch64zbs": if (`ZBS_SUPPORTED) tests = arch64zbs; "arch64b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch64b; endcase end else begin // RV32 @@ -130,7 +134,10 @@ logic [3:0] dummy; "wally32periph": tests = wally32periph; "embench": tests = embench; "coremark": tests = coremark; - "arch32ba": if (`ZBA_SUPPORTED) tests = arch32ba; + "arch32zba": if (`ZBA_SUPPORTED) tests = arch32zba; + "arch32zbb": if (`ZBB_SUPPORTED) tests = arch32zbb; + "arch32zbc": if (`ZBC_SUPPORTED) tests = arch32zbc; + "arch32zbs": if (`ZBS_SUPPORTED) tests = arch32zbs; "arch32b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch32b; endcase end diff --git a/testbench/tests.vh b/testbench/tests.vh index f894d58f8..631775ae5 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -836,17 +836,17 @@ string imperas32f[] = '{ }; - string wally64a[] = '{ + string wally64a[] = '{ `WALLYTEST, "rv64i_m/privilege/src/WALLY-amo-01.S", "rv64i_m/privilege/src/WALLY-lrsc-01.S" }; - string wally32a[] = '{ + string wally32a[] = '{ `WALLYTEST, "rv32i_m/privilege/src/WALLY-amo-01.S", "rv32i_m/privilege/src/WALLY-lrsc-01.S" - }; + }; string arch64priv[] = '{ `RISCVARCHTEST, @@ -881,14 +881,128 @@ string imperas32f[] = '{ "rv32i_m/Zifencei/src/Fencei.S" }; - string arch32ba[] = '{ + string arch32zba[] = '{ `RISCVARCHTEST, - // *** unclear why add.uw isn't in the list "rv32i_m/B/src/sh1add-01.S", - "rv32i_m/B/src/sh1add-02.S", - "rv32i_m/B/src/sh1add-013.S" + "rv32i_m/B/src/sh2add-01.S", + "rv32i_m/B/src/sh3add-01.S" }; + string arch32zbb[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/max-01.S", + "rv32i_m/B/src/maxu-01.S", + "rv32i_m/B/src/min-01.S", + "rv32i_m/B/src/minu-01.S", + "rv32i_m/B/src/orcb_32-01.S", + "rv32i_m/B/src/rev8_32-01.S", + "rv32i_m/B/src/andn-01.S", + "rv32i_m/B/src/orn-01.S", + "rv32i_m/B/src/xnor-01.S", + "rv32i_m/B/src/zext.h_32-01.S", + "rv32i_m/B/src/sext.b-01.S", + "rv32i_m/B/src/sext.h-01.S", + "rv32i_m/B/src/clz-01.S", + "rv32i_m/B/src/cpop-01.S", + "rv32i_m/B/src/ctz-01.S", + "rv32i_m/B/src/ror-01.S", + "rv32i_m/B/src/rori-01.S", + "rv32i_m/B/src/rol-01.S" + }; + + string arch32zbc[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/clmul-01.S", + "rv32i_m/B/src/clmulh-01.S", + "rv32i_m/B/src/clmulr-01.S" + }; + + string arch32zbs[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/bclr-01.S", + "rv32i_m/B/src/bclri-01.S", + "rv32i_m/B/src/bext-01.S", + "rv32i_m/B/src/bexti-01.S", + "rv32i_m/B/src/binv-01.S", + "rv32i_m/B/src/binvi-01.S", + "rv32i_m/B/src/bset-01.S", + "rv32i_m/B/src/bseti-01.S" + }; + + string arch32b[] = '{ + `RISCVARCHTEST, + "rv32i_m/B/src/clmul-01.S", + "rv32i_m/B/src/clmulh-01.S", + "rv32i_m/B/src/clmulr-01.S", + "rv32i_m/B/src/bclr-01.S", + "rv32i_m/B/src/bclri-01.S", + "rv32i_m/B/src/bext-01.S", + "rv32i_m/B/src/bexti-01.S", + "rv32i_m/B/src/binv-01.S", + "rv32i_m/B/src/binvi-01.S", + "rv32i_m/B/src/bset-01.S", + "rv32i_m/B/src/bseti-01.S", + "rv32i_m/B/src/max-01.S", + "rv32i_m/B/src/maxu-01.S", + "rv32i_m/B/src/min-01.S", + "rv32i_m/B/src/minu-01.S", + "rv32i_m/B/src/orcb_32-01.S", + "rv32i_m/B/src/rev8_32-01.S", + "rv32i_m/B/src/andn-01.S", + "rv32i_m/B/src/orn-01.S", + "rv32i_m/B/src/xnor-01.S", + "rv32i_m/B/src/zext.h_32-01.S", + "rv32i_m/B/src/sext.b-01.S", + "rv32i_m/B/src/sext.h-01.S", + "rv32i_m/B/src/clz-01.S", + "rv32i_m/B/src/cpop-01.S", + "rv32i_m/B/src/ctz-01.S", + "rv32i_m/B/src/ror-01.S", + "rv32i_m/B/src/rori-01.S", + "rv32i_m/B/src/rol-01.S", + "rv32i_m/B/src/sh1add-01.S", + "rv32i_m/B/src/sh2add-01.S", + "rv32i_m/B/src/sh3add-01.S", + "rv32i_m/I/src/add-01.S", + "rv32i_m/I/src/addi-01.S", + "rv32i_m/I/src/and-01.S", + "rv32i_m/I/src/andi-01.S", + "rv32i_m/I/src/auipc-01.S", + "rv32i_m/I/src/beq-01.S", + "rv32i_m/I/src/bge-01.S", + "rv32i_m/I/src/bgeu-01.S", + "rv32i_m/I/src/blt-01.S", + "rv32i_m/I/src/bltu-01.S", + "rv32i_m/I/src/bne-01.S", + "rv32i_m/I/src/fence-01.S", + "rv32i_m/I/src/jal-01.S", + "rv32i_m/I/src/jalr-01.S", + "rv32i_m/I/src/lb-align-01.S", + "rv32i_m/I/src/lbu-align-01.S", + "rv32i_m/I/src/lh-align-01.S", + "rv32i_m/I/src/lhu-align-01.S", + "rv32i_m/I/src/lui-01.S", + "rv32i_m/I/src/lw-align-01.S", + "rv32i_m/I/src/or-01.S", + "rv32i_m/I/src/ori-01.S", + "rv32i_m/I/src/sb-align-01.S", + "rv32i_m/I/src/sh-align-01.S", + "rv32i_m/I/src/sll-01.S", + "rv32i_m/I/src/slli-01.S", + "rv32i_m/I/src/slt-01.S", + "rv32i_m/I/src/slti-01.S", + "rv32i_m/I/src/sltiu-01.S", + "rv32i_m/I/src/sltu-01.S", + "rv32i_m/I/src/sra-01.S", + "rv32i_m/I/src/srai-01.S", + "rv32i_m/I/src/srl-01.S", + "rv32i_m/I/src/srli-01.S", + "rv32i_m/I/src/sub-01.S", + "rv32i_m/I/src/sw-align-01.S", + "rv32i_m/I/src/xor-01.S", + "rv32i_m/I/src/xori-01.S" +}; + string arch64m[] = '{ `RISCVARCHTEST, "rv64i_m/M/src/div-01.S", @@ -1422,101 +1536,59 @@ string arch64b[] = '{ "rv64i_m/B/src/binvi-01.S", "rv64i_m/B/src/bset-01.S", "rv64i_m/B/src/bseti-01.S" - /*"rv64i_m/B/src/add.uw-01.S", - "rv64i_m/B/src/bclr-01.S", - "rv64i_m/B/src/bclri-01.S", - "rv64i_m/B/src/bext-01.S", - "rv64i_m/B/src/bexti-01.S", - "rv64i_m/B/src/binv-01.S", - "rv64i_m/B/src/binvi-01.S", - "rv64i_m/B/src/bset-01.S", - "rv64i_m/B/src/bseti-01.S", - "rv64i_m/B/src/clmul-01.S", - - - - "rv64i_m/B/src/rol-01.S", - - - - - */ }; -string arch32b[] = '{ + string arch64zba[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/slli.uw-01.S", + "rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/sh1add-01.S", + "rv64i_m/B/src/sh2add-01.S", + "rv64i_m/B/src/sh3add-01.S", + "rv64i_m/B/src/sh1add.uw-01.S", + "rv64i_m/B/src/sh2add.uw-01.S", + "rv64i_m/B/src/sh3add.uw-01.S" + }; + + + +string arch64zbb[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/max-01.S", + "rv64i_m/B/src/maxu-01.S", + "rv64i_m/B/src/min-01.S", + "rv64i_m/B/src/minu-01.S", + "rv64i_m/B/src/orcb_64-01.S", + "rv64i_m/B/src/rev8-01.S", + "rv64i_m/B/src/andn-01.S", + "rv64i_m/B/src/orn-01.S", + "rv64i_m/B/src/xnor-01.S", + "rv64i_m/B/src/zext.h-01.S", + "rv64i_m/B/src/sext.b-01.S", + "rv64i_m/B/src/sext.h-01.S", + "rv64i_m/B/src/clz-01.S", + "rv64i_m/B/src/clzw-01.S", + "rv64i_m/B/src/cpop-01.S", + "rv64i_m/B/src/cpopw-01.S", + "rv64i_m/B/src/ctz-01.S", + "rv64i_m/B/src/ctzw-01.S", + "rv64i_m/B/src/rolw-01.S", + "rv64i_m/B/src/ror-01.S", + "rv64i_m/B/src/rori-01.S", + "rv64i_m/B/src/roriw-01.S", + "rv64i_m/B/src/rorw-01.S", + "rv64i_m/B/src/rol-01.S" +}; + +string arch64zbc[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/clmul-01.S", + "rv64i_m/B/src/clmulh-01.S", + "rv64i_m/B/src/clmulr-01.S" +}; + +string arch64zbs[] = '{ `RISCVARCHTEST, - "rv32i_m/B/src/clmul-01.S", - "rv32i_m/B/src/clmulh-01.S", - "rv32i_m/B/src/clmulr-01.S", - "rv32i_m/B/src/bclr-01.S", - "rv32i_m/B/src/bclri-01.S", - "rv32i_m/B/src/bext-01.S", - "rv32i_m/B/src/bexti-01.S", - "rv32i_m/B/src/binv-01.S", - "rv32i_m/B/src/binvi-01.S", - "rv32i_m/B/src/bset-01.S", - "rv32i_m/B/src/bseti-01.S", - "rv32i_m/B/src/max-01.S", - "rv32i_m/B/src/maxu-01.S", - "rv32i_m/B/src/min-01.S", - "rv32i_m/B/src/minu-01.S", - "rv32i_m/B/src/orcb_32-01.S", - "rv32i_m/B/src/rev8_32-01.S", - "rv32i_m/B/src/andn-01.S", - "rv32i_m/B/src/orn-01.S", - "rv32i_m/B/src/xnor-01.S", - "rv32i_m/B/src/zext.h_32-01.S", - "rv32i_m/B/src/sext.b-01.S", - "rv32i_m/B/src/sext.h-01.S", - "rv32i_m/B/src/clz-01.S", - "rv32i_m/B/src/cpop-01.S", - "rv32i_m/B/src/ctz-01.S", - "rv32i_m/B/src/ror-01.S", - "rv32i_m/B/src/rori-01.S", - "rv32i_m/B/src/rol-01.S", - "rv32i_m/B/src/sh1add-01.S", - "rv32i_m/B/src/sh2add-01.S", - "rv32i_m/B/src/sh3add-01.S", - "rv32i_m/I/src/add-01.S", - "rv32i_m/I/src/addi-01.S", - "rv32i_m/I/src/and-01.S", - "rv32i_m/I/src/andi-01.S", - "rv32i_m/I/src/auipc-01.S", - "rv32i_m/I/src/beq-01.S", - "rv32i_m/I/src/bge-01.S", - "rv32i_m/I/src/bgeu-01.S", - "rv32i_m/I/src/blt-01.S", - "rv32i_m/I/src/bltu-01.S", - "rv32i_m/I/src/bne-01.S", - "rv32i_m/I/src/fence-01.S", - "rv32i_m/I/src/jal-01.S", - "rv32i_m/I/src/jalr-01.S", - "rv32i_m/I/src/lb-align-01.S", - "rv32i_m/I/src/lbu-align-01.S", - "rv32i_m/I/src/lh-align-01.S", - "rv32i_m/I/src/lhu-align-01.S", - "rv32i_m/I/src/lui-01.S", - "rv32i_m/I/src/lw-align-01.S", - "rv32i_m/I/src/or-01.S", - "rv32i_m/I/src/ori-01.S", - "rv32i_m/I/src/sb-align-01.S", - "rv32i_m/I/src/sh-align-01.S", - "rv32i_m/I/src/sll-01.S", - "rv32i_m/I/src/slli-01.S", - "rv32i_m/I/src/slt-01.S", - "rv32i_m/I/src/slti-01.S", - "rv32i_m/I/src/sltiu-01.S", - "rv32i_m/I/src/sltu-01.S", - "rv32i_m/I/src/sra-01.S", - "rv32i_m/I/src/srai-01.S", - "rv32i_m/I/src/srl-01.S", - "rv32i_m/I/src/srli-01.S", - "rv32i_m/I/src/sub-01.S", - "rv32i_m/I/src/sw-align-01.S", - "rv32i_m/I/src/xor-01.S", - "rv32i_m/I/src/xori-01.S" - - /*"rv64i_m/B/src/add.uw-01.S", "rv64i_m/B/src/bclr-01.S", "rv64i_m/B/src/bclri-01.S", "rv64i_m/B/src/bext-01.S", @@ -1524,18 +1596,11 @@ string arch32b[] = '{ "rv64i_m/B/src/binv-01.S", "rv64i_m/B/src/binvi-01.S", "rv64i_m/B/src/bset-01.S", - "rv64i_m/B/src/bseti-01.S", - "rv64i_m/B/src/clmul-01.S", - - - - "rv64i_m/B/src/rol-01.S", - - - - - */ + "rv64i_m/B/src/bseti-01.S" }; + + + string arch32priv[] = '{ `RISCVARCHTEST, "rv32i_m/privilege/src/ebreak.S", From 0339dc5e787badb821757253c7ef3034661e3439 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Tue, 21 Feb 2023 15:26:47 -0800 Subject: [PATCH 094/231] added extra commands to make dut run work with spike for bit manip tests --- tests/riscof/spike/riscof_spike.py | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tests/riscof/spike/riscof_spike.py b/tests/riscof/spike/riscof_spike.py index d7d65c0b3..308d55f28 100644 --- a/tests/riscof/spike/riscof_spike.py +++ b/tests/riscof/spike/riscof_spike.py @@ -105,6 +105,14 @@ class spike(pluginTemplate): self.isa += 'd' if "C" in ispec["ISA"]: self.isa += 'c' + if "Zba" in ispec["ISA"]: + self.isa += '_Zba' + if "Zbb" in ispec["ISA"]: + self.isa += '_Zbb' + if "Zbc" in ispec["ISA"]: + self.isa += '_Zbc' + if "Zbs" in ispec["ISA"]: + self.isa += '_Zbs' #TODO: The following assumes you are using the riscv-gcc toolchain. If # not please change appropriately From ba3bfdf68b6121fcbff2405fb638aed676222019 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Feb 2023 19:42:30 -0800 Subject: [PATCH 095/231] Manual attempt to merge with upstream changes --- sim/imperas.ic | 1 - sim/wally-imperas.do | 1 + src/generic/lzc.sv | 2 +- src/generic/mem/ram1p1rwbe.sv | 4 +- src/ieu/controller.sv | 4 +- src/ieu/datapath.sv | 29 ++++++++ src/ieu/ieu.sv | 9 +-- src/ifu/bpred/RASPredictor.sv | 7 +- src/ifu/bpred/bpred.sv | 75 ++++++++------------- src/ifu/bpred/btb.sv | 1 - src/ifu/bpred/gshare.sv | 4 +- src/ifu/ifu.sv | 2 + src/wally/wallypipelinedcore.sv | 3 + synthDC/.synopsys_dc.setup | 4 ++ synthDC/Makefile | 5 +- synthDC/wallySynth.py | 2 +- testbench/testbench_imperas.sv | 1 + testbench/tests.vh | 1 - tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py | 34 ---------- tests/riscof/spike/spike_rv32gc_isa.yaml | 4 +- tests/riscof/spike/spike_rv64gc_isa.yaml | 4 +- 21 files changed, 88 insertions(+), 109 deletions(-) delete mode 100644 tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py diff --git a/sim/imperas.ic b/sim/imperas.ic index 302773d0e..d28234bbc 100644 --- a/sim/imperas.ic +++ b/sim/imperas.ic @@ -1,6 +1,5 @@ --override cpu/show_c_prefix=T --override cpu/unaligned=F ---override cpu/mstatus_FS=1 --override cpu/ignore_non_leaf_DAU=1 # Enable the Imperas instruction coverage diff --git a/sim/wally-imperas.do b/sim/wally-imperas.do index 821b9e54e..985739cb4 100644 --- a/sim/wally-imperas.do +++ b/sim/wally-imperas.do @@ -35,6 +35,7 @@ vlog +incdir+../config/$1 \ $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/imperasDV-api-pkg.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2api.sv \ $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2log.sv \ + $env(IMPERAS_HOME)/ImpProprietary/source/host/rvvi/trace2cov.sv \ ../testbench/testbench_imperas.sv \ ../testbench/common/*.sv \ ../src/*/*.sv \ diff --git a/src/generic/lzc.sv b/src/generic/lzc.sv index 60719c494..ecfd6796a 100644 --- a/src/generic/lzc.sv +++ b/src/generic/lzc.sv @@ -33,6 +33,6 @@ module lzc #(parameter WIDTH = 1) ( always_comb begin i = 0; while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1; // search for leading one - ZeroCnt = i[$clog2(WIDTH)-1:0]; + ZeroCnt = i[$clog2(WIDTH+1)-1:0]; end endmodule diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 81142a171..f3c98873e 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -55,7 +55,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) ( logic [WIDTH-1:0] BitWriteMask; for (index=0; index < WIDTH; index++) assign BitWriteMask[index] = bwe[index/8]; - TS1N28HPCPSVTB64X128M4SW sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), + ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); @@ -75,7 +75,7 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) ( logic [WIDTH-1:0] BitWriteMask; for (index=0; index < WIDTH; index++) assign BitWriteMask[index] = bwe[index/8]; - ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), + ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), .A(addr), .D(din), .BWEB(~BitWriteMask), .Q(dout)); diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 95ebe7dc6..02ef3eeae 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -66,6 +66,8 @@ module controller( output logic RegWriteM, // Instruction writes a register (needed for Hazard unit) output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$ output logic InstrValidD, InstrValidE, InstrValidM, // Instruction is valid + output logic BranchD, BranchE, + output logic JumpD, output logic FWriteIntM, // FPU controller writes integer register file // Writeback stage control signals @@ -88,8 +90,6 @@ module controller( logic RegWriteD, RegWriteE; // RegWrite (register will be written) logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file logic [1:0] MemRWD, MemRWE; // Store (write to memory) - logic JumpD; // Jump instruction - logic BranchD, BranchE; // Branch instruction logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) logic [2:0] ALUControlD; // Determines ALU operation logic [2:0] ALUSelectD; // ALU mux select signal diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index d0f6f0397..9f09efe77 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -1,3 +1,32 @@ +/////////////////////////////////////////// +// datapath.sv +// +// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu +// Created: 9 January 2021 +// Modified: +// +// Purpose: Wally Integer Datapath +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + `include "wally-config.vh" module datapath ( diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 0b2fbf84e..43c16554d 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -55,6 +55,8 @@ module ieu ( input logic [`XLEN-1:0] FIntResM, // Integer result from FPU (fmv, fclass, fcmp) output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$ output logic InstrValidD, InstrValidE, InstrValidM,// Instruction is valid + output logic BranchD, BranchE, + output logic JumpD, JumpE, // Writeback stage signals input logic [`XLEN-1:0] FIntDivResultW, // Integer divide result from FPU fdivsqrt) input logic [`XLEN-1:0] CSRReadValW, // CSR read value, @@ -90,15 +92,14 @@ module ieu ( logic [1:0] ForwardAE, ForwardBE; // Select signals for forwarding multiplexers logic RegWriteM, RegWriteW; // Register will be written in Memory, Writeback stages logic MemReadE, CSRReadE; // Load, CSRRead instruction - logic JumpE; // Jump instruction logic BranchSignedE; // Branch does signed comparison on operands logic MDUE; // Multiply/divide instruction - controller c( +controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE, - .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE, - .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, + .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, + .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD); diff --git a/src/ifu/bpred/RASPredictor.sv b/src/ifu/bpred/RASPredictor.sv index 0a841ae11..330607af4 100644 --- a/src/ifu/bpred/RASPredictor.sv +++ b/src/ifu/bpred/RASPredictor.sv @@ -34,7 +34,9 @@ module RASPredictor #(parameter int StackSize = 16 )( input logic reset, input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM, input logic [3:0] WrongPredInstrClassD, // Prediction class is wrong - input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, // Instr class + input logic [3:0] InstrClassD, + input logic [3:0] InstrClassE, // Instr class + input logic [3:0] PredInstrClassF, input logic [`XLEN-1:0] PCLinkE, // PC of instruction after a jal output logic [`XLEN-1:0] RASPCF // Top of the stack ); @@ -93,6 +95,3 @@ module RASPredictor #(parameter int StackSize = 16 )( endmodule - - - diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index f6f826118..710775968 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -52,6 +52,8 @@ module bpred ( // Branch and jump outcome input logic InstrValidD, InstrValidE, + input logic BranchD, BranchE, + input logic JumpD, JumpE, input logic PCSrcE, // Executation stage branch is taken input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address input logic [`XLEN-1:0] IEUAdrM, // The branch/jump target address @@ -74,7 +76,8 @@ module bpred ( logic [`XLEN-1:0] PredPCF, RASPCF; logic PredictionPCWrongE; logic AnyWrongPredInstrClassD, AnyWrongPredInstrClassE; - logic [3:0] InstrClassF, InstrClassD, InstrClassE, InstrClassW; + logic [3:0] InstrClassD; + logic [3:0] InstrClassE; logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE; logic SelBPPredF; @@ -83,9 +86,9 @@ module bpred ( logic [`XLEN-1:0] PCCorrectE; logic [3:0] WrongPredInstrClassD; - logic BTBTargetWrongE; - logic RASTargetWrongE; - logic JumpOrTakenBranchE; + logic BTBTargetWrongE; + logic RASTargetWrongE; + logic JumpOrTakenBranchE; logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE; @@ -113,29 +116,11 @@ module bpred ( .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); -<<<<<<< HEAD - end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor - speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .DirPredictionF, .DirPredictionWrongE, - .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE); - - end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor - gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM, - .PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE, - .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); - - end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor - speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, - .PCNextF, .PCF, .PCD, .PCE, .DirPredictionF, .DirPredictionWrongE, - .PredInstrClassF, .InstrClassD, .InstrClassE, .WrongPredInstrClassD, .PCSrcE); - -======= end else if (`BPRED_TYPE == "BP_GLOBAL_BASIC") begin:Predictor gsharebasic #(`BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE, .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE); ->>>>>>> upstream/main end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor // *** Fix me /* -----\/----- EXCLUDED -----\/----- @@ -167,7 +152,8 @@ module bpred ( if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode logic [4:0] CompressedOpcF; logic [3:0] InstrClassF; - logic cjal, cj, cjr, cjalr; + logic cjal, cj, cjr, cjalr, CJumpF, CBranchF; + logic JumpF, BranchF; assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]}; @@ -175,24 +161,23 @@ module bpred ( assign cj = CompressedOpcF == 5'h0d; assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0; + assign CJumpF = cjal | cj | cjr | cjalr; + assign CBranchF = CompressedOpcF[4:1] == 4'h7; + + assign JumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F; + assign BranchF = PostSpillInstrRawF[6:0] == 7'h63; - assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 | - (`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7); - - assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return - (PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5 - (`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) )); - - assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5 + assign InstrClassF[0] = BranchF | (`C_SUPPORTED & CBranchF); + assign InstrClassF[1] = JumpF | (`C_SUPPORTED & (cjal | cj | cj | cjalr)); + assign InstrClassF[2] = (JumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01) | // return must return to ra or r5 (`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01)); - assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 + assign InstrClassF[3] = (JumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5 (`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01))); + assign PredInstrClassF = InstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | - PredInstrClassF[2] | - PredInstrClassF[1] | - PredInstrClassF[3]; + PredInstrClassF[1]; end else begin assign PredInstrClassF = BTBPredInstrClassF; assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) | @@ -206,15 +191,13 @@ module bpred ( assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF; - assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 - assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5 - assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return - (InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5 - assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch + assign InstrClassD[0] = BranchD; + assign InstrClassD[1] = JumpD ; + assign InstrClassD[2] = JumpD & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or x5 + assign InstrClassD[3] = JumpD & (InstrD[11:7] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5 flopenrc #(4) InstrClassRegE(clk, reset, FlushE, ~StallE, InstrClassD, InstrClassE); flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, InstrClassE, InstrClassM); - flopenrc #(4) InstrClassRegW(clk, reset, FlushW, ~StallW, InstrClassM, InstrClassW); flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM); // branch predictor @@ -235,13 +218,10 @@ module bpred ( assign PredictionPCWrongE = PCCorrectE != PCD; // branch class prediction wrong. - assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD; + assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD[3:0]; assign AnyWrongPredInstrClassD = |WrongPredInstrClassD; // branch is wrong only if the PC does not match and both the Decode and Fetch stages have valid instructions. -<<<<<<< HEAD - assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD; -======= //assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE | (AnyWrongPredInstrClassE & ~|InstrClassE)); assign BPPredWrongE = PredictionPCWrongE & InstrValidE & InstrValidD; @@ -249,7 +229,6 @@ module bpred ( logic NotMatch; assign BPPredWrongEAlt = PredictionPCWrongE & InstrValidE & InstrValidD; // this does not work for cubic benchmark assign NotMatch = BPPredWrongE != BPPredWrongEAlt; ->>>>>>> upstream/main // Output the predicted PC or corrected PC on miss-predict. // Selects the BP or PC+2/4. @@ -274,10 +253,10 @@ module bpred ( // could be wrong or the fall through address selected for branch predict not taken. // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of // both without the above inaccuracies. - assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE; + assign BTBPredPCWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] & ~InstrClassE[2]) & PCSrcE; assign RASPredPCWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE; - assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3]; + assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1]; flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM); diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index a6201d4c1..8e2d0e259 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -52,7 +52,6 @@ module btb #(parameter Depth = 10 ) ( logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF; logic [`XLEN+3:0] TableBTBPredictionF; logic [`XLEN-1:0] PredPCD; - logic [3:0] PredInstrClassD; // *** copy of reg outside module logic UpdateEn; // hashing function for indexing the PC diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index 7ab6f7140..5332ce5cd 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -33,8 +33,8 @@ module gshare #(parameter k = 10, parameter integer TYPE = 1) ( input logic clk, input logic reset, - input logic StallF, StallD, StallE, StallM, - input logic FlushD, FlushE, FlushM, + input logic StallF, StallD, StallE, StallM, StallW, + input logic FlushD, FlushE, FlushM, FlushW, output logic [1:0] DirPredictionF, output logic DirPredictionWrongE, // update diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 73e4c7e73..71221ef63 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -36,6 +36,8 @@ module ifu ( input logic InvalidateICacheM, // Clears all instruction cache valid bits input logic CSRWriteFenceM, // CSR write or fence instruction, PCNextF = the next valid PC (typically PCE) input logic InstrValidD, InstrValidE, InstrValidM, + input logic BranchD, BranchE, + input logic JumpD, JumpE, // Bus interface output logic [`PA_BITS-1:0] IFUHADDR, // Bus address from IFU to EBU input logic [`XLEN-1:0] HRDATA, // Bus read data from IFU to EBU diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 71bad10ad..02074f973 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -161,11 +161,13 @@ module wallypipelinedcore ( logic FCvtIntE; logic CommittedF; logic JumpOrTakenBranchM; + logic BranchD, BranchE, JumpD, JumpE; // instruction fetch unit: PC, branch prediction, instruction cache ifu ifu(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .InstrValidM, .InstrValidE, .InstrValidD, + .BranchD, .BranchE, .JumpD, .JumpE, // Fetch .HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F, .IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE, @@ -199,6 +201,7 @@ module wallypipelinedcore ( .Funct3M, // size and signedness to LSU .SrcAM, // to privilege and fpu .RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM, + .BranchD, .BranchE, .JumpD, .JumpE, // Writeback stage .CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]), .InstrValidM, .InstrValidE, .InstrValidD, .FCvtIntResW, .FCvtIntW, diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 310b45c09..5c6b7f6b9 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -52,6 +52,10 @@ if {$tech == "sky130"} { lappend target_library $s9lib/scc9gena_tt_1.2v_25C.db } elseif {$tech == "tsmc28"} { lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db +} elseif {$tech == "tsmc28psyn"} { + set mw_reference_library [list ] + lappend target_library $s10lib/tcbn28hpcplusbwp30p140tt0p9v25c.db + lappend mw_reference_library $MW_REFERENCE_LIBRARY/tcbn28hpcplusbwp30p140 } # Set up DesignWare cache read and write directories to speed up compile. diff --git a/synthDC/Makefile b/synthDC/Makefile index 208fabaa0..136e610d2 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -30,8 +30,6 @@ export SAIFPOWER ?= 0 OLDCONFIGDIR ?= ${WALLY}/config export CONFIGDIR ?= $(OUTPUTDIR)/config - - default: @echo " Basic synthesis procedure for Wally:" @echo " Invoke with make synth" @@ -130,7 +128,6 @@ mkdirecs: @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped - synth: mkdirecs configs rundc clean rundc: @@ -150,4 +147,4 @@ clean: rm -f filenames*.log rm -f power.saif rm -f Synopsys_stack_trace_*.txt - rm -f crte_*.txt \ No newline at end of file + rm -f crte_*.txt diff --git a/synthDC/wallySynth.py b/synthDC/wallySynth.py index c1ea7b9cb..139bcdd60 100755 --- a/synthDC/wallySynth.py +++ b/synthDC/wallySynth.py @@ -16,7 +16,7 @@ def mask(command): if __name__ == '__main__': - techs = ['sky90', 'tsmc28'] + techs = ['sky90', 'tsmc28', 'tsmc28psyn'] allConfigs = ['rv32gc', 'rv32imc', 'rv64gc', 'rv64imc', 'rv32e', 'rv32i', 'rv64i'] freqVaryPct = [-20, -12, -8, -6, -4, -2, 0, 2, 4, 6, 8, 12, 20] # freqVaryPct = [-20, -10, 0, 10, 20] diff --git a/testbench/testbench_imperas.sv b/testbench/testbench_imperas.sv index cbd08c3b9..f26339007 100644 --- a/testbench/testbench_imperas.sv +++ b/testbench/testbench_imperas.sv @@ -126,6 +126,7 @@ module testbench; `ifdef USE_IMPERAS_DV trace2log idv_trace2log(rvvi); + trace2cov idv_trace2cov(rvvi); // enabling of comparison types trace2api #(.CMP_PC (1), diff --git a/testbench/tests.vh b/testbench/tests.vh index cb15a5ee3..e86b83f9e 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -54,7 +54,6 @@ string tvpaths[] = '{ "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches "bd_speedopt_speed/src/aha-mont64/aha-mont64", "bd_speedopt_speed/src/crc32/crc32", - "bd_speedopt_speed/src/cubic/cubic", // cubic is likely going to removed when embench 2.0 launches "bd_speedopt_speed/src/edn/edn", "bd_speedopt_speed/src/huffbench/huffbench", "bd_speedopt_speed/src/matmult-int/matmult-int", diff --git a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py b/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py deleted file mode 100644 index 4a728a476..000000000 --- a/tests/riscof/make-zb_REMOVE_BEFORE_MERGE.py +++ /dev/null @@ -1,34 +0,0 @@ -#Kip Macsai-Goren and Kevin Kim -#Purpose is to manually make the B extension tests -import os - -f = open("genBScript.sh", "w") -WALLY = os.getenv("WALLY") -os.chdir(f"{WALLY}/tests/riscof/riscof_work/rv64i_m/B/src") - -lines = "" - -#BUILDS B TESTS -for testname in os.listdir(): - lines = lines + f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/B/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; -rsync -a {WALLY}/tests/riscof/riscof_work/rv64i_m/ {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/ || echo "error suppressed"; -riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/B/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.memfile; -extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/B/src/{testname}/ref/ref.elf.objdump; -""" - -os.chdir(f"{WALLY}/tests/riscof/riscof_work/rv64i_m/I/src") - -#BUILDS I TESTS -for testname in os.listdir(): - lines = lines + f"""cd {WALLY}/tests/riscof/riscof_work/rv64i_m/I/src/{testname}/ref;riscv64-unknown-elf-gcc -march=rv64izba_zbb_zbc_zbs -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -T {WALLY}/tests/riscof/sail_cSim/env/link.ld -I {WALLY}/tests/riscof/sail_cSim/env/ -I {WALLY}/addins/riscv-arch-test/riscv-test-suite/env -mabi=lp64 {WALLY}/addins/riscv-arch-test/riscv-test-suite/rv64i_m/I/src/{testname} -o ref.elf -DTEST_CASE_1=True -DXLEN=64;riscv64-unknown-elf-objdump -D ref.elf > ref.elf.objdump;riscv_sim_RV64 -z268435455 -i --test-signature={WALLY}/tests/riscof/riscof_work/rv64i_m/I/src/{testname}/ref/Reference-sail_c_simulator.signature ref.elf > add.uw-01.log 2>&1; -rsync -a {WALLY}/tests/riscof/riscof_work/rv64i_m/ {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/ || echo "error suppressed"; -riscv64-unknown-elf-elf2hex --bit-width 64 --input {WALLY}/tests/riscof/riscof_work/rv64i_m/I/src/{testname}/ref/ref.elf --output {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/{testname}/ref/ref.elf.memfile; -extractFunctionRadix.sh {WALLY}/tests/riscof/work/riscv-arch-test/rv64i_m/I/src/{testname}/ref/ref.elf.objdump; -""" - - - - -f.write(lines) -f.close() - diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index 4a5935244..05fc6f60e 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,12 +1,12 @@ hart_ids: [0] hart0: #ISA: RV32IMAFDCZicsr_Zifencei - ISA: RV32IMACZicsr_Zifencei_Zba_Zbb_Zbc_Zbs + ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 32 User_Spec_Version: '2.3' supported_xlen: [32] misa: - reset-val: 0x40001105 + reset-val: 0x4000112D rv32: accessible: true mxl: diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index ad745f47b..e6bfc72ef 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -1,12 +1,12 @@ hart_ids: [0] hart0: # ISA: RV64IMAFDCSUZicsr_Zifencei - ISA: RV64IMACSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs + ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 56 User_Spec_Version: '2.3' supported_xlen: [64] misa: - reset-val: 0x8000000000141105 + reset-val: 0x800000000014112D rv32: accessible: false rv64: From 1a9ba9d9444ed417ccdd84c6db7e9cc3d522f625 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Feb 2023 20:17:52 -0800 Subject: [PATCH 096/231] added 32 bit tests for bit manipulation --- config/rv32gc/wally-config.vh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/config/rv32gc/wally-config.vh b/config/rv32gc/wally-config.vh index 57857f3be..1fb89abf1 100644 --- a/config/rv32gc/wally-config.vh +++ b/config/rv32gc/wally-config.vh @@ -144,10 +144,10 @@ `define DIVCOPIES 32'h4 // bit manipulation -`define ZBA_SUPPORTED 0 -`define ZBB_SUPPORTED 0 -`define ZBC_SUPPORTED 0 -`define ZBS_SUPPORTED 0 +`define ZBA_SUPPORTED 1 +`define ZBB_SUPPORTED 1 +`define ZBC_SUPPORTED 1 +`define ZBS_SUPPORTED 1 // Memory synthesis configuration `define USE_SRAM 0 From 6b047065efbc4c584ac7d899e7496e6653f0a8aa Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Feb 2023 20:18:05 -0800 Subject: [PATCH 097/231] added bit manipulation tests to regression --- sim/regression-wally | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index 07603120b..82cb4eff4 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -66,7 +66,7 @@ tc = TestCase( configs.append(tc) tests64gcimperas = ["imperas64i", "imperas64f", "imperas64d", "imperas64m", "imperas64c"] # unused -tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] +tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "wally64a", "wally64periph", "wally64priv"] for test in tests64gc: tc = TestCase( name=test, @@ -85,7 +85,7 @@ for test in tests64i: configs.append(tc) tests32gcimperas = ["imperas32i", "imperas32f", "imperas32m", "imperas32c"] # unused -tests32gc = ["arch32f", "arch32d", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32zi", "wally32a", "wally32priv", "wally32periph"] +tests32gc = ["arch32f", "arch32d", "arch32i", "arch32priv", "arch32c", "arch32m", "arch32zi", "arch32zba", "arch32zbb", "arch32zbc", "arch32zbs", "wally32a", "wally32priv", "wally32periph"] for test in tests32gc: tc = TestCase( name=test, From 67f83cda7f1e2021986dfd55f95b5c83b979f746 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Feb 2023 20:25:51 -0800 Subject: [PATCH 098/231] Fixed lint errors on zero and pop count. All of regression passes --- src/ieu/bmu/cnt.sv | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 540d5e910..32be6b2eb 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -79,9 +79,12 @@ module cnt #(parameter WIDTH = 32) ( end end - //NOTE: Signal width mistmatch from log2(WIDTH) to WIDTH but deal with that later. - lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult)); - popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult)); + + lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult[$clog2(WIDTH):0])); + popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult[$clog2(WIDTH):0])); + // zero extend these results to fit into width *** There may be a more elegant way to do this + assign czResult[WIDTH-1:$clog2(WIDTH)+1] = {(WIDTH-$clog2(WIDTH)-1){1'b0}}; + assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = {(WIDTH-$clog2(WIDTH)-1){1'b0}}; assign CntResult = (B[1]) ? cpopResult : czResult; From bb1e99a58c7238873d22ed9a3b81e3800baf6819 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Feb 2023 20:35:01 -0800 Subject: [PATCH 099/231] Cleaned up consolidated arch_b tests from tests.vh --- testbench/testbench.sv | 4 +- testbench/tests.vh | 176 ----------------------------------------- 2 files changed, 1 insertion(+), 179 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index ec2829573..eb5014999 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -109,7 +109,6 @@ logic [3:0] dummy; "arch64zbb": if (`ZBB_SUPPORTED) tests = arch64zbb; "arch64zbc": if (`ZBC_SUPPORTED) tests = arch64zbc; "arch64zbs": if (`ZBS_SUPPORTED) tests = arch64zbs; - "arch64b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch64b; endcase end else begin // RV32 case (TEST) @@ -138,7 +137,6 @@ logic [3:0] dummy; "arch32zbb": if (`ZBB_SUPPORTED) tests = arch32zbb; "arch32zbc": if (`ZBC_SUPPORTED) tests = arch32zbc; "arch32zbs": if (`ZBS_SUPPORTED) tests = arch32zbs; - "arch32b": if (`ZBB_SUPPORTED & `ZBA_SUPPORTED & `ZBS_SUPPORTED & `ZBC_SUPPORTED) tests = arch32b; endcase end if (tests.size() == 0) begin @@ -364,7 +362,7 @@ logic [3:0] dummy; errors = errors+1; $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); - $stop;//***debug + //$stop;//***debug end i = i + 1; end diff --git a/testbench/tests.vh b/testbench/tests.vh index e86b83f9e..e00ae7d71 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -929,80 +929,6 @@ string imperas32f[] = '{ "rv32i_m/B/src/bseti-01.S" }; - string arch32b[] = '{ - `RISCVARCHTEST, - "rv32i_m/B/src/clmul-01.S", - "rv32i_m/B/src/clmulh-01.S", - "rv32i_m/B/src/clmulr-01.S", - "rv32i_m/B/src/bclr-01.S", - "rv32i_m/B/src/bclri-01.S", - "rv32i_m/B/src/bext-01.S", - "rv32i_m/B/src/bexti-01.S", - "rv32i_m/B/src/binv-01.S", - "rv32i_m/B/src/binvi-01.S", - "rv32i_m/B/src/bset-01.S", - "rv32i_m/B/src/bseti-01.S", - "rv32i_m/B/src/max-01.S", - "rv32i_m/B/src/maxu-01.S", - "rv32i_m/B/src/min-01.S", - "rv32i_m/B/src/minu-01.S", - "rv32i_m/B/src/orcb_32-01.S", - "rv32i_m/B/src/rev8_32-01.S", - "rv32i_m/B/src/andn-01.S", - "rv32i_m/B/src/orn-01.S", - "rv32i_m/B/src/xnor-01.S", - "rv32i_m/B/src/zext.h_32-01.S", - "rv32i_m/B/src/sext.b-01.S", - "rv32i_m/B/src/sext.h-01.S", - "rv32i_m/B/src/clz-01.S", - "rv32i_m/B/src/cpop-01.S", - "rv32i_m/B/src/ctz-01.S", - "rv32i_m/B/src/ror-01.S", - "rv32i_m/B/src/rori-01.S", - "rv32i_m/B/src/rol-01.S", - "rv32i_m/B/src/sh1add-01.S", - "rv32i_m/B/src/sh2add-01.S", - "rv32i_m/B/src/sh3add-01.S", - "rv32i_m/I/src/add-01.S", - "rv32i_m/I/src/addi-01.S", - "rv32i_m/I/src/and-01.S", - "rv32i_m/I/src/andi-01.S", - "rv32i_m/I/src/auipc-01.S", - "rv32i_m/I/src/beq-01.S", - "rv32i_m/I/src/bge-01.S", - "rv32i_m/I/src/bgeu-01.S", - "rv32i_m/I/src/blt-01.S", - "rv32i_m/I/src/bltu-01.S", - "rv32i_m/I/src/bne-01.S", - "rv32i_m/I/src/fence-01.S", - "rv32i_m/I/src/jal-01.S", - "rv32i_m/I/src/jalr-01.S", - "rv32i_m/I/src/lb-align-01.S", - "rv32i_m/I/src/lbu-align-01.S", - "rv32i_m/I/src/lh-align-01.S", - "rv32i_m/I/src/lhu-align-01.S", - "rv32i_m/I/src/lui-01.S", - "rv32i_m/I/src/lw-align-01.S", - "rv32i_m/I/src/or-01.S", - "rv32i_m/I/src/ori-01.S", - "rv32i_m/I/src/sb-align-01.S", - "rv32i_m/I/src/sh-align-01.S", - "rv32i_m/I/src/sll-01.S", - "rv32i_m/I/src/slli-01.S", - "rv32i_m/I/src/slt-01.S", - "rv32i_m/I/src/slti-01.S", - "rv32i_m/I/src/sltiu-01.S", - "rv32i_m/I/src/sltu-01.S", - "rv32i_m/I/src/sra-01.S", - "rv32i_m/I/src/srai-01.S", - "rv32i_m/I/src/srl-01.S", - "rv32i_m/I/src/srli-01.S", - "rv32i_m/I/src/sub-01.S", - "rv32i_m/I/src/sw-align-01.S", - "rv32i_m/I/src/xor-01.S", - "rv32i_m/I/src/xori-01.S" -}; - string arch64m[] = '{ `RISCVARCHTEST, "rv64i_m/M/src/div-01.S", @@ -1440,104 +1366,6 @@ string imperas32f[] = '{ "rv64i_m/D/src/fssub.d_b8-01.S" }; - -string arch64b[] = '{ - `RISCVARCHTEST, - "rv64i_m/B/src/max-01.S", - "rv64i_m/B/src/maxu-01.S", - "rv64i_m/B/src/min-01.S", - "rv64i_m/B/src/minu-01.S", - "rv64i_m/B/src/orcb_64-01.S", - "rv64i_m/B/src/rev8-01.S", - "rv64i_m/B/src/andn-01.S", - "rv64i_m/B/src/orn-01.S", - "rv64i_m/B/src/xnor-01.S", - "rv64i_m/B/src/zext.h-01.S", - "rv64i_m/B/src/sext.b-01.S", - "rv64i_m/B/src/sext.h-01.S", - "rv64i_m/B/src/clz-01.S", - "rv64i_m/B/src/clzw-01.S", - "rv64i_m/B/src/cpop-01.S", - "rv64i_m/B/src/cpopw-01.S", - "rv64i_m/B/src/ctz-01.S", - "rv64i_m/B/src/ctzw-01.S", - "rv64i_m/B/src/rolw-01.S", - "rv64i_m/B/src/ror-01.S", - "rv64i_m/B/src/rori-01.S", - "rv64i_m/B/src/roriw-01.S", - "rv64i_m/B/src/rorw-01.S", - "rv64i_m/B/src/rol-01.S", - "rv64i_m/B/src/slli.uw-01.S", - "rv64i_m/B/src/add.uw-01.S", - "rv64i_m/B/src/sh1add-01.S", - "rv64i_m/B/src/sh2add-01.S", - "rv64i_m/B/src/sh3add-01.S", - "rv64i_m/B/src/sh1add.uw-01.S", - "rv64i_m/B/src/sh2add.uw-01.S", - "rv64i_m/B/src/sh3add.uw-01.S", - "rv64i_m/I/src/add-01.S", - "rv64i_m/I/src/addi-01.S", - "rv64i_m/I/src/addiw-01.S", - "rv64i_m/I/src/addw-01.S", - "rv64i_m/I/src/and-01.S", - "rv64i_m/I/src/andi-01.S", - "rv64i_m/I/src/auipc-01.S", - "rv64i_m/I/src/beq-01.S", - "rv64i_m/I/src/bge-01.S", - "rv64i_m/I/src/bgeu-01.S", - "rv64i_m/I/src/blt-01.S", - "rv64i_m/I/src/bltu-01.S", - "rv64i_m/I/src/bne-01.S", - "rv64i_m/I/src/fence-01.S", - "rv64i_m/I/src/jal-01.S", - "rv64i_m/I/src/jalr-01.S", - "rv64i_m/I/src/lb-align-01.S", - "rv64i_m/I/src/lbu-align-01.S", - "rv64i_m/I/src/ld-align-01.S", - "rv64i_m/I/src/lh-align-01.S", - "rv64i_m/I/src/lhu-align-01.S", - "rv64i_m/I/src/lui-01.S", - "rv64i_m/I/src/lw-align-01.S", - "rv64i_m/I/src/lwu-align-01.S", - "rv64i_m/I/src/or-01.S", - "rv64i_m/I/src/ori-01.S", - "rv64i_m/I/src/sb-align-01.S", - "rv64i_m/I/src/sd-align-01.S", - "rv64i_m/I/src/sh-align-01.S", - "rv64i_m/I/src/sll-01.S", - "rv64i_m/I/src/slli-01.S", - "rv64i_m/I/src/slliw-01.S", - "rv64i_m/I/src/sllw-01.S", - "rv64i_m/I/src/slt-01.S", - "rv64i_m/I/src/slti-01.S", - "rv64i_m/I/src/sltiu-01.S", - "rv64i_m/I/src/sltu-01.S", - "rv64i_m/I/src/sra-01.S", - "rv64i_m/I/src/srai-01.S", - "rv64i_m/I/src/sraiw-01.S", - "rv64i_m/I/src/sraw-01.S", - "rv64i_m/I/src/srl-01.S", - "rv64i_m/I/src/srli-01.S", - "rv64i_m/I/src/srliw-01.S", - "rv64i_m/I/src/srlw-01.S", - "rv64i_m/I/src/sub-01.S", - "rv64i_m/I/src/subw-01.S", - "rv64i_m/I/src/sw-align-01.S", - "rv64i_m/I/src/xor-01.S", - "rv64i_m/I/src/xori-01.S", - "rv64i_m/B/src/clmul-01.S", - "rv64i_m/B/src/clmulh-01.S", - "rv64i_m/B/src/clmulr-01.S", - "rv64i_m/B/src/bclr-01.S", - "rv64i_m/B/src/bclri-01.S", - "rv64i_m/B/src/bext-01.S", - "rv64i_m/B/src/bexti-01.S", - "rv64i_m/B/src/binv-01.S", - "rv64i_m/B/src/binvi-01.S", - "rv64i_m/B/src/bset-01.S", - "rv64i_m/B/src/bseti-01.S" -}; - string arch64zba[] = '{ `RISCVARCHTEST, "rv64i_m/B/src/slli.uw-01.S", @@ -1550,8 +1378,6 @@ string arch64b[] = '{ "rv64i_m/B/src/sh3add.uw-01.S" }; - - string arch64zbb[] = '{ `RISCVARCHTEST, "rv64i_m/B/src/max-01.S", @@ -1599,8 +1425,6 @@ string arch64zbs[] = '{ "rv64i_m/B/src/bseti-01.S" }; - - string arch32priv[] = '{ `RISCVARCHTEST, "rv32i_m/privilege/src/ebreak.S", From c426155b762133c32c852c45c1ae6aece14303e7 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Feb 2023 20:42:52 -0800 Subject: [PATCH 100/231] removed bit manipulation from rv[xlen]_i. tests still pass --- config/rv32i/wally-config.vh | 8 ++++---- config/rv64i/wally-config.vh | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/config/rv32i/wally-config.vh b/config/rv32i/wally-config.vh index baee5a829..efbf6e7c0 100644 --- a/config/rv32i/wally-config.vh +++ b/config/rv32i/wally-config.vh @@ -145,10 +145,10 @@ `define DIVCOPIES 32'h4 // bit manipulation -`define ZBA_SUPPORTED 1 -`define ZBB_SUPPORTED 1 -`define ZBC_SUPPORTED 1 -`define ZBS_SUPPORTED 1 +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 // Memory synthesis configuration `define USE_SRAM 0 diff --git a/config/rv64i/wally-config.vh b/config/rv64i/wally-config.vh index 671e36204..a3702c3fd 100644 --- a/config/rv64i/wally-config.vh +++ b/config/rv64i/wally-config.vh @@ -147,10 +147,10 @@ `define DIVCOPIES 32'h4 // bit manipulation -`define ZBA_SUPPORTED 1 -`define ZBB_SUPPORTED 1 -`define ZBC_SUPPORTED 1 -`define ZBS_SUPPORTED 1 +`define ZBA_SUPPORTED 0 +`define ZBB_SUPPORTED 0 +`define ZBC_SUPPORTED 0 +`define ZBS_SUPPORTED 0 // Memory synthesis configuration `define USE_SRAM 0 From 055dbfe8cf1c6a7da72c5a0145dc6fe0dc77ae24 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Feb 2023 20:47:14 -0800 Subject: [PATCH 101/231] removed comment out on stop in testbench --- testbench/testbench.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index eb5014999..756b75f48 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -362,7 +362,7 @@ logic [3:0] dummy; errors = errors+1; $display(" Error on test %s result %d: adr = %h sim (D$) %h sim (DTIM_SUPPORTED) = %h, signature = %h", tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], sig, signature[i]); - //$stop;//***debug + $stop;//***debug end i = i + 1; end From 8b6d6998570c6f82d4c888aba88300dcf36fb45c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 23 Feb 2023 21:57:28 -0800 Subject: [PATCH 102/231] small optimization to condzext select --- src/ieu/alu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index b6e8d0b42..222097e1e 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -64,7 +64,7 @@ module alu #(parameter WIDTH=32) ( if (`ZBA_SUPPORTED) begin: zbamuxes // Zero Extend Mux if (WIDTH == 64) begin - assign CondZextA = (BSelect[3] & (W64 | Funct3[0])) ? {{(32){1'b0}}, A[31:0]} : A; //NOTE: do we move this mux select logic into the Decode Stage? + assign CondZextA = (BSelect[3] & (W64)) ? {{(32){1'b0}}, A[31:0]} : A; //NOTE: do we move this mux select logic into the Decode Stage? end else assign CondZextA = A; // Pre-Shift Mux From 00a0170b30720d72ef7e7d407f026e1258edd99f Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 24 Feb 2023 12:09:34 -0800 Subject: [PATCH 103/231] optimized mux to shifter, passes rv32/64i --- src/ieu/alu.sv | 14 +++- src/ieu/shifternew.sv | 153 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 166 insertions(+), 1 deletion(-) create mode 100644 src/ieu/shifternew.sv diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 222097e1e..7979e065c 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -54,6 +54,7 @@ module alu #(parameter WIDTH=32) ( logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B logic Rotate; + logic [WIDTH:0] shA; // 65 bit input source to shifter if (`ZBS_SUPPORTED) begin: zbsdec @@ -61,6 +62,17 @@ module alu #(parameter WIDTH=32) ( assign CondMaskB = (BSelect[0]) ? MaskB : B; end else assign CondMaskB = B; + + if (WIDTH == 64) begin + always_comb + case ({W64, SubArith}) + 2'b00: shA = {{1'b0}, A}; + 2'b01: shA = {A[63], A}; + 2'b10: shA = {{33'b0}, A[31:0]}; + 2'b11: shA = {{33{A[31]}}, A[31:0]}; + endcase + end else assign shA = (SubArith) ? {A[31], A} : {{1'b0},A}; + if (`ZBA_SUPPORTED) begin: zbamuxes // Zero Extend Mux if (WIDTH == 64) begin @@ -89,7 +101,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts - shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(Rotate)); + shifternew sh(.shA(shA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(Rotate)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign diff --git a/src/ieu/shifternew.sv b/src/ieu/shifternew.sv new file mode 100644 index 000000000..12f2bf999 --- /dev/null +++ b/src/ieu/shifternew.sv @@ -0,0 +1,153 @@ +/////////////////////////////////////////// +// shifter.sv +// +// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu +// Created: 9 January 2021 +// Modified: 6 February 2023 +// +// Purpose: RISC-V 32/64 bit shifter +// +// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3) +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module shifternew ( + input logic [`XLEN:0] shA, // Source + input logic [`LOG_XLEN-1:0] Amt, // Shift amount + input logic Right, Arith, W64, Rotate, // Shift right, arithmetic, RV64 W-type shift + output logic [`XLEN-1:0] Y); // Shifted result + + logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits + logic [`LOG_XLEN-1:0] amttrunc, offset, CondOffsetTrunc; // Shift amount adjusted for RV64, right-shift amount + + + if (`XLEN==32) begin:shifter // RV32 + always_comb // funnel mux + if (Right) z = {{31{shA[32]}}, shA[31:0]}; + else z = {shA[31:0], 31'b0}; + assign amttrunc = Amt; // shift amount + end else begin:shifter // RV64 + always_comb // funnel mux + if (Right) z = {{63{shA[64]}},shA[63:0]}; + else z = {shA[63:0],{63'b0}}; + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + // Handle left and right shifts with a funnel shifter. + // For RV32, only 32-bit shifts are needed. + // For RV64, 32- and 64-bit shifts are needed, with sign extension. + /* + // Funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) + if (`XLEN==32) begin:shifter // RV32 + always_comb // funnel mux + if (Right) + if (Arith) z = {{31{A[31]}}, A}; + else z = {31'b0, A}; + else z = {A, 31'b0}; + assign amttrunc = Amt; // shift amount + end else begin:shifter // RV64 + always_comb // funnel mux + if (W64) begin // 32-bit shifts + if (Right) + if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; + else z = {95'b0, A[31:0]}; + else z = {32'b0, A[31:0], 63'b0}; + end else begin + if (Right) + if (Arith) z = {{63{A[63]}}, A}; + else z = {63'b0, A}; + else z = {A, 63'b0}; + end + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + */ + /* + + if (`ZBB_SUPPORTED) begin: rotFunnel // HANDLES ROTATE + if (`XLEN==32) begin:shifter // RV32 + always_comb // funnel mux + if (Right) + if (Rotate) z = {A[30:0], A[31:0]}; //ror (rv32) + else + if (Arith) z = {{31{A[31]}}, A}; + else z = {31'b0, A}; + else + if (Rotate) z = {A[31:0], A[31:1]}; //rol (rv32) + else z = {A, 31'b0}; + assign amttrunc = Amt; // shift amount + end else begin:shifter // RV64 + always_comb // funnel mux + if (W64) begin // 32-bit shifts + if (Right) + if (Rotate) z = {{64'b0},A[30:0],A[31:0]}; //rorw + else + if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; + else z = {95'b0, A[31:0]}; + else + if (Rotate) z = {{64'b0},A[31:0],A[31:1]}; //rolw + else z = {32'b0, A[31:0], 63'b0}; + end else begin + if (Right) + if (Rotate) z = {A[62:0], A[63:0]}; //ror + else + if (Arith) z = {{63{A[63]}}, A}; + else z = {63'b0, A}; + else + if (Rotate) z = {A[63:0], A[63:1]}; //rol + else z = {A, 63'b0}; + end + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + end else begin: norotFunnel + if (`XLEN==32) begin:shifter // RV32 + always_comb // funnel mux + if (Right) + if (Arith) z = {{31{A[31]}}, A}; + else z = {31'b0, A}; + else z = {A, 31'b0}; + assign amttrunc = Amt; // shift amount + end else begin:shifter // RV64 + always_comb // funnel mux + if (W64) begin // 32-bit shifts + if (Right) + if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; + else z = {95'b0, A[31:0]}; + else z = {32'b0, A[31:0], 63'b0}; + end else begin + if (Right) + if (Arith) z = {{63{A[63]}}, A}; + else z = {63'b0, A}; + else z = {A, 63'b0}; + end + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + end + */ + // Opposite offset for right shifts + assign offset = Right ? amttrunc : ~amttrunc; + //if (`XLEN == 64) assign CondOffsetTrunc = (W64 & Rotate) ? {{1'b0}, offset[4:0]} : offset; + //else assign CondOffsetTrunc = offset; + + // Funnel operation + assign zshift = z >> offset; + assign Y = zshift[`XLEN-1:0]; +endmodule + + From 1d4200e3a36bd24d777e72b3aa339add80ef6eaf Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 24 Feb 2023 17:09:56 -0800 Subject: [PATCH 104/231] took sign extension out of shifter --- src/ieu/alu.sv | 30 ++++++---- src/ieu/shifternew.sv | 128 ++++++++++-------------------------------- 2 files changed, 49 insertions(+), 109 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 7979e065c..46ca2e179 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -54,7 +54,8 @@ module alu #(parameter WIDTH=32) ( logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B logic Rotate; - logic [WIDTH:0] shA; // 65 bit input source to shifter + logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter + logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter if (`ZBS_SUPPORTED) begin: zbsdec @@ -63,15 +64,22 @@ module alu #(parameter WIDTH=32) ( end else assign CondMaskB = B; - if (WIDTH == 64) begin - always_comb - case ({W64, SubArith}) - 2'b00: shA = {{1'b0}, A}; - 2'b01: shA = {A[63], A}; - 2'b10: shA = {{33'b0}, A[31:0]}; - 2'b11: shA = {{33{A[31]}}, A[31:0]}; - endcase - end else assign shA = (SubArith) ? {A[31], A} : {{1'b0},A}; + // Sign/Zero extend mux + if (WIDTH == 64) begin // rv64 must handle word s/z extensions + always_comb + case ({W64, SubArith}) + 2'b00: shA = {{1'b0}, A}; + 2'b01: shA = {A[63], A}; + 2'b10: shA = {{33'b0}, A[31:0]}; + 2'b11: shA = {{33{A[31]}}, A[31:0]}; + endcase + end else assign shA = (SubArith) ? {A[31], A} : {{1'b0},A}; // rv32 does need to handle s/z extensions + + // shifter rotate source select mux + if (`ZBB_SUPPORTED) begin + if (WIDTH == 64) assign rotA = (W64) ? {A[31:0], A[31:0]} : A; + else assign rotA = A; // NOTE: change this for the future! + end else assign rotA = A; if (`ZBA_SUPPORTED) begin: zbamuxes // Zero Extend Mux @@ -101,7 +109,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts - shifternew sh(.shA(shA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .Arith(SubArith), .W64, .Y(Shift), .Rotate(Rotate)); + shifternew sh(.shA(shA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign diff --git a/src/ieu/shifternew.sv b/src/ieu/shifternew.sv index 12f2bf999..e58a12770 100644 --- a/src/ieu/shifternew.sv +++ b/src/ieu/shifternew.sv @@ -30,120 +30,52 @@ `include "wally-config.vh" module shifternew ( - input logic [`XLEN:0] shA, // Source + input logic [`XLEN:0] shA, // shift Source + input logic [`XLEN-1:0] rotA, // rotate source input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Arith, W64, Rotate, // Shift right, arithmetic, RV64 W-type shift + input logic Right, Rotate, W64, // Shift right, rotate signals output logic [`XLEN-1:0] Y); // Shifted result logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] amttrunc, offset, CondOffsetTrunc; // Shift amount adjusted for RV64, right-shift amount + logic [`LOG_XLEN-1:0] amttrunc, offset; // Shift amount adjusted for RV64, right-shift amount - if (`XLEN==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) z = {{31{shA[32]}}, shA[31:0]}; - else z = {shA[31:0], 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (Right) z = {{63{shA[64]}},shA[63:0]}; - else z = {shA[63:0],{63'b0}}; - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - // Handle left and right shifts with a funnel shifter. - // For RV32, only 32-bit shifts are needed. - // For RV64, 32- and 64-bit shifts are needed, with sign extension. - /* - // Funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) - if (`XLEN==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else z = {A, 63'b0}; - end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - */ - /* - - if (`ZBB_SUPPORTED) begin: rotFunnel // HANDLES ROTATE + if (`ZBB_SUPPORTED) begin: rotfunnel + if (`XLEN==32) begin // rv32 with rotates + always_comb // funnel mux + case({Right, Rotate}) + 2'b00: z = {shA[31:0], 31'b0}; + 2'b01: z = {rotA,rotA[31:1]}; + 2'b10: z = {{31{shA[32]}}, shA[31:0]}; + 2'b11: z = {rotA[30:0],rotA}; + endcase + assign amttrunc = Amt; // shift amount + end else begin // rv64 with rotates + always_comb // funnel mux + case ({Right, Rotate}) + 2'b00: z = {shA[63:0],{63'b0}}; + 2'b01: z = {rotA, rotA[63:1]}; + 2'b10: z = {{63{shA[64]}},shA[63:0]}; + 2'b11: z = {rotA[62:0],rotA[63:0]}; + endcase + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + end else begin: norotfunnel if (`XLEN==32) begin:shifter // RV32 always_comb // funnel mux - if (Right) - if (Rotate) z = {A[30:0], A[31:0]}; //ror (rv32) - else - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else - if (Rotate) z = {A[31:0], A[31:1]}; //rol (rv32) - else z = {A, 31'b0}; + if (Right) z = {{31{shA[32]}}, shA[31:0]}; + else z = {shA[31:0], 31'b0}; assign amttrunc = Amt; // shift amount end else begin:shifter // RV64 always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Rotate) z = {{64'b0},A[30:0],A[31:0]}; //rorw - else - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else - if (Rotate) z = {{64'b0},A[31:0],A[31:1]}; //rolw - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Rotate) z = {A[62:0], A[63:0]}; //ror - else - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else - if (Rotate) z = {A[63:0], A[63:1]}; //rol - else z = {A, 63'b0}; - end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - end else begin: norotFunnel - if (`XLEN==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else z = {A, 63'b0}; - end + if (Right) z = {{63{shA[64]}},shA[63:0]}; + else z = {shA[63:0],{63'b0}}; assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end end - */ + // Opposite offset for right shifts assign offset = Right ? amttrunc : ~amttrunc; - //if (`XLEN == 64) assign CondOffsetTrunc = (W64 & Rotate) ? {{1'b0}, offset[4:0]} : offset; - //else assign CondOffsetTrunc = offset; // Funnel operation assign zshift = z >> offset; From 601c6fcdc4c14ec1b2f0a446ab68ad1325bab29e Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 24 Feb 2023 17:14:12 -0800 Subject: [PATCH 105/231] removed now-redundant zero-extend mux in alu --- src/ieu/alu.sv | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 46ca2e179..1fdd06e45 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -78,22 +78,17 @@ module alu #(parameter WIDTH=32) ( // shifter rotate source select mux if (`ZBB_SUPPORTED) begin if (WIDTH == 64) assign rotA = (W64) ? {A[31:0], A[31:0]} : A; - else assign rotA = A; // NOTE: change this for the future! + else assign rotA = A; end else assign rotA = A; if (`ZBA_SUPPORTED) begin: zbamuxes - // Zero Extend Mux - if (WIDTH == 64) begin - assign CondZextA = (BSelect[3] & (W64)) ? {{(32){1'b0}}, A[31:0]} : A; //NOTE: do we move this mux select logic into the Decode Stage? - end else assign CondZextA = A; - // Pre-Shift Mux always_comb case (Funct3[2:1] & {2{BSelect[3]}}) - 2'b00: CondShiftA = CondZextA; - 2'b01: CondShiftA = {CondZextA[WIDTH-2:0],{1'b0}}; // sh1add - 2'b10: CondShiftA = {CondZextA[WIDTH-3:0],{2'b00}}; // sh2add - 2'b11: CondShiftA = {CondZextA[WIDTH-4:0],{3'b000}}; // sh3add + 2'b00: CondShiftA = shA[63:0]; + 2'b01: CondShiftA = {shA[WIDTH-2:0],{1'b0}}; // sh1add + 2'b10: CondShiftA = {shA[WIDTH-3:0],{2'b00}}; // sh2add + 2'b11: CondShiftA = {shA[WIDTH-4:0],{3'b000}}; // sh3add endcase end else assign CondShiftA = A; From f5d3e0e8a08e7235dd6771d8f3cdcdba510f32d8 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 24 Feb 2023 17:33:47 -0800 Subject: [PATCH 106/231] removed old shifter --- src/ieu/alu.sv | 4 +- src/ieu/shifter.sv | 121 ++++++++++++------------------------------ src/ieu/shifternew.sv | 85 ----------------------------- 3 files changed, 35 insertions(+), 175 deletions(-) delete mode 100644 src/ieu/shifternew.sv diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 1fdd06e45..96d8c8f52 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -55,7 +55,7 @@ module alu #(parameter WIDTH=32) ( logic Asign, Bsign; // Sign bits of A, B logic Rotate; logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter - logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter + logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter if (`ZBS_SUPPORTED) begin: zbsdec @@ -85,7 +85,7 @@ module alu #(parameter WIDTH=32) ( // Pre-Shift Mux always_comb case (Funct3[2:1] & {2{BSelect[3]}}) - 2'b00: CondShiftA = shA[63:0]; + 2'b00: CondShiftA = shA[WIDTH-1:0]; 2'b01: CondShiftA = {shA[WIDTH-2:0],{1'b0}}; // sh1add 2'b10: CondShiftA = {shA[WIDTH-3:0],{2'b00}}; // sh2add 2'b11: CondShiftA = {shA[WIDTH-4:0],{3'b000}}; // sh3add diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index feb346ef1..f6cb5bc1c 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // shifter.sv // -// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu +// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, Kevin Kim // Created: 9 January 2021 // Modified: 6 February 2023 // @@ -29,111 +29,56 @@ `include "wally-config.vh" -module shifter ( - input logic [`XLEN-1:0] A, // Source +module shifternew ( + input logic [`XLEN:0] shA, // shift Source + input logic [`XLEN-1:0] rotA, // rotate source input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Arith, W64, Rotate, // Shift right, arithmetic, RV64 W-type shift + input logic Right, Rotate, W64, // Shift right, rotate signals output logic [`XLEN-1:0] Y); // Shifted result logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] amttrunc, offset, CondOffsetTrunc; // Shift amount adjusted for RV64, right-shift amount + logic [`LOG_XLEN-1:0] amttrunc, offset; // Shift amount adjusted for RV64, right-shift amount - // Handle left and right shifts with a funnel shifter. - // For RV32, only 32-bit shifts are needed. - // For RV64, 32- and 64-bit shifts are needed, with sign extension. - /* - // Funnel shifter input (see CMOS VLSI Design 4e Section 11.8.1, note Table 11.11 shift types wrong) - if (`XLEN==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else z = {A, 63'b0}; - end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - */ - if (`ZBB_SUPPORTED) begin: rotFunnel // HANDLES ROTATE + if (`ZBB_SUPPORTED) begin: rotfunnel + if (`XLEN==32) begin // rv32 with rotates + always_comb // funnel mux + case({Right, Rotate}) + 2'b00: z = {shA[31:0], 31'b0}; + 2'b01: z = {rotA,rotA[31:1]}; + 2'b10: z = {{31{shA[32]}}, shA[31:0]}; + 2'b11: z = {rotA[30:0],rotA}; + endcase + assign amttrunc = Amt; // shift amount + end else begin // rv64 with rotates + always_comb // funnel mux + case ({Right, Rotate}) + 2'b00: z = {shA[63:0],{63'b0}}; + 2'b01: z = {rotA, rotA[63:1]}; + 2'b10: z = {{63{shA[64]}},shA[63:0]}; + 2'b11: z = {rotA[62:0],rotA[63:0]}; + endcase + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + end + end else begin: norotfunnel if (`XLEN==32) begin:shifter // RV32 always_comb // funnel mux - if (Right) - if (Rotate) z = {A[30:0], A[31:0]}; //ror (rv32) - else - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else - if (Rotate) z = {A[31:0], A[31:1]}; //rol (rv32) - else z = {A, 31'b0}; + if (Right) z = {{31{shA[32]}}, shA[31:0]}; + else z = {shA[31:0], 31'b0}; assign amttrunc = Amt; // shift amount end else begin:shifter // RV64 always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Rotate) z = {{64'b0},A[30:0],A[31:0]}; //rorw - else - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else - if (Rotate) z = {{64'b0},A[31:0],A[31:1]}; //rolw - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Rotate) z = {A[62:0], A[63:0]}; //ror - else - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else - if (Rotate) z = {A[63:0], A[63:1]}; //rol - else z = {A, 63'b0}; - end - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - end else begin: norotFunnel - if (`XLEN==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) - if (Arith) z = {{31{A[31]}}, A}; - else z = {31'b0, A}; - else z = {A, 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (W64) begin // 32-bit shifts - if (Right) - if (Arith) z = {64'b0, {31{A[31]}}, A[31:0]}; - else z = {95'b0, A[31:0]}; - else z = {32'b0, A[31:0], 63'b0}; - end else begin - if (Right) - if (Arith) z = {{63{A[63]}}, A}; - else z = {63'b0, A}; - else z = {A, 63'b0}; - end + if (Right) z = {{63{shA[64]}},shA[63:0]}; + else z = {shA[63:0],{63'b0}}; assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end end - + // Opposite offset for right shifts assign offset = Right ? amttrunc : ~amttrunc; - if (`XLEN == 64) assign CondOffsetTrunc = (W64 & Rotate) ? {{1'b0}, offset[4:0]} : offset; - else assign CondOffsetTrunc = offset; // Funnel operation - assign zshift = z >> CondOffsetTrunc; + assign zshift = z >> offset; assign Y = zshift[`XLEN-1:0]; endmodule diff --git a/src/ieu/shifternew.sv b/src/ieu/shifternew.sv deleted file mode 100644 index e58a12770..000000000 --- a/src/ieu/shifternew.sv +++ /dev/null @@ -1,85 +0,0 @@ -/////////////////////////////////////////// -// shifter.sv -// -// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu -// Created: 9 January 2021 -// Modified: 6 February 2023 -// -// Purpose: RISC-V 32/64 bit shifter -// -// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.5, Table 4.3) -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module shifternew ( - input logic [`XLEN:0] shA, // shift Source - input logic [`XLEN-1:0] rotA, // rotate source - input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Rotate, W64, // Shift right, rotate signals - output logic [`XLEN-1:0] Y); // Shifted result - - logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] amttrunc, offset; // Shift amount adjusted for RV64, right-shift amount - - - if (`ZBB_SUPPORTED) begin: rotfunnel - if (`XLEN==32) begin // rv32 with rotates - always_comb // funnel mux - case({Right, Rotate}) - 2'b00: z = {shA[31:0], 31'b0}; - 2'b01: z = {rotA,rotA[31:1]}; - 2'b10: z = {{31{shA[32]}}, shA[31:0]}; - 2'b11: z = {rotA[30:0],rotA}; - endcase - assign amttrunc = Amt; // shift amount - end else begin // rv64 with rotates - always_comb // funnel mux - case ({Right, Rotate}) - 2'b00: z = {shA[63:0],{63'b0}}; - 2'b01: z = {rotA, rotA[63:1]}; - 2'b10: z = {{63{shA[64]}},shA[63:0]}; - 2'b11: z = {rotA[62:0],rotA[63:0]}; - endcase - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - end else begin: norotfunnel - if (`XLEN==32) begin:shifter // RV32 - always_comb // funnel mux - if (Right) z = {{31{shA[32]}}, shA[31:0]}; - else z = {shA[31:0], 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (Right) z = {{63{shA[64]}},shA[63:0]}; - else z = {shA[63:0],{63'b0}}; - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - end - - // Opposite offset for right shifts - assign offset = Right ? amttrunc : ~amttrunc; - - // Funnel operation - assign zshift = z >> offset; - assign Y = zshift[`XLEN-1:0]; -endmodule - - From 1506d50c63fa528e3193e36a807b655bafcd0188 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 28 Feb 2023 07:27:34 -0800 Subject: [PATCH 107/231] rename result back to ALUResult in ALU --- src/ieu/alu.sv | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 96d8c8f52..d5f338276 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -37,12 +37,12 @@ module alu #(parameter WIDTH=32) ( input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect input logic [1:0] CompFlags, // Comparator flags - output logic [WIDTH-1:0] Result, // ALU result + output logic [WIDTH-1:0] ALUResult, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult, ZBBResult; // Intermediate results + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,CondExtFullResult, ZBCResult, ZBBResult; // Intermediate results logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux @@ -152,8 +152,8 @@ module alu #(parameter WIDTH=32) ( // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; - else assign ALUResult = FullResult; + if (WIDTH == 64) assign CondExtFullResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + else assign CondExtFullResult = FullResult; //NOTE: This looks good and can be merged. if (`ZBC_SUPPORTED) begin: zbc @@ -161,7 +161,7 @@ module alu #(parameter WIDTH=32) ( end else assign ZBCResult = 0; if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(ALUResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(CondExtFullResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); end else assign ZBBResult = 0; // Final Result B instruction select mux @@ -169,11 +169,11 @@ module alu #(parameter WIDTH=32) ( always_comb case (BSelect) //ZBA_ZBB_ZBC_ZBS - 4'b0001: Result = FullResult; - 4'b0010: Result = ZBCResult; - 4'b1000: Result = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word. - 4'b0100: Result = ZBBResult; - default: Result = ALUResult; + 4'b0001: ALUResult = FullResult; + 4'b0010: ALUResult = ZBCResult; + 4'b1000: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word. + 4'b0100: ALUResult = ZBBResult; + default: ALUResult = CondExtFullResult; endcase - end else assign Result = ALUResult; + end else assign ALUResult = CondExtFullResult; endmodule \ No newline at end of file From 692e406976a120e67b490715fd42add6f2a38f21 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 28 Feb 2023 11:41:40 -0800 Subject: [PATCH 108/231] changed shifter source select signal name --- src/ieu/alu.sv | 5 ++++- src/ieu/controller.sv | 3 ++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index d5f338276..f1bfd912c 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -56,6 +56,9 @@ module alu #(parameter WIDTH=32) ( logic Rotate; logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter + logic [1:0] shASelect; // select signal for shifter source generation mux + + assign shASelect = {W64,SubArith}; if (`ZBS_SUPPORTED) begin: zbsdec @@ -67,7 +70,7 @@ module alu #(parameter WIDTH=32) ( // Sign/Zero extend mux if (WIDTH == 64) begin // rv64 must handle word s/z extensions always_comb - case ({W64, SubArith}) + case (shASelect) 2'b00: shA = {{1'b0}, A}; 2'b01: shA = {A[63], A}; 2'b10: shA = {{33'b0}, A[31:0]}; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 02ef3eeae..2520bbe2d 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -197,7 +197,8 @@ module controller( assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001); assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i - + + //NOTE: Move the B conditional logic into bctrl if (`ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. Only conflict with Funct3 is with slt instructionsb assign sltD = (Funct3D == 3'b010 & (~BSelectD[3])); From b61d881c1bb9f816886f5c2fe2ab2787c37cdd8e Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 28 Feb 2023 11:54:10 -0800 Subject: [PATCH 109/231] added BRegWrite, BW64, BALUOp signals to bctrl and controller -TODO: Main decode in bmuctrl must assert these 3 signals --- src/ieu/bmu/bmuctrl.sv | 11 +++++++---- src/ieu/controller.sv | 5 ++++- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 097ee27e8..0ca949efb 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -38,6 +38,9 @@ module bmuctrl( output logic [2:0] ALUSelectD, // ALU Mux select signal output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? + output logic BRegWriteD, // Indicates if it is a R type B instruction + output logic BW64D, // Indiciates if it is a W type B instruction + output logic BALUOpD, // Indicates if it is an ALU B instruction // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectE, @@ -50,7 +53,7 @@ module bmuctrl( logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs2D; // Rs2 source register in Decode stage - `define BMUCTRLW 10 + `define BMUCTRLW 13 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -64,7 +67,7 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp // ZBS 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) @@ -146,12 +149,12 @@ module bmuctrl( 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110; // min 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110; // minu - default: BMUControlsD = {Funct3D, {7'b0}}; // not B instruction or shift + default: BMUControlsD = {Funct3D, {10'b0}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD} = BMUControlsD; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 2520bbe2d..e39c5cacf 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -121,6 +121,9 @@ module controller( logic IntDivM; // Integer divide instruction logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage logic [2:0] ZBBSelectD; // ZBB Mux Select Signal + logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage + logic BW64D; // Indiciates if it is a W type B instruction in decode stage + logic BALUOpD; // Indicates if it is an ALU B instruction in decode stage // Extract fields @@ -241,7 +244,7 @@ module controller( assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, BW64D, BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; From df0d75034befdebf4753dbc45656e3f7690c1e83 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 28 Feb 2023 12:09:35 -0800 Subject: [PATCH 110/231] bitmanip decoder spits out regwrite, w64, and aluop signals [NEEDS DEBUG] --- src/ieu/bmu/bmuctrl.sv | 108 ++++++++++++++++++++--------------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 0ca949efb..7bc2bbe37 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -69,85 +69,85 @@ module bmuctrl( casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000; // bseti + BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_101; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_101; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_111; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_111; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_111; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111_111; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0100_100_101; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0100_000_101; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_111; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_100_101; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_100_101; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111; // xnor + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_101; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_101; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_101; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_011_101; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_011_101; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110; // minu + BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_101; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_101; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_101; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_101; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_101; // minu default: BMUControlsD = {Funct3D, {10'b0}}; // not B instruction or shift endcase From a5e2e243207f61cd697c67cfe34d483db546a2d7 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 11:22:09 -0800 Subject: [PATCH 111/231] removed redundant zbs --- src/ieu/bmu/zbs.sv | 59 ---------------------------------------------- 1 file changed, 59 deletions(-) delete mode 100644 src/ieu/bmu/zbs.sv diff --git a/src/ieu/bmu/zbs.sv b/src/ieu/bmu/zbs.sv deleted file mode 100644 index 214d6e2c0..000000000 --- a/src/ieu/bmu/zbs.sv +++ /dev/null @@ -1,59 +0,0 @@ -/////////////////////////////////////////// -// zbs.sv -// -// Written: Kevin Kim and Kip Macsai-Goren -// Created: 31 January 2023 -// Modified: -// -// Purpose: RISC-V single bit manipulation unit (ZBS instructions) -// -// Documentation: RISC-V System on Chip Design Chapter *** -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -`include "wally-config.vh" - -module zbs #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands - //input logic [2:0] ALUControl, // With Funct3, indicates operation to perform - input logic [6:0] Funct7, - input logic [2:0] Funct3, // With ***Control, indicates operation to perform - output logic [WIDTH-1:0] ZBSResult); // ZBS result - - logic [WIDTH-1:0] BMask, ClrResult, InvResult, ExtResult, SetResult; - - decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], BMask); - - assign InvResult = A ^ BMask; - assign ClrResult = A & ~BMask; - assign SetResult = A | BMask; - assign ExtResult = {{(WIDTH-1){1'b0}},{|(A & BMask)}}; - - always_comb begin - casez ({Funct7, Funct3}) - 10'b010010?_001: ZBSResult = ClrResult; - 10'b010010?_101: ZBSResult = ExtResult; - 10'b011010?_001: ZBSResult = InvResult; - 10'b001010?_001: ZBSResult = SetResult; - default: ZBSResult = 0; // *** expand to include faults - endcase - end - -endmodule - From e62a7525224ca674eda6d560adf3728e0d100542 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 11:36:12 -0800 Subject: [PATCH 112/231] fixed controller lint, changed byte unit mux select name and input width --- src/ieu/bmu/byte.sv | 5 +++-- src/ieu/bmu/zbb.sv | 2 +- src/ieu/controller.sv | 2 +- 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index efd43d846..2b98b83d6 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -30,7 +30,8 @@ `include "wally-config.vh" module byteUnit #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] A, // Operands + input logic ByteSelect, // LSB of Immediate output logic [WIDTH-1:0] ByteResult); // rev8, orcb result logic [WIDTH-1:0] OrcBResult, Rev8Result; @@ -41,6 +42,6 @@ module byteUnit #(parameter WIDTH=32) ( assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i]; end - assign ByteResult = (B[0]) ? OrcBResult : Rev8Result; + assign ByteResult = (ByteSelect) ? OrcBResult : Rev8Result; endmodule \ No newline at end of file diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 3289d13a4..13529d6a1 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -54,7 +54,7 @@ module zbb #(parameter WIDTH=32) ( logic [WIDTH-1:0] ExtResult; // sign/zero extend result cnt #(WIDTH) cnt(.A(A), .B(B), .W64(W64), .CntResult(CntResult)); - byteUnit #(WIDTH) bu(.A(A), .B(B), .ByteResult(ByteResult)); + byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult)); ext #(WIDTH) ext(.A(A), .B(B), .ExtResult(ExtResult)); diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 7bbc8bf6c..d27af3b4d 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -244,7 +244,7 @@ module controller( assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, BW64D, BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; From 657719220a943616cec42d1a8d825ebba90f8e61 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 11:40:29 -0800 Subject: [PATCH 113/231] zbc select mux optimization --- src/ieu/bmu/zbc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 580cdacca..ad8588462 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -66,7 +66,7 @@ module zbc #(parameter WIDTH=32) ( clmul #(WIDTH) clm(.A(x), .B(y), .ClmulResult(ClmulResult)); bitreverse #(WIDTH) brClmulResult(.a(ClmulResult), .b(RevClmulResult)); - assign ZBCResult = (Funct3 == 3'b011 || Funct3 == 3'b010) ? RevClmulResult : ClmulResult; + assign ZBCResult = (Funct3[1]) ? RevClmulResult : ClmulResult; endmodule \ No newline at end of file From cf324510f31c70ca628a7e1915fa22b9e95e32bf Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 11:43:05 -0800 Subject: [PATCH 114/231] zbc input select mux optimize --- src/ieu/bmu/zbc.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index ad8588462..243ed3967 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -43,16 +43,16 @@ module zbc #(parameter WIDTH=32) ( //NOTE: Optimize this when doing decoder stuff. always_comb begin - casez (Funct3) - 3'b001: begin //clmul + casez (Funct3[1:0]) + 2'b01: begin //clmul x = A; y = B; end - 3'b011: begin //clmulh + 2'b11: begin //clmulh x = {RevA[WIDTH-2:0], {1'b0}}; y = {{1'b0}, RevB[WIDTH-2:0]}; end - 3'b010: begin //clmulr + 2'b10: begin //clmulr x = RevA; y = RevB; end From 5e10720bed5141b2fa358b4b8606dc2f0e77568b Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 11:45:32 -0800 Subject: [PATCH 115/231] rename shifternew to shifter --- src/ieu/alu.sv | 4 ++-- src/ieu/shifter.sv | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index f1bfd912c..4cf8d6ed1 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -106,8 +106,8 @@ module alu #(parameter WIDTH=32) ( assign CondInvB = SubArith ? ~CondMaskB : CondMaskB; assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; - // Shifts - shifternew sh(.shA(shA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); + // Shifts (configurable for rotation) + shifter sh(.shA(shA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index f6cb5bc1c..b784414b9 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" -module shifternew ( +module shifter ( input logic [`XLEN:0] shA, // shift Source input logic [`XLEN-1:0] rotA, // rotate source input logic [`LOG_XLEN-1:0] Amt, // Shift amount From b81a5e4452a7725f742035b611a55415dabe2248 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 12:15:22 -0800 Subject: [PATCH 116/231] added BRegWriteE signal --- src/ieu/bmu/bmuctrl.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 7bc2bbe37..b9df2154a 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -45,7 +45,8 @@ module bmuctrl( input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectE, output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding - output logic [2:0] ZBBSelectE // ZBB mux select signal + output logic [2:0] ZBBSelectE, // ZBB mux select signal + output logic BRegWriteE // Indicates if it is a R type B instruction in Execute ); logic [6:0] OpD; // Opcode in Decode stage @@ -159,5 +160,5 @@ module bmuctrl( // BMU Execute stage pipieline control register - flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD}, {ALUSelectE, BSelectE, ZBBSelectE}); + flopenrc#(11) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE}); endmodule \ No newline at end of file From 0f6050517973e994809544122b04943a183644a3 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 12:15:57 -0800 Subject: [PATCH 117/231] moved SubArith and RegWriteE into configurable block --- src/ieu/controller.sv | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index d27af3b4d..549e23ad8 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -114,6 +114,7 @@ module controller( logic unused; logic BranchFlagE; // Branch flag to use (chosen between eq or lt) logic IEURegWriteE; // Register write + logic BRegWriteE; // Register write from BMU controller in Execute Stage logic IllegalERegAdrD; // RV32E attempts to write upper 16 registers logic [1:0] AtomicE; // Atomic instruction logic FenceD, FenceE, FenceM; // Fence instruction @@ -240,17 +241,26 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand - assign ALUControlD = {W64D, SubArithD, ALUOpD}; + assign ALUControlD = {(W64D | BW64D), SubArithD, ALUOpD}; if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); + + assign RegWriteE = IEURegWriteE | FWriteIntE | BRegWriteE; // IRF register writes could come from IEU, BMU or FPU controllers + assign SubArithD = (ALUOpD | BALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; assign BSelectE = 4'b0000; assign BSelectD = 4'b0000; assign ZBBSelectE = 3'b000; + assign BRegWriteD = 1'b0; + assign BW64D = 1'b0; + assign BALUOpD = 1'b0; + assign BRegWriteE = 1'b0; + + assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); end // Fences @@ -287,7 +297,6 @@ module controller( // Other execute stage controller signals assign MemReadE = MemRWE[1]; assign SCE = (ResultSrcE == 3'b100); - assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers assign IntDivE = MDUE & Funct3E[2]; // Integer division operation // Memory stage pipeline control register From 24b0b83d5290e2246c9a0d6990f6c9134b92e187 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 12:17:03 -0800 Subject: [PATCH 118/231] moved ALUControlD into configurable block --- src/ieu/controller.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 549e23ad8..6911f75ee 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -241,13 +241,13 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign ALUControlD = {(W64D | BW64D), SubArithD, ALUOpD}; if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); assign RegWriteE = IEURegWriteE | FWriteIntE | BRegWriteE; // IRF register writes could come from IEU, BMU or FPU controllers assign SubArithD = (ALUOpD | BALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand + assign ALUControlD = {(W64D | BW64D), SubArithD, ALUOpD}; end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; @@ -261,6 +261,7 @@ module controller( assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); + assign ALUControlD = {W64D, SubArithD, ALUOpD}; end // Fences From b0307f5082c2f0ad74656f775cd4323e764461df Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 13:45:15 -0800 Subject: [PATCH 119/231] formatted bmu decoder --- src/ieu/bmu/bmuctrl.sv | 108 ++++++++++++++++++++--------------------- 1 file changed, 54 insertions(+), 54 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index b9df2154a..e838c6ea1 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -70,85 +70,85 @@ module bmuctrl( casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_101; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_101; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_101; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_101; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_101; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_101; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_101; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_111; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_111; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_111; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_111; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_101; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_111; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100_101; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000_101; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_111; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100_101; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100_101; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_101; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_101; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_101; // xnor + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011_101; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011_101; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_000; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_101; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_101; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_101; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_101; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_101; // minu + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1; // minu default: BMUControlsD = {Funct3D, {10'b0}}; // not B instruction or shift endcase From 3e8e633a560db5996bfde77b6acf9003ac40098a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 13:52:00 -0800 Subject: [PATCH 120/231] zbc comments --- src/ieu/bmu/zbc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 243ed3967..011af80e3 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -41,7 +41,7 @@ module zbc #(parameter WIDTH=32) ( bitreverse #(WIDTH) brA(.a(A), .b(RevA)); bitreverse #(WIDTH) brB(.a(B), .b(RevB)); - //NOTE: Optimize this when doing decoder stuff. + // zbc input select mux always_comb begin casez (Funct3[1:0]) 2'b01: begin //clmul From 05b329dd6ad8eb7870370c29f3cbbe3a1c7c8d16 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 15:09:55 -0800 Subject: [PATCH 121/231] added bitmanip illegal instruction signal --- src/ieu/bmu/bmuctrl.sv | 115 +++++++++++++++++++++-------------------- src/ieu/controller.sv | 8 ++- 2 files changed, 64 insertions(+), 59 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index e838c6ea1..145b2513d 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -41,6 +41,7 @@ module bmuctrl( output logic BRegWriteD, // Indicates if it is a R type B instruction output logic BW64D, // Indiciates if it is a W type B instruction output logic BALUOpD, // Indicates if it is an ALU B instruction + output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectE, @@ -54,7 +55,7 @@ module bmuctrl( logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs2D; // Rs2 source register in Decode stage - `define BMUCTRLW 13 + `define BMUCTRLW 14 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -70,92 +71,92 @@ module bmuctrl( casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1; // xnor + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1; // minu + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0; // minu - default: BMUControlsD = {Funct3D, {10'b0}}; // not B instruction or shift + default: BMUControlsD = {Funct3D, {10'b0}, {1'b1}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, IllegalBitmanipInstrD} = BMUControlsD; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 6911f75ee..eaf289896 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -116,6 +116,7 @@ module controller( logic IEURegWriteE; // Register write logic BRegWriteE; // Register write from BMU controller in Execute Stage logic IllegalERegAdrD; // RV32E attempts to write upper 16 registers + logic IllegalBitmanipInstrD; // Unrecognized B instruction logic [1:0] AtomicE; // Atomic instruction logic FenceD, FenceE, FenceM; // Fence instruction logic SFenceVmaD; // sfence.vma instruction @@ -191,7 +192,8 @@ module controller( // Squash control signals if coming from an illegal compressed instruction // On RV32E, can't write to upper 16 registers. Checking reads to upper 16 is more costly so disregard them. assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; - assign IllegalBaseInstrD = ControlsD[0] | IllegalERegAdrD; + assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ; //NOTE: Do we want to segregate the IllegalBitmanipInstrD into its own output signal + //assign IllegalBaseInstrD = 1'b0; assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD, ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD, PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD; @@ -243,7 +245,7 @@ module controller( assign sraD = (Funct3D == 3'b101 & Funct7D[5]); if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); assign RegWriteE = IEURegWriteE | FWriteIntE | BRegWriteE; // IRF register writes could come from IEU, BMU or FPU controllers assign SubArithD = (ALUOpD | BALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand @@ -262,6 +264,8 @@ module controller( assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); assign ALUControlD = {W64D, SubArithD, ALUOpD}; + + assign IllegalBitmanipInstrD = 1'b1; end // Fences From 910eeea3ffedf0f4d5c5c46c11c6b5f3f3b42eff Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 15:28:33 -0800 Subject: [PATCH 122/231] removed main instruction decoder dependence on bmu controller --- src/ieu/controller.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index eaf289896..324b255b5 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -162,14 +162,14 @@ module controller( ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo end else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction - 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | ((`ZBB_SUPPORTED & BSelectD[2]) | (`ZBC_SUPPORTED & BSelectD[1]) | (`ZBS_SUPPORTED & BSelectD[0]) | (`ZBA_SUPPORTED & BSelectD[3]))) + 7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type else if (Funct7D == 7'b0000001 & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2]))) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction 7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui - 7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000 | (`ZBA_SUPPORTED & BSelectD[3]) | (`ZBB_SUPPORTED & BSelectD[2])) & `XLEN == 64) + 7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000) & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i else if (Funct7D == 7'b0000001 & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])) & `XLEN == 64) ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide From c9bd37c92bfada6ee04dc4b3239e72a40300f33c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 15:28:43 -0800 Subject: [PATCH 123/231] formatting --- src/ieu/alu.sv | 10 +++++----- src/ieu/bmu/bmuctrl.sv | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 4cf8d6ed1..a22a3a02b 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -58,15 +58,18 @@ module alu #(parameter WIDTH=32) ( logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter logic [1:0] shASelect; // select signal for shifter source generation mux - assign shASelect = {W64,SubArith}; + // Extract control signals from ALUControl. + assign {W64, SubArith, ALUOp} = ALUControl; + + // Pack control signals into shifter select + assign shASelect = {W64,SubArith}; if (`ZBS_SUPPORTED) begin: zbsdec decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); assign CondMaskB = (BSelect[0]) ? MaskB : B; end else assign CondMaskB = B; - // Sign/Zero extend mux if (WIDTH == 64) begin // rv64 must handle word s/z extensions always_comb @@ -99,9 +102,6 @@ module alu #(parameter WIDTH=32) ( assign Rotate = BSelect[2] & (ALUSelect == 3'b001); //NOTE: Do we want to move this logic into the Decode Stage? end else assign Rotate = 1'b0; - // Extract control signals from ALUControl. - assign {W64, SubArith, ALUOp} = ALUControl; - // Addition assign CondInvB = SubArith ? ~CondMaskB : CondMaskB; assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 145b2513d..9b3e3a97b 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -69,7 +69,7 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_IllegalBitmanipInstrD // ZBS 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) From b21ca2fba0ec7d288536d17d0f9c75625edb8305 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 2 Mar 2023 16:00:56 -0800 Subject: [PATCH 124/231] bug fix, more elegant logic changes in controller --- src/ieu/controller.sv | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 324b255b5..e41a73ad7 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -91,6 +91,8 @@ module controller( logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file logic [1:0] MemRWD, MemRWE; // Store (write to memory) logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) + logic BaseALUOpD, BaseW64D; // ALU operation and W64 for Base instructions specifically + logic BaseRegWriteD; // Indicates if Base instruction register write instruction logic [2:0] ALUControlD; // Determines ALU operation logic [2:0] ALUSelectD; // ALU mux select signal logic ALUSrcAD, ALUSrcBD; // ALU inputs @@ -137,7 +139,7 @@ module controller( // Main Instruction Decoder always_comb case(OpD) - // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal + // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_BaseALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal 7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Illegal instruction 7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw 7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported @@ -194,9 +196,14 @@ module controller( assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ; //NOTE: Do we want to segregate the IllegalBitmanipInstrD into its own output signal //assign IllegalBaseInstrD = 1'b0; - assign {RegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD, - ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, W64D, CSRReadD, + assign {BaseRegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD, + ResultSrcD, BranchD, BaseALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD; + + // If either bitmanip signal or base instruction signal + assign ALUOpD = BaseALUOpD | BALUOpD; + assign RegWriteD = BaseRegWriteD | BRegWriteD; + assign W64D = BaseW64D | BW64D; assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source? @@ -243,13 +250,13 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); + assign ALUControlD = {W64D, SubArithD, ALUOpD}; + // BITMANIP Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); - assign RegWriteE = IEURegWriteE | FWriteIntE | BRegWriteE; // IRF register writes could come from IEU, BMU or FPU controllers - assign SubArithD = (ALUOpD | BALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand - assign ALUControlD = {(W64D | BW64D), SubArithD, ALUOpD}; + assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; @@ -261,9 +268,7 @@ module controller( assign BALUOpD = 1'b0; assign BRegWriteE = 1'b0; - assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); - assign ALUControlD = {W64D, SubArithD, ALUOpD}; assign IllegalBitmanipInstrD = 1'b1; end @@ -302,6 +307,7 @@ module controller( // Other execute stage controller signals assign MemReadE = MemRWE[1]; assign SCE = (ResultSrcE == 3'b100); + assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers assign IntDivE = MDUE & Funct3E[2]; // Integer division operation // Memory stage pipeline control register From 2c3271dd62e960fad41deaa39041ce4b52341243 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 08:27:11 -0800 Subject: [PATCH 125/231] began subarith configurability optimization in controller --- src/ieu/controller.sv | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index e41a73ad7..0e5f30792 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -93,6 +93,7 @@ module controller( logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) logic BaseALUOpD, BaseW64D; // ALU operation and W64 for Base instructions specifically logic BaseRegWriteD; // Indicates if Base instruction register write instruction + logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu logic [2:0] ALUControlD; // Determines ALU operation logic [2:0] ALUSelectD; // ALU mux select signal logic ALUSrcAD, ALUSrcBD; // ALU inputs @@ -106,7 +107,7 @@ module controller( logic PrivilegedD, PrivilegedE; // Privileged instruction logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$ logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals - logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu + logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions logic bclrD, bextD; // Indicates if is one of these instructions logic andnD, ornD, xnorD; // Indicates if is one of these instructions @@ -128,6 +129,7 @@ module controller( logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage logic BW64D; // Indiciates if it is a W type B instruction in decode stage logic BALUOpD; // Indicates if it is an ALU B instruction in decode stage + logic BSubArithD; // TRUE for B-type ext, clr, andn, orn, xnor // Extract fields @@ -250,6 +252,7 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); + assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand assign ALUControlD = {W64D, SubArithD, ALUOpD}; // BITMANIP Configuration Block @@ -267,6 +270,7 @@ module controller( assign BW64D = 1'b0; assign BALUOpD = 1'b0; assign BRegWriteE = 1'b0; + assign BSubArithD = 1'b0; assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); From 19410b4196a9b29e385a1933c046edd27ecb7fbc Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 08:40:29 -0800 Subject: [PATCH 126/231] migrated B-subarith logic into b controller --- src/ieu/bmu/bmuctrl.sv | 117 +++++++++++++++++++++-------------------- src/ieu/controller.sv | 8 +-- 2 files changed, 63 insertions(+), 62 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 9b3e3a97b..2a4a450e2 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -41,6 +41,7 @@ module bmuctrl( output logic BRegWriteD, // Indicates if it is a R type B instruction output logic BW64D, // Indiciates if it is a W type B instruction output logic BALUOpD, // Indicates if it is an ALU B instruction + output logic BSubArithD, // Indicates if Bitmanip SubArith flag should be on output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage @@ -55,7 +56,7 @@ module bmuctrl( logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs2D; // Rs2 source register in Decode stage - `define BMUCTRLW 14 + `define BMUCTRLW 15 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -69,94 +70,94 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_IllegalBitmanipInstrD + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_IllegalBitmanipInstrD // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_0; // xnor + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_1; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0; // minu + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0; // minu - default: BMUControlsD = {Funct3D, {10'b0}, {1'b1}}; // not B instruction or shift + default: BMUControlsD = {Funct3D, {11'b0}, {1'b1}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, IllegalBitmanipInstrD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, IllegalBitmanipInstrD} = BMUControlsD; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 0e5f30792..2cee4183a 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -206,6 +206,7 @@ module controller( assign ALUOpD = BaseALUOpD | BALUOpD; assign RegWriteD = BaseRegWriteD | BRegWriteD; assign W64D = BaseW64D | BW64D; + assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source? @@ -252,14 +253,14 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand + assign BaseSubArithD = ALUOpD & (subD | sraD | sltD | sltuD); assign ALUControlD = {W64D, SubArithD, ALUOpD}; // BITMANIP Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); - assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand + //assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; @@ -272,7 +273,6 @@ module controller( assign BRegWriteE = 1'b0; assign BSubArithD = 1'b0; - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD); assign IllegalBitmanipInstrD = 1'b1; end From 9cad890c1a69fe55ee488a89762880c3d9115108 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 08:41:47 -0800 Subject: [PATCH 127/231] comments to bctrl --- src/ieu/bmu/bmuctrl.sv | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 2a4a450e2..527a2428b 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -35,14 +35,14 @@ module bmuctrl( // Decode stage control signals input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage - output logic [2:0] ALUSelectD, // ALU Mux select signal + output logic [2:0] ALUSelectD, // ALU Mux select signal in Decode Stage output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? - output logic BRegWriteD, // Indicates if it is a R type B instruction - output logic BW64D, // Indiciates if it is a W type B instruction - output logic BALUOpD, // Indicates if it is an ALU B instruction - output logic BSubArithD, // Indicates if Bitmanip SubArith flag should be on - output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction + output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage + output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage + output logic BALUOpD, // Indicates if it is an ALU B instruction in Decode Stage + output logic BSubArithD, // TRUE if ext, clr, andn, orn, xnor instruction in Decode Stage + output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction in Decode Stage // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectE, @@ -156,7 +156,6 @@ module bmuctrl( endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, IllegalBitmanipInstrD} = BMUControlsD; From 422b428cba1b75816c32d23fe7514c8e3fb77e67 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 08:45:42 -0800 Subject: [PATCH 128/231] removed outdated b-signals in controller --- src/ieu/controller.sv | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 2cee4183a..f8b0d983f 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -109,8 +109,6 @@ module controller( logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions - logic bclrD, bextD; // Indicates if is one of these instructions - logic andnD, ornD, xnorD; // Indicates if is one of these instructions logic maxE, maxuE, minE, minuE; // Indicates if is one of these instructions in Execute Stage logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs @@ -222,27 +220,13 @@ module controller( assign sltD = (Funct3D == 3'b010); end - if (`ZBS_SUPPORTED) begin - assign bclrD = (ALUSelectD == 3'b111 & BSelectD[0]); - assign bextD = (ALUSelectD == 3'b101 & BSelectD[0]); - end else begin - assign bclrD = 1'b0; - assign bextD = 1'b0; - end - if (`ZBB_SUPPORTED) begin - assign andnD = (ALUSelectD == 3'b111 & BSelectD[2]); - assign ornD = (ALUSelectD == 3'b110 & BSelectD[2]); - assign xnorD = (ALUSelectD == 3'b100 & BSelectD[2]); // we only need these signals if we want to calculate a signedD flag in decode stage to pass to the comparator. assign maxE = (Funct3E[1:0] == 2'b10 & BSelectE[2]); assign maxuE = (Funct3E[1:0] == 2'b11 & BSelectE[2]); assign minE = (Funct3E[1:0] == 2'b00 & BSelectE[2]); assign minuE = (Funct3E[1:0] == 2'b01 & BSelectE[2]); end else begin - assign andnD = 0; - assign ornD = 0; - assign xnorD = 0; assign maxE = 0; assign maxuE = 0; assign minE = 0; From c836eea17c1ad9a7d0962a2199235cc5ff6b5bd7 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 12:35:40 -0800 Subject: [PATCH 129/231] sltD logic optimize --- src/ieu/controller.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index e20d29aeb..4c8376d75 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -216,7 +216,7 @@ module controller( //NOTE: Move the B conditional logic into bctrl if (`ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. Only conflict with Funct3 is with slt instructionsb - assign sltD = (Funct3D == 3'b010 & (~BSelectD[3])); + assign sltD = (Funct3D == 3'b010 & ~(Funct7D[4])); end else begin assign sltD = (Funct3D == 3'b010); end From 5e01f86bc52eeaf7ce34d66aafced58a30f12e4d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 12:44:33 -0800 Subject: [PATCH 130/231] sltD signal debug. Passes regression --- src/ieu/controller.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 4c8376d75..ec54394e8 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -215,8 +215,8 @@ module controller( //NOTE: Move the B conditional logic into bctrl if (`ZBA_SUPPORTED) begin - // ALU Decoding is more comprehensive when ZBA is supported. Only conflict with Funct3 is with slt instructionsb - assign sltD = (Funct3D == 3'b010 & ~(Funct7D[4])); + // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw + assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; end else begin assign sltD = (Funct3D == 3'b010); end From 8dd39fbcfba48db86adb0a807f8db840c3f6e761 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 17:12:29 -0800 Subject: [PATCH 131/231] b controller generates comparison signed flag and controller branch signed logic updated accordingly --- src/ieu/bmu/bmuctrl.sv | 9 +++++++-- src/ieu/controller.sv | 11 +++++++---- 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 527a2428b..3ee6c42ee 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -48,13 +48,15 @@ module bmuctrl( output logic [2:0] ALUSelectE, output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding output logic [2:0] ZBBSelectE, // ZBB mux select signal - output logic BRegWriteE // Indicates if it is a R type B instruction in Execute + output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute + output logic BComparatorSignedE // Indicates if comparator signed in Execute Stage ); logic [6:0] OpD; // Opcode in Decode stage logic [2:0] Funct3D; // Funct3 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs2D; // Rs2 source register in Decode stage + logic BComparatorSignedD; // Indicates if comparator signed (max, min instruction) in Decode Stage `define BMUCTRLW 15 @@ -158,8 +160,11 @@ module bmuctrl( // Unpack Control Signals assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, IllegalBitmanipInstrD} = BMUControlsD; + // Comparator should perform signed comparison when min/max instruction. We have overlap in funct3 with some branch instructions so we use opcode to differentiate betwen min/max and branches + assign BComparatorSignedD = (Funct3D[2]^Funct3D[0]) & ~OpD[6]; + // BMU Execute stage pipieline control register - flopenrc#(11) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE}); + flopenrc#(12) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE}); endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index ec54394e8..9ea091e30 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -126,9 +126,10 @@ module controller( logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage logic [2:0] ZBBSelectD; // ZBB Mux Select Signal logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage - logic BW64D; // Indiciates if it is a W type B instruction in decode stage + logic BW64D; // Indicates if it is a W type B instruction in decode stage logic BALUOpD; // Indicates if it is an ALU B instruction in decode stage logic BSubArithD; // TRUE for B-type ext, clr, andn, orn, xnor + logic BComparatorSignedE; // Indicates if max, min (signed comarison) instruction in Execute Stage // Extract fields @@ -243,7 +244,8 @@ module controller( // BITMANIP Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE); + //assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand end else begin: bitmanipi @@ -257,6 +259,7 @@ module controller( assign BALUOpD = 1'b0; assign BRegWriteE = 1'b0; assign BSubArithD = 1'b0; + assign BComparatorSignedE = 1'b0; assign IllegalBitmanipInstrD = 1'b1; @@ -286,8 +289,8 @@ module controller( // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE // Hence, only eq and lt flags are needed - assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & ~BSelectE[2]) | (`ZBB_SUPPORTED & (maxE | minE)) ; - //assign BranchSignedE = ~(Funct3E[2:1] == 2'b11); + // We also want comparator to handle signed comparison on a max/min bitmanip instruction + assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & BranchE) | BComparatorSignedE ; assign {eqE, ltE} = FlagsE; mux2 #(1) branchflagmux(eqE, ltE, Funct3E[2], BranchFlagE); assign BranchTakenE = BranchFlagE ^ Funct3E[0]; From 0403cfd41a2f76cb4ed551bb566b7dc55cb7522b Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 21:52:25 -0800 Subject: [PATCH 132/231] removed redundant signals in controller --- src/ieu/controller.sv | 31 +++++++++---------------------- 1 file changed, 9 insertions(+), 22 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 9ea091e30..b76421d4e 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -1,9 +1,9 @@ /////////////////////////////////////////// // controller.sv // -// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu +// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu // Created: 9 January 2021 -// Modified: +// Modified: 3 March 2023 // // Purpose: Top level controller module // @@ -110,7 +110,6 @@ module controller( logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions - logic maxE, maxuE, minE, minuE; // Indicates if is one of these instructions in Execute Stage logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; @@ -215,25 +214,8 @@ module controller( assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i //NOTE: Move the B conditional logic into bctrl - if (`ZBA_SUPPORTED) begin - // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw - assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; - end else begin - assign sltD = (Funct3D == 3'b010); - end + - if (`ZBB_SUPPORTED) begin - // we only need these signals if we want to calculate a signedD flag in decode stage to pass to the comparator. - assign maxE = (Funct3E[1:0] == 2'b10 & BSelectE[2]); - assign maxuE = (Funct3E[1:0] == 2'b11 & BSelectE[2]); - assign minE = (Funct3E[1:0] == 2'b00 & BSelectE[2]); - assign minuE = (Funct3E[1:0] == 2'b01 & BSelectE[2]); - end else begin - assign maxE = 0; - assign maxuE = 0; - assign minE = 0; - assign minuE = 0; - end // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra assign sltuD = (Funct3D == 3'b011); @@ -245,7 +227,10 @@ module controller( // BITMANIP Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE); - + if (`ZBA_SUPPORTED) begin + // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw + assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; + end else assign sltD = (Funct3D == 3'b010); //assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand end else begin: bitmanipi @@ -261,6 +246,8 @@ module controller( assign BSubArithD = 1'b0; assign BComparatorSignedE = 1'b0; + assign sltD = (Funct3D == 3'b010); + assign IllegalBitmanipInstrD = 1'b1; end From b315066b03349dc32287b2664a22eba10909b384 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 21:52:34 -0800 Subject: [PATCH 133/231] license comments --- src/ieu/alu.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index a22a3a02b..9843cea67 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -1,9 +1,9 @@ /////////////////////////////////////////// // alu.sv // -// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu +// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu, kekim@hmc.edu // Created: 9 January 2021 -// Modified: +// Modified: 3 March 2023 // // Purpose: RISC-V Arithmetic/Logic Unit // From 72de867e65db7b60c0a49d866ccd0cc1cb9c4fd9 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 3 Mar 2023 22:57:49 -0800 Subject: [PATCH 134/231] Rotate signal now gets generated in bmu ctrl --- src/ieu/alu.sv | 6 +- src/ieu/bmu/bmuctrl.sv | 123 +++++++++++++++++++++-------------------- src/ieu/controller.sv | 8 +-- src/ieu/datapath.sv | 3 +- src/ieu/ieu.sv | 7 ++- 5 files changed, 72 insertions(+), 75 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 9843cea67..3e5642262 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -37,6 +37,7 @@ module alu #(parameter WIDTH=32) ( input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect input logic [1:0] CompFlags, // Comparator flags + input logic Rotate, // Perform Rotate Operation output logic [WIDTH-1:0] ALUResult, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands @@ -53,7 +54,6 @@ module alu #(parameter WIDTH=32) ( logic SubArith; // Performing subtraction or arithmetic right shift logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B - logic Rotate; logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter logic [1:0] shASelect; // select signal for shifter source generation mux @@ -98,10 +98,6 @@ module alu #(parameter WIDTH=32) ( endcase end else assign CondShiftA = A; - if (`ZBB_SUPPORTED) begin: rotatelogic - assign Rotate = BSelect[2] & (ALUSelect == 3'b001); //NOTE: Do we want to move this logic into the Decode Stage? - end else assign Rotate = 1'b0; - // Addition assign CondInvB = SubArith ? ~CondMaskB : CondMaskB; assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 3ee6c42ee..8fe3cb75a 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -49,7 +49,8 @@ module bmuctrl( output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding output logic [2:0] ZBBSelectE, // ZBB mux select signal output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute - output logic BComparatorSignedE // Indicates if comparator signed in Execute Stage + output logic BComparatorSignedE, // Indicates if comparator signed in Execute Stage + output logic RotateE // Indiciates if rotate instruction in Execute Stage ); logic [6:0] OpD; // Opcode in Decode stage @@ -57,8 +58,9 @@ module bmuctrl( logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs2D; // Rs2 source register in Decode stage logic BComparatorSignedD; // Indicates if comparator signed (max, min instruction) in Decode Stage + logic RotateD; // Indicates if rotate instruction in Decode Stage - `define BMUCTRLW 15 + `define BMUCTRLW 16 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -72,93 +74,92 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_IllegalBitmanipInstrD + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_RotateD_IllegalBitmanipInstrD // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_0; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_0; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_0; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_0; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_0; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_0; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0_0; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0_0; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_0; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_0; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0_0; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0; // xnor + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0; // minu - - default: BMUControlsD = {Funct3D, {11'b0}, {1'b1}}; // not B instruction or shift + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0_0; // minu + default: BMUControlsD = {Funct3D, {12'b0}, {1'b1}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, IllegalBitmanipInstrD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, RotateD, IllegalBitmanipInstrD} = BMUControlsD; // Comparator should perform signed comparison when min/max instruction. We have overlap in funct3 with some branch instructions so we use opcode to differentiate betwen min/max and branches assign BComparatorSignedD = (Funct3D[2]^Funct3D[0]) & ~OpD[6]; @@ -166,5 +167,5 @@ module bmuctrl( // BMU Execute stage pipieline control register - flopenrc#(12) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE}); + flopenrc#(13) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, RotateD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, RotateE}); endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index b76421d4e..b2e21ebf7 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -60,6 +60,7 @@ module controller( output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction output logic [2:0] ZBBSelectE, // ZBB mux select signal in Execute stage + output logic RotateE, // Indicates if rotate instruction in Execute Stage // Memory stage control signals input logic StallM, FlushM, // Stall, flush Memory stage output logic [1:0] MemRWM, // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write @@ -129,7 +130,6 @@ module controller( logic BALUOpD; // Indicates if it is an ALU B instruction in decode stage logic BSubArithD; // TRUE for B-type ext, clr, andn, orn, xnor logic BComparatorSignedE; // Indicates if max, min (signed comarison) instruction in Execute Stage - // Extract fields assign OpD = InstrD[6:0]; @@ -213,9 +213,6 @@ module controller( assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001); assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i - //NOTE: Move the B conditional logic into bctrl - - // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra assign sltuD = (Funct3D == 3'b011); @@ -226,7 +223,7 @@ module controller( // BITMANIP Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .RotateE); if (`ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; @@ -245,6 +242,7 @@ module controller( assign BRegWriteE = 1'b0; assign BSubArithD = 1'b0; assign BComparatorSignedE = 1'b0; + assign RotateE = 1'b0; assign sltD = (Funct3D == 3'b010); diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 9f09efe77..19057fcb7 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -48,6 +48,7 @@ module datapath ( input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelectE, // ZBB mux select signal + input logic RotateE, // Indicates if Rotate instruction in Execute Stage output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B @@ -112,7 +113,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, RotateE, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index e26622f96..88a83ea66 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -86,7 +86,8 @@ module ieu ( logic FWriteIntM; // FPU writing to integer register file logic IntDivW; // Integer divide instruction logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding - logic [2:0] ZBBSelectE; + logic [2:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage + logic RotateE; // Indicates if Rotate Instruction in Execute Stage // Forwarding signals logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers @@ -100,7 +101,7 @@ controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, - .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .StallM, .FlushM, .MemRWM, + .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .RotateE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .FenceM, .StoreStallD); @@ -108,7 +109,7 @@ controller c( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, - .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, + .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .RotateE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); From f5dca0bf4f0169bec7890168c42effef8432ed53 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 4 Mar 2023 09:22:21 -0800 Subject: [PATCH 135/231] zbc result mux is now structural --- src/ieu/bmu/zbc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 011af80e3..74b2f64b6 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -66,7 +66,7 @@ module zbc #(parameter WIDTH=32) ( clmul #(WIDTH) clm(.A(x), .B(y), .ClmulResult(ClmulResult)); bitreverse #(WIDTH) brClmulResult(.a(ClmulResult), .b(RevClmulResult)); - assign ZBCResult = (Funct3[1]) ? RevClmulResult : ClmulResult; + mux2 #(WIDTH) zbcresultmux(ClmulResult, RevClmulResult, Funct3[1], ZBCResult); endmodule \ No newline at end of file From 9494cf9340af7c797ee1c2bcdd7b9d09446f8455 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 4 Mar 2023 22:44:03 -0800 Subject: [PATCH 136/231] removed rotate signal in datapath and instead packed into the new BALUControl Signal - BALUControl contains Rotate, Mask, PreShift signals to select from the respective generation muxes in the ALU --- src/ieu/alu.sv | 30 ++++++---- src/ieu/bmu/bmuctrl.sv | 130 +++++++++++++++++++++-------------------- src/ieu/controller.sv | 7 ++- src/ieu/datapath.sv | 6 +- src/ieu/ieu.sv | 8 +-- 5 files changed, 96 insertions(+), 85 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 3e5642262..dea870227 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -30,16 +30,16 @@ `include "wally-config.vh" module alu #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands - input logic [2:0] ALUControl, // With Funct3, indicates operation to perform - input logic [2:0] ALUSelect, // ALU mux select signal - input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction - input logic [2:0] ZBBSelect, // ZBB mux select signal - input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect - input logic [1:0] CompFlags, // Comparator flags - input logic Rotate, // Perform Rotate Operation - output logic [WIDTH-1:0] ALUResult, // ALU result - output logic [WIDTH-1:0] Sum); // Sum of operands + input logic [WIDTH-1:0] A, B, // Operands + input logic [2:0] ALUControl, // With Funct3, indicates operation to perform + input logic [2:0] ALUSelect, // ALU mux select signal + input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction + input logic [2:0] ZBBSelect, // ZBB mux select signal + input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect + input logic [1:0] CompFlags, // Comparator flags + input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage + output logic [WIDTH-1:0] ALUResult, // ALU result + output logic [WIDTH-1:0] Sum); // Sum of operands // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. @@ -57,17 +57,23 @@ module alu #(parameter WIDTH=32) ( logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter logic [1:0] shASelect; // select signal for shifter source generation mux + logic Rotate; // Indicates if it is Rotate instruction + logic Mask; // Indicates if it is ZBS instruction + logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; + // Extract control signals from bitmanip ALUControl. + assign {Rotate, Mask, PreShift} = BALUControl; + // Pack control signals into shifter select assign shASelect = {W64,SubArith}; if (`ZBS_SUPPORTED) begin: zbsdec decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); - assign CondMaskB = (BSelect[0]) ? MaskB : B; + assign CondMaskB = (Mask) ? MaskB : B; end else assign CondMaskB = B; // Sign/Zero extend mux @@ -90,7 +96,7 @@ module alu #(parameter WIDTH=32) ( if (`ZBA_SUPPORTED) begin: zbamuxes // Pre-Shift Mux always_comb - case (Funct3[2:1] & {2{BSelect[3]}}) + case (Funct3[2:1] & {2{PreShift}}) 2'b00: CondShiftA = shA[WIDTH-1:0]; 2'b01: CondShiftA = {shA[WIDTH-2:0],{1'b0}}; // sh1add 2'b10: CondShiftA = {shA[WIDTH-3:0],{2'b00}}; // sh2add diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 8fe3cb75a..b9fb539a7 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -1,11 +1,11 @@ /////////////////////////////////////////// -// controller.sv +// bmuctrl.sv // // Written: Kevin Kim // Created: 16 February 2023 // Modified: // -// Purpose: Top level B instrution controller module +// Purpose: Top level B instruction decoder // // Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) // @@ -50,7 +50,8 @@ module bmuctrl( output logic [2:0] ZBBSelectE, // ZBB mux select signal output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute output logic BComparatorSignedE, // Indicates if comparator signed in Execute Stage - output logic RotateE // Indiciates if rotate instruction in Execute Stage + output logic [2:0] BALUControlE // ALU Control signals for B instructions in Execute Stage + ); logic [6:0] OpD; // Opcode in Decode stage @@ -59,8 +60,10 @@ module bmuctrl( logic [4:0] Rs2D; // Rs2 source register in Decode stage logic BComparatorSignedD; // Indicates if comparator signed (max, min instruction) in Decode Stage logic RotateD; // Indicates if rotate instruction in Decode Stage - - `define BMUCTRLW 16 + logic MaskD; // Indicates if zbs instruction in Decode Stage + logic PreShiftD; // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage + logic [2:0] BALUControlD; // ALU Control signals for B instructions + `define BMUCTRLW 18 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -74,92 +77,93 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_RotateD_IllegalBitmanipInstrD + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_0; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_1_0_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_0; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_1_0_0; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_0; // bexti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_1_0_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_0; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_1_0_0; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_0; // binvi + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_1_0_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_0; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_1_0_0; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_0; // bseti + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_1_0_0; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_0; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_1_0_0; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_0; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0_0; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_1_0_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_1_0_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_1_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_1_0_0; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0_0_0_0; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0_0; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0_0_0_0; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0_0; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0_1_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0_1_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0_1_0; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_1_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_1_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_1_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0_0_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0_0_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0_0_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0; // roriw + BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0_0_0; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0_0_0; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0_0; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0_0; // count word instruction + BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0_0_0_0; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0_0_0; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0_0_0; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0_0; // xnor + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0_0_0_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0_0_0; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0_0_0; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_0100_110_1_0_1_0_0_0; // minu - default: BMUControlsD = {Funct3D, {12'b0}, {1'b1}}; // not B instruction or shift + BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0_0_0; // maxu + default: BMUControlsD = {Funct3D, {14'b0}, {1'b1}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, RotateD, IllegalBitmanipInstrD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD; + + // Pack BALUControl Signals + assign BALUControlD = {RotateD, MaskD, PreShiftD}; // Comparator should perform signed comparison when min/max instruction. We have overlap in funct3 with some branch instructions so we use opcode to differentiate betwen min/max and branches assign BComparatorSignedD = (Funct3D[2]^Funct3D[0]) & ~OpD[6]; @@ -167,5 +171,5 @@ module bmuctrl( // BMU Execute stage pipieline control register - flopenrc#(13) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, RotateD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, RotateE}); + flopenrc#(15) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, BALUControlD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE}); endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index b2e21ebf7..0486ff21c 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -60,7 +60,8 @@ module controller( output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction output logic [2:0] ZBBSelectE, // ZBB mux select signal in Execute stage - output logic RotateE, // Indicates if rotate instruction in Execute Stage + output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage + // Memory stage control signals input logic StallM, FlushM, // Stall, flush Memory stage output logic [1:0] MemRWM, // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write @@ -223,7 +224,7 @@ module controller( // BITMANIP Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .RotateE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); if (`ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; @@ -242,7 +243,7 @@ module controller( assign BRegWriteE = 1'b0; assign BSubArithD = 1'b0; assign BComparatorSignedE = 1'b0; - assign RotateE = 1'b0; + assign BALUControlE = 3'b0; assign sltD = (Funct3D == 3'b010); diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 19057fcb7..dd93e71d6 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -48,7 +48,7 @@ module datapath ( input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelectE, // ZBB mux select signal - input logic RotateE, // Indicates if Rotate instruction in Execute Stage + input logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B @@ -60,7 +60,7 @@ module datapath ( output logic [`XLEN-1:0] WriteDataM, // Write data in Memory stage // Writeback stage signals input logic StallW, FlushW, // Stall, flush Writeback stage - input logic RegWriteW, IntDivW, // Write register file, integer divide instruction + input logic RegWriteW, IntDivW, // Write register file, integer divide instruction input logic SquashSCW, // Squash a store conditional when a conflict arose input logic [2:0] ResultSrcW, // Select source of result to write back to register file input logic [`XLEN-1:0] FCvtIntResW, // FPU convert fp to integer result @@ -113,7 +113,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, RotateE, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, BALUControlE, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 88a83ea66..39bd36e66 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -72,7 +72,7 @@ module ieu ( output logic MDUStallD, CSRRdStallD, StoreStallD, output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction output logic CSRWriteFenceM, // CSR write or fence instruction needs to flush subsequent instructions - output logic FenceM + output logic FenceM ); logic [2:0] ImmSrcD; // Select type of immediate extension @@ -87,7 +87,7 @@ module ieu ( logic IntDivW; // Integer divide instruction logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding logic [2:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage - logic RotateE; // Indicates if Rotate Instruction in Execute Stage + logic [2:0] BALUControlE; // ALU Control signals for B instructions in Execute Stage // Forwarding signals logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers @@ -101,7 +101,7 @@ controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, - .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .RotateE, .StallM, .FlushM, .MemRWM, + .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .FenceM, .StoreStallD); @@ -109,7 +109,7 @@ controller c( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, - .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .RotateE, + .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW); From 7512e55699b87b977969d51d66216fad04de572c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 4 Mar 2023 22:54:32 -0800 Subject: [PATCH 137/231] added python script -I've been using this python script to make quick changes to the bitmanip controller --- src/ieu/bmu/bitfieldedit.py | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 src/ieu/bmu/bitfieldedit.py diff --git a/src/ieu/bmu/bitfieldedit.py b/src/ieu/bmu/bitfieldedit.py new file mode 100644 index 000000000..a9f604a33 --- /dev/null +++ b/src/ieu/bmu/bitfieldedit.py @@ -0,0 +1,32 @@ +""" + bitfieldedit.py + Script that appends 0 just before the "illegal instruction" field of the bitstring + Written by Kevin Kim +""" +def addZero(s): + try: + indexSemicolon = s.index(";") + newS = s[:indexSemicolon-1]+"0_"+s[indexSemicolon-1:] + return newS + except: return s + +def main(): + filename = input("Enter full filename: ") + n1 = int(input("Line number to begin: ")) + n2 = int(input("Line number to end: ")) + f = open(filename, "r") + flines = f.readlines() + + #create list of lines from line n1 to n2, inclusive + lines = flines[(n1-1):(n2-1)] + + #string to be printed + out = "" + + for i in range(len(lines)): + lines[i] = addZero(lines[i]) + out += lines[i] + print(out) + +if __name__ == "__main__": + main() \ No newline at end of file From a293c350bae6902dbc36130937c5a091cfbb423f Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 4 Mar 2023 23:07:06 -0800 Subject: [PATCH 138/231] alu pre-shift -changed ALU pre shift logic to use a 2 bit shifter instead of mux --- src/ieu/alu.sv | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index dea870227..96751be83 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -94,14 +94,8 @@ module alu #(parameter WIDTH=32) ( end else assign rotA = A; if (`ZBA_SUPPORTED) begin: zbamuxes - // Pre-Shift Mux - always_comb - case (Funct3[2:1] & {2{PreShift}}) - 2'b00: CondShiftA = shA[WIDTH-1:0]; - 2'b01: CondShiftA = {shA[WIDTH-2:0],{1'b0}}; // sh1add - 2'b10: CondShiftA = {shA[WIDTH-3:0],{2'b00}}; // sh2add - 2'b11: CondShiftA = {shA[WIDTH-4:0],{3'b000}}; // sh3add - endcase + // Pre-Shift + assign CondShiftA = shA[WIDTH-1:0] << (Funct3[2:1] & {2{PreShift}}); end else assign CondShiftA = A; // Addition From 6b25c64a1f28387cca101c92aa486d8b4e6faf51 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 4 Mar 2023 23:19:31 -0800 Subject: [PATCH 139/231] BSelect from OH encoding to Binary --- src/ieu/alu.sv | 13 +++-- src/ieu/bmu/bmuctrl.sv | 114 ++++++++++++++++++++--------------------- src/ieu/controller.sv | 8 +-- src/ieu/datapath.sv | 2 +- src/ieu/ieu.sv | 2 +- 5 files changed, 69 insertions(+), 70 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 96751be83..565d30d27 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -33,7 +33,7 @@ module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform input logic [2:0] ALUSelect, // ALU mux select signal - input logic [3:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction + input logic [1:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect input logic [1:0] CompFlags, // Comparator flags @@ -167,12 +167,11 @@ module alu #(parameter WIDTH=32) ( if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : zbdecoder always_comb case (BSelect) - //ZBA_ZBB_ZBC_ZBS - 4'b0001: ALUResult = FullResult; - 4'b0010: ALUResult = ZBCResult; - 4'b1000: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA instructions don't sign extend the MSB of the right-hand word. - 4'b0100: ALUResult = ZBBResult; - default: ALUResult = CondExtFullResult; + // 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC + 2'b00: ALUResult = CondExtFullResult; + 2'b01: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word. + 2'b10: ALUResult = ZBBResult; + 2'b11: ALUResult = ZBCResult; endcase end else assign ALUResult = CondExtFullResult; endmodule \ No newline at end of file diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index b9fb539a7..6bac07d92 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -36,7 +36,7 @@ module bmuctrl( input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage output logic [2:0] ALUSelectD, // ALU Mux select signal in Decode Stage - output logic [3:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage + output logic [1:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage @@ -46,7 +46,7 @@ module bmuctrl( // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectE, - output logic [3:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + output logic [1:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding output logic [2:0] ZBBSelectE, // ZBB mux select signal output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute output logic BComparatorSignedE, // Indicates if comparator signed in Execute Stage @@ -63,7 +63,7 @@ module bmuctrl( logic MaskD; // Indicates if zbs instruction in Decode Stage logic PreShiftD; // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage logic [2:0] BALUControlD; // ALU Control signals for B instructions - `define BMUCTRLW 18 + `define BMUCTRLW 16 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -79,84 +79,84 @@ module bmuctrl( casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_1_0_0; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_1_1_0_1_0_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_1_0_0; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_01_000_1_0_1_1_0_1_0_0; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_1_0_0; // bexti + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_1_1_0_1_0_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_1_0_0; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_01_000_1_0_1_1_0_1_0_0; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_1_0_0; // binvi + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_1_0_0_1_0_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_1_0_0; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_01_000_1_0_1_0_0_1_0_0; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_1_0_0; // bseti + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_1_0_0_1_0_0; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_1_0_0; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_01_000_1_0_1_0_0_1_0_0; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_0001_000_1_0_1_1_0_1_0_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_0001_000_1_0_1_1_0_1_0_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_0001_000_1_0_1_0_0_1_0_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_0001_000_1_0_1_0_0_1_0_0; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_0000_000_1_0_1_0_0_0_0_0; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_1_1_0_1_0_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_1_1_0_1_0_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_1_0_0_1_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_1_0_0_1_0_0; // bset + 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_0_0_0_0_0; // sra, srai, srl, srli, sll, slli // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_0010_000_1_0_1_0_0_0_0_0; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_1_0_0_0_0_0; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0_1_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0_1_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_0_1_0_0_0_1_0; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_1_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_1_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_1_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_1000_000_1_1_1_0_0_0_0_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_1000_000_1_1_1_0_0_0_0_0; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_0_0_0_1_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_0_0_0_1_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_0_0_0_1_0; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_1_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_1_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_1_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_0_0_0_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0_0_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0_0_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_10_111_1_1_1_0_1_0_0_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_10_111_1_1_1_0_1_0_0_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_0_1_0_1_0_0_0; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_0100_111_1_1_1_0_1_0_0_0; // roriw + BMUControlsD = `BMUCTRLW'b001_10_111_1_1_1_0_1_0_0_0; // roriw else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0_0_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_0100_000_1_0_1_0_0_0_0_0; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_0100_000_1_1_1_0_0_0_0_0; // count word instruction + BMUControlsD = `BMUCTRLW'b000_10_000_1_0_1_0_0_0_0_0; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_0_0_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0_0_0; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_100_1_0_1_0_0_0_0_0; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_0100_111_1_0_1_1_0_0_0_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_0100_111_1_0_1_1_0_0_0_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_0100_111_1_0_1_1_0_0_0_0; // xnor + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_10_111_1_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_10_111_1_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_10_111_1_0_1_1_0_0_0_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0_0_0; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0_0_0; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_0000_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_0100_011_1_0_1_0_0_0_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_0100_101_1_0_1_0_0_0_0_0; // maxu - default: BMUControlsD = {Funct3D, {14'b0}, {1'b1}}; // not B instruction or shift + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_101_1_0_1_0_0_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_101_1_0_1_0_0_0_0_0; // maxu + default: BMUControlsD = {Funct3D, {12'b0}, {1'b1}}; // not B instruction or shift endcase // Unpack Control Signals @@ -171,5 +171,5 @@ module bmuctrl( // BMU Execute stage pipieline control register - flopenrc#(15) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, BALUControlD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE}); + flopenrc#(13) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, BALUControlD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE}); endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 0486ff21c..ce853aee4 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -58,7 +58,7 @@ module controller( output logic BranchE, // Branch instruction output logic SCE, // Store Conditional instruction output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) - output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction + output logic [1:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction output logic [2:0] ZBBSelectE, // ZBB mux select signal in Execute stage output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage @@ -124,7 +124,7 @@ module controller( logic FenceD, FenceE; // Fence instruction logic SFenceVmaD; // sfence.vma instruction logic IntDivM; // Integer divide instruction - logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage + logic [1:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage logic [2:0] ZBBSelectD; // ZBB Mux Select Signal logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage logic BW64D; // Indicates if it is a W type B instruction in decode stage @@ -234,8 +234,8 @@ module controller( end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; - assign BSelectE = 4'b0000; - assign BSelectD = 4'b0000; + assign BSelectE = 2'b00; + assign BSelectD = 2'b00; assign ZBBSelectE = 3'b000; assign BRegWriteD = 1'b0; assign BW64D = 1'b0; diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index dd93e71d6..dc9a02894 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -46,7 +46,7 @@ module datapath ( input logic [2:0] ALUSelectE, // ALU mux select signal input logic JumpE, // Is a jump (j) instruction input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) - input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction + input logic [1:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelectE, // ZBB mux select signal input logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 39bd36e66..b5fa4517b 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -85,7 +85,7 @@ module ieu ( logic SCE; // Store Conditional instruction logic FWriteIntM; // FPU writing to integer register file logic IntDivW; // Integer divide instruction - logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding + logic [1:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding logic [2:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage logic [2:0] BALUControlE; // ALU Control signals for B instructions in Execute Stage From 0f2360f0d7c0dd62d205699a9f994553454e0d23 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sat, 4 Mar 2023 23:56:33 -0800 Subject: [PATCH 140/231] bug in bctrl - deleted the min/minu decoding for some reason. --- src/ieu/bmu/bmuctrl.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 6bac07d92..a3ed483a1 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -156,6 +156,8 @@ module bmuctrl( 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // orc.b 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_101_1_0_1_0_0_0_0_0; // max 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_101_1_0_1_0_0_0_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_110_1_0_1_0_0_0_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_110_1_0_1_0_0_0_0_0; // minu default: BMUControlsD = {Funct3D, {12'b0}, {1'b1}}; // not B instruction or shift endcase From 7836bc1e375886be2470927b4b25830313c1cfb5 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Mar 2023 14:06:24 -0800 Subject: [PATCH 141/231] ALU changes - added PreShiftAmt signal for shadd - condinvB now muxes from B instead of mask --- src/ieu/alu.sv | 32 ++++++++++++++++++++------------ 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 565d30d27..5ee0f900d 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -43,11 +43,12 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,CondExtFullResult, ZBCResult, ZBBResult; // Intermediate results + logic [WIDTH-1:0] CondInvB,CondMaskInvB, Shift, SLT, SLTU, FullResult,CondExtFullResult, ZBCResult, ZBBResult; // Intermediate results logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux logic [WIDTH-1:0] CondZextA; // Result of Zero Extend A select mux + logic [WIDTH-1:0] RevA; // Bit-reversed A logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction @@ -60,6 +61,7 @@ module alu #(parameter WIDTH=32) ( logic Rotate; // Indicates if it is Rotate instruction logic Mask; // Indicates if it is ZBS instruction logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction + logic [1:0] PreShiftAmt; // Amount to Pre-Shift A // Extract control signals from ALUControl. @@ -71,6 +73,8 @@ module alu #(parameter WIDTH=32) ( // Pack control signals into shifter select assign shASelect = {W64,SubArith}; + assign PreShiftAmt = Funct3[2:1] & {2{PreShift}}; + if (`ZBS_SUPPORTED) begin: zbsdec decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); assign CondMaskB = (Mask) ? MaskB : B; @@ -80,10 +84,10 @@ module alu #(parameter WIDTH=32) ( if (WIDTH == 64) begin // rv64 must handle word s/z extensions always_comb case (shASelect) - 2'b00: shA = {{1'b0}, A}; - 2'b01: shA = {A[63], A}; - 2'b10: shA = {{33'b0}, A[31:0]}; - 2'b11: shA = {{33{A[31]}}, A[31:0]}; + 2'b00: shA = {{1'b0}, A}; // zero-extend double-word (srl) + 2'b01: shA = {A[63], A}; // sign-extend double-word (sra) + 2'b10: shA = {{33'b0}, A[31:0]}; // zero-extend word (add.uw, shadd.uw, srlw) + 2'b11: shA = {{33{A[31]}}, A[31:0]}; //sign extend-word (sraw) endcase end else assign shA = (SubArith) ? {A[31], A} : {{1'b0},A}; // rv32 does need to handle s/z extensions @@ -95,11 +99,12 @@ module alu #(parameter WIDTH=32) ( if (`ZBA_SUPPORTED) begin: zbamuxes // Pre-Shift - assign CondShiftA = shA[WIDTH-1:0] << (Funct3[2:1] & {2{PreShift}}); + assign CondShiftA = shA[WIDTH-1:0] << (PreShiftAmt); end else assign CondShiftA = A; // Addition - assign CondInvB = SubArith ? ~CondMaskB : CondMaskB; + assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB; + assign CondInvB = SubArith ? ~B : B; assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) @@ -128,9 +133,9 @@ module alu #(parameter WIDTH=32) ( 3'b001: FullResult = Shift; // sll, sra, or srl 3'b010: FullResult = SLT; // slt 3'b011: FullResult = SLTU; // sltu - 3'b100: FullResult = A ^ CondInvB; // xor, xnor, binv - 3'b110: FullResult = A | CondInvB; // or, orn, bset - 3'b111: FullResult = A & CondInvB; // and, bclr + 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv + 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset + 3'b111: FullResult = A & CondMaskInvB; // and, bclr 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}};// bext endcase end @@ -154,13 +159,16 @@ module alu #(parameter WIDTH=32) ( if (WIDTH == 64) assign CondExtFullResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; else assign CondExtFullResult = FullResult; + if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse + bitreverse #(WIDTH) brA(.a(A), .b(RevA)); + end //NOTE: This looks good and can be merged. if (`ZBC_SUPPORTED) begin: zbc - zbc #(WIDTH) ZBC(.A(A), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); + zbc #(WIDTH) ZBC(.A(A), .RevA(RevA), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); end else assign ZBCResult = 0; if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A(A), .B(B), .ALUResult(CondExtFullResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + zbb #(WIDTH) ZBB(.A(A), .RevA(RevA), .B(B), .ALUResult(CondExtFullResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); end else assign ZBBResult = 0; // Final Result B instruction select mux From 77d8f10574458edc570c9e94e2b37e37e30c819a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Mar 2023 14:26:24 -0800 Subject: [PATCH 142/231] revA signals to cnt, zbb --- src/ieu/bmu/cnt.sv | 3 ++- src/ieu/bmu/zbb.sv | 6 +++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 32be6b2eb..b5096a813 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -31,7 +31,8 @@ `include "wally-config.vh" module cnt #(parameter WIDTH = 32) ( - input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] A, RevA, // Operands + input logic [4:0] B, // Last 5 bits of immediate input logic W64, // Indicates word operation output logic [WIDTH-1:0] CntResult // count result ); diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 13529d6a1..1c2ae6bc0 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -31,14 +31,13 @@ `include "wally-config.vh" module zbb #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] A, RevA, B, // Operands input logic [WIDTH-1:0] ALUResult, // ALU Result input logic W64, // Indicates word operation input logic lt, // lt flag input logic [2:0] ZBBSelect, // Indicates word operation output logic [WIDTH-1:0] ZBBResult); // ZBB result - // count result logic [WIDTH-1:0] CntResult; @@ -53,7 +52,8 @@ module zbb #(parameter WIDTH=32) ( // sign/zero extend results logic [WIDTH-1:0] ExtResult; // sign/zero extend result - cnt #(WIDTH) cnt(.A(A), .B(B), .W64(W64), .CntResult(CntResult)); + + cnt #(WIDTH) cnt(.A(A), .RevA(RevA), .B(B[4:0]), .W64(W64), .CntResult(CntResult)); byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult)); ext #(WIDTH) ext(.A(A), .B(B), .ExtResult(ExtResult)); From 2ae32f75b5e46a2a3ef40250843243a05e2db109 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Mar 2023 14:26:31 -0800 Subject: [PATCH 143/231] zbc input mux structural --- src/ieu/bmu/zbc.sv | 37 ++++++++++--------------------------- 1 file changed, 10 insertions(+), 27 deletions(-) diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 74b2f64b6..fc4b17b76 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -30,39 +30,22 @@ `include "wally-config.vh" module zbc #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands - input logic [2:0] Funct3, // Indicates operation to perform - output logic [WIDTH-1:0] ZBCResult); // ZBC result + input logic [WIDTH-1:0] A, RevA, B, // Operands + input logic [2:0] Funct3, // Indicates operation to perform + output logic [WIDTH-1:0] ZBCResult); // ZBC result logic [WIDTH-1:0] ClmulResult, RevClmulResult; - logic [WIDTH-1:0] RevA, RevB; + logic [WIDTH-1:0] RevB; logic [WIDTH-1:0] x,y; + logic [1:0] select; + + assign select = ~Funct3[1:0]; - bitreverse #(WIDTH) brA(.a(A), .b(RevA)); bitreverse #(WIDTH) brB(.a(B), .b(RevB)); - // zbc input select mux - always_comb begin - casez (Funct3[1:0]) - 2'b01: begin //clmul - x = A; - y = B; - end - 2'b11: begin //clmulh - x = {RevA[WIDTH-2:0], {1'b0}}; - y = {{1'b0}, RevB[WIDTH-2:0]}; - end - 2'b10: begin //clmulr - x = RevA; - y = RevB; - end - default: begin - x = 0; - y = 0; - end - endcase - - end + + mux3 #(WIDTH) xmux({RevA[WIDTH-2:0], {1'b0}}, RevA, A, select, x); + mux3 #(WIDTH) ymux({{1'b0},RevB[WIDTH-2:0]}, RevB, B, select, y); clmul #(WIDTH) clm(.A(x), .B(y), .ClmulResult(ClmulResult)); bitreverse #(WIDTH) brClmulResult(.a(ClmulResult), .b(RevClmulResult)); From 696cfb69495ec0191f0dbd8366f3ea992a6733ba Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Mar 2023 14:57:30 -0800 Subject: [PATCH 144/231] zbb result select mux structural --- src/ieu/bmu/bmuctrl.sv | 40 ++++++++++++++++++++-------------------- src/ieu/bmu/zbb.sv | 23 ++--------------------- 2 files changed, 22 insertions(+), 41 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index a3ed483a1..d57aecfd7 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -116,48 +116,48 @@ module bmuctrl( 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_0_0; // add.uw 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_0_0_0_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_10_111_1_1_1_0_1_0_0_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_10_111_1_1_1_0_1_0_0_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_1_0_1_0_0_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_0_1_0_0_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_1_0_1_0_0_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_0_1_0_0_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_0_1_0_0_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_10_111_1_0_1_0_1_0_0_0; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_0_1_0_0_0; // rori (rv64) else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_10_111_1_1_1_0_1_0_0_0; // roriw + BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_0_1_0_0_0; // roriw else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_10_001_1_0_1_0_0_0_0_0; // sign extend instruction else BMUControlsD = `BMUCTRLW'b000_10_000_1_0_1_0_0_0_0_0; // count instruction 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_0_0_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_10_001_1_0_1_0_0_0_0_0; // zexth (rv64) else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_10_001_1_0_1_0_0_0_0_0; // zexth (rv32) else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_10_111_1_0_1_1_0_0_0_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_10_111_1_0_1_1_0_0_0_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_10_111_1_0_1_1_0_0_0_0; // xnor + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_1_1_0_0_0_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_10_010_1_0_1_0_0_0_0_0; // rev8 (rv64) else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_10_010_1_0_1_0_0_0_0_0; // rev8 (rv32) else BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_101_1_0_1_0_0_0_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_101_1_0_1_0_0_0_0_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_110_1_0_1_0_0_0_0_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_110_1_0_1_0_0_0_0_0; // minu + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_010_1_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // minu default: BMUControlsD = {Funct3D, {12'b0}, {1'b1}}; // not B instruction or shift endcase diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 1c2ae6bc0..fc1918742 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -61,27 +61,8 @@ module zbb #(parameter WIDTH=32) ( assign MaxResult = (lt) ? B : A; assign MinResult = (lt) ? A : B; - //can replace with structural mux by looking at bit 4 in rs2 field - always_comb begin - case (ZBBSelect) - 3'b111: ZBBResult = ALUResult; // rotates, andn, xnor, orn - 3'b000: ZBBResult = CntResult; // count - 3'b100: ZBBResult = ExtResult; // sign/zero extend - 3'b011: ZBBResult = ByteResult; // byte instructions - 3'b110: ZBBResult = MinResult; // min, minu - 3'b101: ZBBResult = MaxResult; // max, maxu - /*15'b0010100_101_00111: ZBBResult = OrcBResult; - 15'b0110100_101_11000: ZBBResult = Rev8Result; - 15'b0110101_101_11000: ZBBResult = Rev8Result; - 15'b0110000_001_00000: ZBBResult = czResult; - 15'b0110000_001_00010: ZBBResult = cpopResult; - 15'b0110000_001_00001: ZBBResult = czResult; - 15'b0000100_100_00000: ZBBResult = zexthResult; - 15'b0110000_001_00100: ZBBResult = sextbResult; - 15'b0110000_001_00101: ZBBResult = sexthResult;*/ - default: ZBBResult = {(WIDTH){1'b0}}; - endcase - end + // ZBB Result select mux + mux5 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinResult, MaxResult, ZBBSelect, ZBBResult); endmodule \ No newline at end of file From 3dbdf3d579bec7570654ba78d4f4fc496ea879a4 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Mar 2023 15:09:02 -0800 Subject: [PATCH 145/231] extend unit structural mux --- src/ieu/bmu/ext.sv | 12 ++++-------- src/ieu/bmu/zbb.sv | 2 +- 2 files changed, 5 insertions(+), 9 deletions(-) diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 05cb24c01..346b7811d 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -31,21 +31,17 @@ `include "wally-config.vh" module ext #(parameter WIDTH = 32) ( - input logic [WIDTH-1:0] A, B, // Operands + input logic [WIDTH-1:0] A, // Operands + input logic [1:0] ExtSelect, // B[2], B[0] of immediate output logic [WIDTH-1:0] ExtResult); // Extend Result logic [WIDTH-1:0] sexthResult, zexthResult, sextbResult; + assign sexthResult = {{(WIDTH-16){A[15]}},A[15:0]}; assign zexthResult = {{(WIDTH-16){1'b0}},A[15:0]}; assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]}; - always_comb - case({B[2],B[0]}) - 2'b00: ExtResult = zexthResult; - 2'b10: ExtResult = sextbResult; - 2'b11: ExtResult = sexthResult; - default: ExtResult = 0; - endcase + mux3 #(WIDTH) extmux(zexthResult, sextbResult, sexthResult, ExtSelect, ExtResult); endmodule \ No newline at end of file diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index fc1918742..654146291 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -55,7 +55,7 @@ module zbb #(parameter WIDTH=32) ( cnt #(WIDTH) cnt(.A(A), .RevA(RevA), .B(B[4:0]), .W64(W64), .CntResult(CntResult)); byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult)); - ext #(WIDTH) ext(.A(A), .B(B), .ExtResult(ExtResult)); + ext #(WIDTH) ext(.A(A), .ExtSelect({B[2], B[0]}), .ExtResult(ExtResult)); assign MaxResult = (lt) ? B : A; From e80c1248a260a13b2e06443cd198c664dfcf1c10 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Sun, 5 Mar 2023 15:20:48 -0800 Subject: [PATCH 146/231] bug fix --- src/ieu/bmu/ext.sv | 2 +- src/ieu/bmu/zbb.sv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 346b7811d..0b4103273 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -41,7 +41,7 @@ module ext #(parameter WIDTH = 32) ( assign zexthResult = {{(WIDTH-16){1'b0}},A[15:0]}; assign sextbResult = {{(WIDTH-8){A[7]}},A[7:0]}; - mux3 #(WIDTH) extmux(zexthResult, sextbResult, sexthResult, ExtSelect, ExtResult); + mux3 #(WIDTH) extmux(sextbResult, sexthResult, zexthResult, ExtSelect, ExtResult); endmodule \ No newline at end of file diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 654146291..f4b7eead8 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -55,7 +55,7 @@ module zbb #(parameter WIDTH=32) ( cnt #(WIDTH) cnt(.A(A), .RevA(RevA), .B(B[4:0]), .W64(W64), .CntResult(CntResult)); byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult)); - ext #(WIDTH) ext(.A(A), .ExtSelect({B[2], B[0]}), .ExtResult(ExtResult)); + ext #(WIDTH) ext(.A(A), .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult(ExtResult)); assign MaxResult = (lt) ? B : A; From fb529e1640001b5c3bc9ad83884fbee8406522b2 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 6 Mar 2023 05:41:53 -0800 Subject: [PATCH 147/231] updated license header --- src/ieu/bmu/bitreverse.sv | 4 ++-- src/ieu/bmu/bmuctrl.sv | 4 ++-- src/ieu/bmu/byte.sv | 6 +++--- src/ieu/bmu/clmul.sv | 4 ++-- src/ieu/bmu/ext.sv | 2 +- src/ieu/bmu/popcnt.sv | 2 +- src/ieu/bmu/zbb.sv | 4 ++-- src/ieu/bmu/zbc.sv | 4 ++-- 8 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index 5d195d241..559bb0c09 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -4,9 +4,9 @@ // // Written: Kevin Kim and Kip Macsai-Goren // Created: 1 February 2023 -// Modified: +// Modified: 6 March 2023 // -// Purpose: Carry-Less multiplication top-level unit +// Purpose: Bit reverse submodule // // Documentation: RISC-V System on Chip Design Chapter *** // diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index d57aecfd7..3675a7114 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -3,9 +3,9 @@ // // Written: Kevin Kim // Created: 16 February 2023 -// Modified: +// Modified: 6 March 2023 // -// Purpose: Top level B instruction decoder +// Purpose: Top level bit manipulation instruction decoder // // Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) // diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index 2b98b83d6..19b71fc1e 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -1,11 +1,11 @@ /////////////////////////////////////////// -// clmul.sv +// byte.sv // // Written: Kevin Kim // Created: 1 February 2023 -// Modified: +// Modified: 6 March 2023 // -// Purpose: Carry-Less multiplication top-level unit +// Purpose: RISCV bitmanip byte-wise operation unit // // Documentation: RISC-V System on Chip Design Chapter *** // diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 46893573c..16d600b43 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -1,11 +1,11 @@ /////////////////////////////////////////// -// clmul.sv (carry-less multiplier) +// clmul.sv // // Written: Kevin Kim and Kip Macsai-Goren // Created: 1 February 2023 // Modified: // -// Purpose: Carry-Less multiplication top-level unit +// Purpose: Carry-Less multiplication unit // // Documentation: RISC-V System on Chip Design Chapter *** // diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 0b4103273..3a832de65 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -1,6 +1,6 @@ /////////////////////////////////////////// -// cnt.sv +// ext.sv // // Written: Kevin Kim // Created: 4 February 2023 diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index c82476a61..544c1344f 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -1,6 +1,6 @@ /////////////////////////////////////////// -// +// popccnt.sv // Written: Kevin Kim // Modified: 2/4/2023 // diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index f4b7eead8..54459db82 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -4,9 +4,9 @@ // // Written: Kevin Kim and Kip Macsai-Goren // Created: 2 February 2023 -// Modified: +// Modified: March 6 2023 // -// Purpose: RISC-V miscellaneous bit manipulation unit (subset of ZBB instructions) +// Purpose: RISC-V ZBB top level unit // // Documentation: RISC-V System on Chip Design Chapter *** // diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index fc4b17b76..c1ed706ba 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -3,9 +3,9 @@ // // Written: Kevin Kim and Kip Macsai-Goren // Created: 2 February 2023 -// Modified: +// Modified: 3 March 2023 // -// Purpose: RISC-V single bit manipulation unit (ZBC instructions) +// Purpose: RISC-V ZBC top-level unit // // Documentation: RISC-V System on Chip Design Chapter *** // From 8f3acedec8223bbdd419ca358ed200dfe26b31ed Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 6 Mar 2023 05:52:08 -0800 Subject: [PATCH 148/231] formatted files --- src/ieu/bmu/bitreverse.sv | 1 - src/ieu/bmu/bmuctrl.sv | 6 ++---- src/ieu/bmu/ext.sv | 2 -- src/ieu/bmu/popcnt.sv | 2 -- src/ieu/bmu/zbb.sv | 21 ++++----------------- src/ieu/bmu/zbc.sv | 5 ++--- src/ieu/shifter.sv | 1 - 7 files changed, 8 insertions(+), 30 deletions(-) diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index 559bb0c09..644783e57 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -37,7 +37,6 @@ module bitreverse #(parameter WIDTH=32) ( for (i=0; i Date: Mon, 6 Mar 2023 06:19:01 -0800 Subject: [PATCH 149/231] formatting - reverted back to ALUResult signal in alu.sv --- src/ieu/alu.sv | 21 +++++++++++---------- src/ieu/bmu/bmuctrl.sv | 2 -- src/ieu/controller.sv | 3 +-- 3 files changed, 12 insertions(+), 14 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 5ee0f900d..11fab86ef 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -38,12 +38,13 @@ module alu #(parameter WIDTH=32) ( input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect input logic [1:0] CompFlags, // Comparator flags input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage - output logic [WIDTH-1:0] ALUResult, // ALU result + output logic [WIDTH-1:0] Result, // ALU result output logic [WIDTH-1:0] Sum); // Sum of operands // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB,CondMaskInvB, Shift, SLT, SLTU, FullResult,CondExtFullResult, ZBCResult, ZBBResult; // Intermediate results + logic [WIDTH-1:0] CondInvB,CondMaskInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate Signals + logic [WIDTH-1:0] ZBCResult, ZBBResult; // Result of ZBB, ZBC logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux @@ -156,8 +157,8 @@ module alu #(parameter WIDTH=32) ( // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (WIDTH == 64) assign CondExtFullResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; - else assign CondExtFullResult = FullResult; + if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + else assign ALUResult = FullResult; if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse bitreverse #(WIDTH) brA(.a(A), .b(RevA)); @@ -168,7 +169,7 @@ module alu #(parameter WIDTH=32) ( end else assign ZBCResult = 0; if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A(A), .RevA(RevA), .B(B), .ALUResult(CondExtFullResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + zbb #(WIDTH) ZBB(.A(A), .RevA(RevA), .B(B), .ALUResult(ALUResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); end else assign ZBBResult = 0; // Final Result B instruction select mux @@ -176,10 +177,10 @@ module alu #(parameter WIDTH=32) ( always_comb case (BSelect) // 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC - 2'b00: ALUResult = CondExtFullResult; - 2'b01: ALUResult = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word. - 2'b10: ALUResult = ZBBResult; - 2'b11: ALUResult = ZBCResult; + 2'b00: Result = ALUResult; + 2'b01: Result = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word. + 2'b10: Result = ZBBResult; + 2'b11: Result = ZBCResult; endcase - end else assign ALUResult = CondExtFullResult; + end else assign Result = ALUResult; endmodule \ No newline at end of file diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index ef9d2bb89..f40014564 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -29,7 +29,6 @@ `include "wally-config.vh" -// NOTE: DO we want to make this XLEN parameterized? module bmuctrl( input logic clk, reset, // Decode stage control signals @@ -51,7 +50,6 @@ module bmuctrl( output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute output logic BComparatorSignedE, // Indicates if comparator signed in Execute Stage output logic [2:0] BALUControlE // ALU Control signals for B instructions in Execute Stage - ); logic [6:0] OpD; // Opcode in Decode stage diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index ce853aee4..386ca2280 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -222,7 +222,7 @@ module controller( assign BaseSubArithD = ALUOpD & (subD | sraD | sltD | sltuD); assign ALUControlD = {W64D, SubArithD, ALUOpD}; - // BITMANIP Configuration Block + // bit manipulation Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); if (`ZBA_SUPPORTED) begin @@ -247,7 +247,6 @@ module controller( assign sltD = (Funct3D == 3'b010); - assign IllegalBitmanipInstrD = 1'b1; end From e67b02136cd51d21c8b4844c7a4b2ec4170bf455 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 6 Mar 2023 06:20:25 -0800 Subject: [PATCH 150/231] formatting --- src/ieu/alu.sv | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 11fab86ef..eb7e9f3a3 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -64,7 +64,6 @@ module alu #(parameter WIDTH=32) ( logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction logic [1:0] PreShiftAmt; // Amount to Pre-Shift A - // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; @@ -152,18 +151,12 @@ module alu #(parameter WIDTH=32) ( 3'b110: FullResult = A | B; // or 3'b111: FullResult = A & B; // and endcase - end - - - // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits - if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; - else assign ALUResult = FullResult; if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse bitreverse #(WIDTH) brA(.a(A), .b(RevA)); end - //NOTE: This looks good and can be merged. + if (`ZBC_SUPPORTED) begin: zbc zbc #(WIDTH) ZBC(.A(A), .RevA(RevA), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); end else assign ZBCResult = 0; @@ -171,7 +164,11 @@ module alu #(parameter WIDTH=32) ( if (`ZBB_SUPPORTED) begin: zbb zbb #(WIDTH) ZBB(.A(A), .RevA(RevA), .B(B), .ALUResult(ALUResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); end else assign ZBBResult = 0; - + + // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits + if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; + else assign ALUResult = FullResult; + // Final Result B instruction select mux if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : zbdecoder always_comb From c7d1e35d4a9ecf905f8a82946739e7016900e6aa Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 6 Mar 2023 06:44:15 -0800 Subject: [PATCH 151/231] structural changes in cnt.sv --- src/ieu/bmu/cnt.sv | 41 +++++++---------------------------------- 1 file changed, 7 insertions(+), 34 deletions(-) diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index b5096a813..1e3120e14 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -41,52 +41,25 @@ module cnt #(parameter WIDTH = 32) ( logic [WIDTH-1:0] czResult; // count zeros result logic [WIDTH-1:0] cpopResult; // population count result logic [WIDTH-1:0] lzcA, popcntA; - logic [WIDTH-1:0] revA; - //in both rv64, rv32 - bitreverse #(WIDTH) brtz(.a(A), .b(revA)); - //only in rv64 if (WIDTH==64) begin - //NOTE: signal widths can be decreased - always_comb begin - //clz input select mux - case({B[4:0],W64}) - 6'b00000_0: lzcA = A; //clz - 6'b00000_1: lzcA = {A[31:0],{32{1'b1}}}; //clzw - 6'b00001_0: lzcA = revA; //ctz - 6'b00001_1: lzcA = {revA[63:32],{32{1'b1}}}; //ctzw - default: lzcA = A; - endcase - - //cpop select mux - case ({B[4:0],W64}) - 6'b00010_0: popcntA = A; - 6'b00010_1: popcntA = {{32{1'b0}}, A[31:0]}; - default: popcntA = A; - endcase - end + //clz input select mux + mux4 #(WIDTH) lzcmux64(A, {A[31:0],{32{1'b1}}}, RevA, {RevA[63:32],{32{1'b1}}}, {B[0],W64}, lzcA); + //cpop select mux + mux2 #(WIDTH) popcntmux64(A, {{32{1'b0}}, A[31:0]}, W64, popcntA); end + //rv32 else begin - //rv32 assign popcntA = A; - always_comb begin - //clz input slect mux - case(B[4:0]) - 5'b00000: lzcA = A; - 5'b00001: lzcA = revA; - default: lzcA = A; - endcase - end + mux2 #(WIDTH) lzcmux32(A, RevA, B[0], lzcA); end - lzc #(WIDTH) lzc(.num(lzcA), .ZeroCnt(czResult[$clog2(WIDTH):0])); popcnt #(WIDTH) popcntw(.num(popcntA), .PopCnt(cpopResult[$clog2(WIDTH):0])); // zero extend these results to fit into width *** There may be a more elegant way to do this assign czResult[WIDTH-1:$clog2(WIDTH)+1] = {(WIDTH-$clog2(WIDTH)-1){1'b0}}; assign cpopResult[WIDTH-1:$clog2(WIDTH)+1] = {(WIDTH-$clog2(WIDTH)-1){1'b0}}; - assign CntResult = (B[1]) ? cpopResult : czResult; - + mux2 #(WIDTH) cntresultmux(czResult, cpopResult, B[1], CntResult); endmodule \ No newline at end of file From 5637897dcef3d113ce8c5e863a50a32862dc0c00 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 7 Mar 2023 00:28:07 -0800 Subject: [PATCH 152/231] reverted to working version --- src/ieu/controller.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 386ca2280..cfc8b46a4 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -124,6 +124,7 @@ module controller( logic FenceD, FenceE; // Fence instruction logic SFenceVmaD; // sfence.vma instruction logic IntDivM; // Integer divide instruction +<<<<<<< HEAD logic [1:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage logic [2:0] ZBBSelectD; // ZBB Mux Select Signal logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage @@ -141,6 +142,7 @@ module controller( // Main Instruction Decoder always_comb case(OpD) +<<<<<<< HEAD // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_BaseALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal 7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Illegal instruction 7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw From 81198ce6f66f8dd9eff011799c868167b156b858 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 7 Mar 2023 00:29:58 -0800 Subject: [PATCH 153/231] reverted backing to working version --- src/ieu/controller.sv | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index cfc8b46a4..386ca2280 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -124,7 +124,6 @@ module controller( logic FenceD, FenceE; // Fence instruction logic SFenceVmaD; // sfence.vma instruction logic IntDivM; // Integer divide instruction -<<<<<<< HEAD logic [1:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage logic [2:0] ZBBSelectD; // ZBB Mux Select Signal logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage @@ -142,7 +141,6 @@ module controller( // Main Instruction Decoder always_comb case(OpD) -<<<<<<< HEAD // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_BaseALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal 7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Illegal instruction 7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw From 833e7bd2afe482f6fd1e8a4766757864361ee1a2 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 7 Mar 2023 10:57:06 -0800 Subject: [PATCH 154/231] shifter sign generation logic optimize --- src/ieu/alu.sv | 18 +++++++++++++----- src/ieu/shifter.sv | 12 ++++++------ 2 files changed, 19 insertions(+), 11 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index eb7e9f3a3..cf33df531 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -48,7 +48,7 @@ module alu #(parameter WIDTH=32) ( logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux - logic [WIDTH-1:0] CondZextA; // Result of Zero Extend A select mux + logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux logic [WIDTH-1:0] RevA; // Bit-reversed A logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned @@ -56,7 +56,7 @@ module alu #(parameter WIDTH=32) ( logic SubArith; // Performing subtraction or arithmetic right shift logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B - logic [WIDTH:0] shA; // XLEN+1 bit input source to shifter + logic shSignA; logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter logic [1:0] shASelect; // select signal for shifter source generation mux logic Rotate; // Indicates if it is Rotate instruction @@ -80,7 +80,7 @@ module alu #(parameter WIDTH=32) ( assign CondMaskB = (Mask) ? MaskB : B; end else assign CondMaskB = B; - // Sign/Zero extend mux + /*// Sign/Zero extend mux if (WIDTH == 64) begin // rv64 must handle word s/z extensions always_comb case (shASelect) @@ -90,6 +90,14 @@ module alu #(parameter WIDTH=32) ( 2'b11: shA = {{33{A[31]}}, A[31:0]}; //sign extend-word (sraw) endcase end else assign shA = (SubArith) ? {A[31], A} : {{1'b0},A}; // rv32 does need to handle s/z extensions + */ + if (WIDTH == 64) begin + mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, shSignA); + mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A,{~W64, SubArith}, CondExtA); + end else begin + mux2 #(1) signmux(1'b0, A[31], SubArith, shSignA); + assign CondExtA = A; + end // shifter rotate source select mux if (`ZBB_SUPPORTED) begin @@ -99,7 +107,7 @@ module alu #(parameter WIDTH=32) ( if (`ZBA_SUPPORTED) begin: zbamuxes // Pre-Shift - assign CondShiftA = shA[WIDTH-1:0] << (PreShiftAmt); + assign CondShiftA = CondExtA << (PreShiftAmt); end else assign CondShiftA = A; // Addition @@ -108,7 +116,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) - shifter sh(.shA(shA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); + shifter sh(.shA(CondExtA), .Sign(shSignA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index dbed7655c..594ef3dd5 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -30,10 +30,10 @@ `include "wally-config.vh" module shifter ( - input logic [`XLEN:0] shA, // shift Source + input logic [`XLEN-1:0] shA, // shift Source input logic [`XLEN-1:0] rotA, // rotate source input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Rotate, W64, // Shift right, rotate signals + input logic Right, Rotate, W64, Sign, // Shift right, rotate signals output logic [`XLEN-1:0] Y); // Shifted result logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits @@ -45,7 +45,7 @@ module shifter ( case({Right, Rotate}) 2'b00: z = {shA[31:0], 31'b0}; 2'b01: z = {rotA,rotA[31:1]}; - 2'b10: z = {{31{shA[32]}}, shA[31:0]}; + 2'b10: z = {{31{Sign}}, shA[31:0]}; 2'b11: z = {rotA[30:0],rotA}; endcase assign amttrunc = Amt; // shift amount @@ -54,7 +54,7 @@ module shifter ( case ({Right, Rotate}) 2'b00: z = {shA[63:0],{63'b0}}; 2'b01: z = {rotA, rotA[63:1]}; - 2'b10: z = {{63{shA[64]}},shA[63:0]}; + 2'b10: z = {{63{Sign}},shA[63:0]}; 2'b11: z = {rotA[62:0],rotA[63:0]}; endcase assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift @@ -62,12 +62,12 @@ module shifter ( end else begin: norotfunnel if (`XLEN==32) begin:shifter // RV32 always_comb // funnel mux - if (Right) z = {{31{shA[32]}}, shA[31:0]}; + if (Right) z = {{31{Sign}}, shA[31:0]}; else z = {shA[31:0], 31'b0}; assign amttrunc = Amt; // shift amount end else begin:shifter // RV64 always_comb // funnel mux - if (Right) z = {{63{shA[64]}},shA[63:0]}; + if (Right) z = {{63{Sign}},shA[63:0]}; else z = {shA[63:0],{63'b0}}; assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end From 6d146a7e204d4c7ae63f068a36cb6f0e24c1c0ea Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 7 Mar 2023 10:57:52 -0800 Subject: [PATCH 155/231] formatting --- src/ieu/alu.sv | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index cf33df531..916b25a92 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -80,17 +80,7 @@ module alu #(parameter WIDTH=32) ( assign CondMaskB = (Mask) ? MaskB : B; end else assign CondMaskB = B; - /*// Sign/Zero extend mux - if (WIDTH == 64) begin // rv64 must handle word s/z extensions - always_comb - case (shASelect) - 2'b00: shA = {{1'b0}, A}; // zero-extend double-word (srl) - 2'b01: shA = {A[63], A}; // sign-extend double-word (sra) - 2'b10: shA = {{33'b0}, A[31:0]}; // zero-extend word (add.uw, shadd.uw, srlw) - 2'b11: shA = {{33{A[31]}}, A[31:0]}; //sign extend-word (sraw) - endcase - end else assign shA = (SubArith) ? {A[31], A} : {{1'b0},A}; // rv32 does need to handle s/z extensions - */ + if (WIDTH == 64) begin mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, shSignA); mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A,{~W64, SubArith}, CondExtA); From 26cb1857f357cc83a8ffd042189ab69128235a9f Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 7 Mar 2023 13:58:08 -0800 Subject: [PATCH 156/231] specifc instruction handling for B's - Added BALUSrcBD, BaseALUSrcB for distinguishing between base instruction I/IW and Bitmanip instruction I/IW --- src/ieu/bmu/bmuctrl.sv | 121 +++++++++++++++++++++-------------------- src/ieu/controller.sv | 16 +++--- 2 files changed, 70 insertions(+), 67 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index f40014564..4488ff29b 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -38,6 +38,7 @@ module bmuctrl( output logic [1:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage + output logic BALUSrcBD, // Indicates if it is an I/IW (non auipc) type B instruction in Decode Stage output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage output logic BALUOpD, // Indicates if it is an ALU B instruction in Decode Stage output logic BSubArithD, // TRUE if ext, clr, andn, orn, xnor instruction in Decode Stage @@ -62,7 +63,7 @@ module bmuctrl( logic PreShiftD; // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage logic [2:0] BALUControlD; // ALU Control signals for B instructions - `define BMUCTRLW 16 + `define BMUCTRLW 17 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -75,92 +76,96 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_BSelect_ZBBSelect_BRegWrite_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD + // ALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_1_1_0_1_0_0; // bclri + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b111_01_000_1_0_1_1_0_1_0_0; // bclri (rv64) + BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_1_1_0_1_0_0; // bexti + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b101_01_000_1_0_1_1_0_1_0_0; // bexti (rv64) + BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_1_0_0_1_0_0; // binvi + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b100_01_000_1_0_1_0_0_1_0_0; // binvi (rv64) + BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_1_0_0_1_0_0; // bseti + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b110_01_000_1_0_1_0_0_1_0_0; // bseti (rv64) + BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_1_1_0_1_0_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_1_1_0_1_0_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_1_0_0_1_0_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_1_0_0_1_0_0; // bset - 17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_0_0_0_0_0; // sra, srai, srl, srli, sll, slli + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset + //17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srai, srl, srli, sll, slli + 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll + 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli + 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw + 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_1_0_0_0_0_0; // ZBC instruction + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_0_0_0_1_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_0_0_0_1_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_0_0_0_1_0; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_1_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_1_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_1_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_1_1_0_0_0_0_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_0_0_0_0_0; // slli.uw + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_1_0_1_0_0_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_0_1_0_0_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_1_0_1_0_0_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_0_1_0_0_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_0_1_0_0_0; // rori (rv32) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_0_1_0_0_0; // rori (rv64) + BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_0_1_0_0_0; // roriw + BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) - BMUControlsD = `BMUCTRLW'b000_10_001_1_0_1_0_0_0_0_0; // sign extend instruction + BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction else - BMUControlsD = `BMUCTRLW'b000_10_000_1_0_1_0_0_0_0_0; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_0_0_0_0_0; // count word instruction + BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction + 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_10_001_1_0_1_0_0_0_0_0; // zexth (rv64) + BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_10_001_1_0_1_0_0_0_0_0; // zexth (rv32) + BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_1_1_0_0_0_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_1_1_0_0_0_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_1_1_0_0_0_0; // xnor + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) - BMUControlsD = `BMUCTRLW'b000_10_010_1_0_1_0_0_0_0_0; // rev8 (rv64) + BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv64) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_10_010_1_0_1_0_0_0_0_0; // rev8 (rv32) + BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv32) else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_1; // illegal instruction - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_010_1_0_1_0_0_0_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_1_0_0_0_0_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_1_0_0_0_0_0; // minu - default: BMUControlsD = {Funct3D, {12'b0}, {1'b1}}; // not B instruction or shift + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction + 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu + default: BMUControlsD = {Funct3D, {13'b0}, {1'b1}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD, BW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD; + assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD,BALUSrcBD, BW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD; // Pack BALUControl Signals assign BALUControlD = {RotateD, MaskD, PreShiftD}; diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 97bda128e..03979fc2a 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -97,6 +97,7 @@ module controller( logic BaseALUOpD, BaseW64D; // ALU operation and W64 for Base instructions specifically logic BaseRegWriteD; // Indicates if Base instruction register write instruction logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu + logic BaseALUSrcBD; // Base instruction ALU B source select signal logic [2:0] ALUControlD; // Determines ALU operation logic [2:0] ALUSelectD; // ALU mux select signal logic ALUSrcAD, ALUSrcBD; // ALU inputs @@ -130,6 +131,7 @@ module controller( logic BW64D; // Indicates if it is a W type B instruction in decode stage logic BALUOpD; // Indicates if it is an ALU B instruction in decode stage logic BSubArithD; // TRUE for B-type ext, clr, andn, orn, xnor + logic BALUSrcBD; // B-type alu src select signal logic BComparatorSignedE; // Indicates if max, min (signed comarison) instruction in Execute Stage logic IFunctD, RFunctD, MFunctD; // Detect I, R, and M-type RV32IM/Rv64IM instructions logic LFunctD, SFunctD, BFunctD; // Detect load, store, branch instructions @@ -179,15 +181,9 @@ module controller( always_comb begin ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // default: Illegal instruction case(OpD) -<<<<<<< HEAD - // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_BaseALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal - 7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Illegal instruction - 7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw -======= // RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_ALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal 7'b0000011: if (LFunctD) ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // loads ->>>>>>> origin 7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported 7'b0001111: if (`ZIFENCEI_SUPPORTED) ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence @@ -196,7 +192,7 @@ module controller( 7'b0010011: if (IFunctD) ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU 7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc - 7'b0011011: if (IFunctD & `XLEN == 64) + 7'b0011011: if ((IFunctD & `XLEN == 64)) ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0; // IW-type ALU for RV64i 7'b0100011: if (SFunctD) ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // stores @@ -239,7 +235,7 @@ module controller( assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ; //NOTE: Do we want to segregate the IllegalBitmanipInstrD into its own output signal //assign IllegalBaseInstrD = 1'b0; - assign {BaseRegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD, + assign {BaseRegWriteD, ImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD, ResultSrcD, BranchD, BaseALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD; @@ -247,6 +243,7 @@ module controller( assign ALUOpD = BaseALUOpD | BALUOpD; assign RegWriteD = BaseRegWriteD | BRegWriteD; assign W64D = BaseW64D | BW64D; + assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD; assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand @@ -265,7 +262,7 @@ module controller( // bit manipulation Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BALUSrcBD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); if (`ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; @@ -285,6 +282,7 @@ module controller( assign BSubArithD = 1'b0; assign BComparatorSignedE = 1'b0; assign BALUControlE = 3'b0; + assign BALUSrcBD = 1'b0; assign sltD = (Funct3D == 3'b010); From 4bb43892f9bfadc83edd19180b8c76dbdaac860e Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Tue, 7 Mar 2023 14:01:47 -0800 Subject: [PATCH 157/231] alu formatting --- src/ieu/alu.sv | 1 - 1 file changed, 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 916b25a92..cdb2e4919 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -80,7 +80,6 @@ module alu #(parameter WIDTH=32) ( assign CondMaskB = (Mask) ? MaskB : B; end else assign CondMaskB = B; - if (WIDTH == 64) begin mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, shSignA); mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A,{~W64, SubArith}, CondExtA); From 7002221decf9b57bbc2188988c46b8f33082e911 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 8 Mar 2023 16:22:43 -0800 Subject: [PATCH 158/231] cleaner bmu decode logic --- src/ieu/bmu/bmuctrl.sv | 29 ++++------------------------- 1 file changed, 4 insertions(+), 25 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 4488ff29b..47df5f30f 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -64,6 +64,7 @@ module bmuctrl( logic [2:0] BALUControlD; // ALU Control signals for B instructions `define BMUCTRLW 17 + `define BMUCTRLWSUB3 14 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -74,35 +75,27 @@ module bmuctrl( assign Rs2D = InstrD[24:20]; // Main Instruction Decoder - always_comb + always_comb begin + BMUControlsD = {Funct3D, `BMUCTRLWSUB3'b00_000_0_0_0_0_0_0_0_0_1}; // default: Illegal instruction casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD // ZBS 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti 17'b0010011_0010101_001: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset - //17'b0?1?011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srai, srl, srli, sll, slli 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw @@ -126,43 +119,29 @@ module bmuctrl( 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) 17'b0010011_0110001_101: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0011011_0110000_101: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110000_001: if (Rs2D[2]) BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction - else - BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0110011_0000100_100: if (`XLEN == 32) BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor 17'b0010011_0110101_101: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv64) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0110100_101: if (`XLEN == 32) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv32) - else - BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // illegal instruction 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // max 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // maxu 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu - default: BMUControlsD = {Funct3D, {13'b0}, {1'b1}}; // not B instruction or shift endcase + end // Unpack Control Signals assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD,BALUSrcBD, BW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD; From f335d08bbf0644b220d7cd4e1aa296160e4cf02d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 9 Mar 2023 12:35:42 -0800 Subject: [PATCH 159/231] fixed bmu bug - accidentally deleted count instruction decode --- src/ieu/bmu/bmuctrl.sv | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 47df5f30f..377c26f96 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -123,6 +123,8 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw 17'b0010011_0110000_001: if (Rs2D[2]) BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction + else + BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64) BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) From f29e8932a23284346a6343a16e32c4d09433ded4 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 9 Mar 2023 12:44:51 -0800 Subject: [PATCH 160/231] more comprehensive illegal b instr. check --- src/ieu/bmu/bmuctrl.sv | 127 ++++++++++++++++++++++++++--------------- 1 file changed, 81 insertions(+), 46 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 377c26f96..4d357854d 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -80,68 +80,103 @@ module bmuctrl( casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD // ZBS - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri - 17'b0010011_0100101_001: if (`XLEN == 64) + 17'b0010011_0100100_001: if (`ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri + 17'b0010011_0100101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti - 17'b0010011_0100101_101: if (`XLEN == 64) + 17'b0010011_0100100_101: if (`ZBS_SUPPORTED & `ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti + 17'b0010011_0100101_101: if (`XLEN == 64 & `ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi - 17'b0010011_0110101_001: if (`XLEN == 64) + 17'b0010011_0110100_001: if (`ZBS_SUPPORTED & `ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi + 17'b0010011_0110101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti - 17'b0010011_0010101_001: if (`XLEN == 64) + 17'b0010011_0010100_001: if (`ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti + 17'b0010011_0010101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64) - 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr - 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext - 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv - 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset - 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll - 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli - 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw - 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw + 17'b0110011_0100100_001: if (`ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr + 17'b0110011_0100100_101: if (`ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext + 17'b0110011_0110100_001: if (`ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv + 17'b0110011_0010100_001: if (`ZBS_SUPPORTED) + BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset + 17'b0110011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll + 17'b0010011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli + 17'b0111011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw + 17'b0011011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw // ZBC - 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction + 17'b0110011_0000101_0??: if (`ZBC_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction // ZBA - 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add - 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add - 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw + 17'b0110011_0010000_010: if (`ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add + 17'b0110011_0010000_100: if (`ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add + 17'b0110011_0010000_110: if (`ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add + 17'b0111011_0010000_010: if (`XLEN == 64 & `ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw + 17'b0111011_0010000_100: if (`XLEN == 64 & `ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw + 17'b0111011_0010000_110: if (`XLEN == 64 & `ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw + 17'b0111011_0000100_000: if (`XLEN == 64 & `ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw + 17'b0011011_000010?_001: if (`XLEN == 64 & `ZBA_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw // ZBB - 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw - 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw - 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) - 17'b0010011_0110001_101: if (`XLEN == 64) + 17'b0110011_0110000_001: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol + 17'b0111011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw + 17'b0110011_0110000_101: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror + 17'b0111011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw + 17'b0010011_0110000_101: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) + 17'b0010011_0110001_101: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) - 17'b0011011_0110000_101: if (`XLEN == 64) + 17'b0011011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw - 17'b0010011_0110000_001: if (Rs2D[2]) + 17'b0010011_0110000_001: if (Rs2D[2] & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction else BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction - 17'b0011011_0110000_001: BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction - 17'b0111011_0000100_100: if (`XLEN == 64) + 17'b0011011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction + 17'b0111011_0000100_100: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) - 17'b0110011_0000100_100: if (`XLEN == 32) + 17'b0110011_0000100_100: if (`XLEN == 32 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) - 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn - 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn - 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor - 17'b0010011_0110101_101: if (`XLEN == 64) + 17'b0110011_0100000_111: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor + 17'b0010011_0110101_101: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv64) - 17'b0010011_0110100_101: if (`XLEN == 32) + 17'b0010011_0110100_101: if (`XLEN == 32 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv32) - 17'b0010011_0010100_101: BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b - 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // max - 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // maxu - 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min - 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu + 17'b0010011_0010100_101: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // max + 17'b0110011_0000101_111: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // maxu + 17'b0110011_0000101_100: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min + 17'b0110011_0000101_101: if (`ZBB_SUPPORTED) + BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu endcase end From dcaf9de22885d089294ac5fa1e29b13dca776fb4 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 10 Mar 2023 14:17:38 -0800 Subject: [PATCH 161/231] removed redundant condinvb mux --- src/ieu/alu.sv | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index cdb2e4919..5fce245be 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -101,8 +101,7 @@ module alu #(parameter WIDTH=32) ( // Addition assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB; - assign CondInvB = SubArith ? ~B : B; - assign {Carry, Sum} = CondShiftA + CondInvB + {{(WIDTH-1){1'b0}}, SubArith}; + assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) shifter sh(.shA(CondExtA), .Sign(shSignA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); From c380b0816d81e085f1f177ac04df943a6034ff24 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 10 Mar 2023 14:18:24 -0800 Subject: [PATCH 162/231] removed redundant convinvb signal --- src/ieu/alu.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 5fce245be..6398e4fcf 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -43,7 +43,7 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB,CondMaskInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate Signals + logic [WIDTH-1:0] CondMaskInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate Signals logic [WIDTH-1:0] ZBCResult, ZBBResult; // Result of ZBB, ZBC logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux From 9b4f3219dbe11d5acf5bca5f019ef7cfa25d9744 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 10 Mar 2023 14:32:01 -0800 Subject: [PATCH 163/231] formatting --- src/ieu/alu.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 6398e4fcf..c770a630b 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -43,12 +43,12 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondMaskInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate Signals + logic [WIDTH-1:0] CondMaskInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate Signals logic [WIDTH-1:0] ZBCResult, ZBBResult; // Result of ZBB, ZBC logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux - logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux + logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux logic [WIDTH-1:0] RevA; // Bit-reversed A logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned From 0d0d3b981e66d1da3c4f27acc0ac70be7a10047a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 10 Mar 2023 17:17:24 -0800 Subject: [PATCH 164/231] more checks in bitmanip decode --- src/ieu/bmu/bmuctrl.sv | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 4d357854d..936986cf3 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -147,11 +147,11 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) 17'b0011011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw - 17'b0010011_0110000_001: if (Rs2D[2] & `ZBB_SUPPORTED) + 17'b0010011_0110000_001: if (Rs2D[2] & `ZBB_SUPPORTED & (Rs2D[4:1] == 4'b0010)) BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction - else + else if (`ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))) BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction - 17'b0011011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED) + 17'b0011011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))) BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction 17'b0111011_0000100_100: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) @@ -163,11 +163,11 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn 17'b0110011_0100000_100: if (`ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor - 17'b0010011_0110101_101: if (`XLEN == 64 & `ZBB_SUPPORTED) + 17'b0010011_0110101_101: if (`XLEN == 64 & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv64) - 17'b0010011_0110100_101: if (`XLEN == 32 & `ZBB_SUPPORTED) + 17'b0010011_0110100_101: if (`XLEN == 32 & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv32) - 17'b0010011_0010100_101: if (`ZBB_SUPPORTED) + 17'b0010011_0010100_101: if (`ZBB_SUPPORTED & Rs2D[4:0] == 5'b00111) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b 17'b0110011_0000101_110: if (`ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // max From b394e343f68ff18aec52d9c892d7adcd9a0fcb2f Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 20 Mar 2023 09:37:57 -0700 Subject: [PATCH 165/231] format + min/max structural mux --- src/ieu/bmu/zbb.sv | 4 ++-- src/ieu/controller.sv | 5 +---- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 70b984ead..ddf96b113 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -47,8 +47,8 @@ module zbb #(parameter WIDTH=32) ( byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult)); ext #(WIDTH) ext(.A(A), .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult(ExtResult)); - assign MaxResult = (lt) ? B : A; - assign MinResult = (lt) ? A : B; + mux2 #(WIDTH) maxmux(A, B, lt, MaxResult); + mux2 #(WIDTH) minmux(B, A, lt, MinResult); // ZBB Result select mux mux5 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinResult, MaxResult, ZBBSelect, ZBBResult); diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 4e20458cd..22c9d0577 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -246,13 +246,11 @@ module controller( assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD; assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand - assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source? assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001); assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i - // ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi @@ -268,7 +266,6 @@ module controller( assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; end else assign sltD = (Funct3D == 3'b010); - //assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; @@ -314,7 +311,7 @@ module controller( // The comparator handles both signed and unsigned branches using BranchSignedE // Hence, only eq and lt flags are needed // We also want comparator to handle signed comparison on a max/min bitmanip instruction - assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & BranchE) | BComparatorSignedE ; + assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & BranchE) | BComparatorSignedE; assign {eqE, ltE} = FlagsE; mux2 #(1) branchflagmux(eqE, ltE, Funct3E[2], BranchFlagE); assign BranchTakenE = BranchFlagE ^ Funct3E[0]; From 5056eb404cf53c083070cdefe633022a2de23d27 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 20 Mar 2023 13:09:49 -0700 Subject: [PATCH 166/231] formatting --- src/ieu/alu.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 99e14404a..de649b5e0 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -43,7 +43,7 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondMaskInvB, Shift, SLT, SLTU, FullResult,ALUResult; // Intermediate Signals + logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult,ALUResult; // Intermediate Signals logic [WIDTH-1:0] ZBCResult, ZBBResult; // Result of ZBB, ZBC logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux @@ -123,8 +123,8 @@ module alu #(parameter WIDTH=32) ( else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect 3'b000: FullResult = Sum; // add or sub 3'b001: FullResult = Shift; // sll, sra, or srl - 3'b010: FullResult = SLT; // slt - 3'b011: FullResult = SLTU; // sltu + 3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt + 3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset 3'b111: FullResult = A & CondMaskInvB; // and, bclr @@ -137,8 +137,8 @@ module alu #(parameter WIDTH=32) ( else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect 3'b000: FullResult = Sum; // add or sub 3'b?01: FullResult = Shift; // sll, sra, or srl - 3'b010: FullResult = SLT; // slt - 3'b011: FullResult = SLTU; // sltu + 3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt + 3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu 3'b100: FullResult = A ^ B; // xor 3'b110: FullResult = A | B; // or 3'b111: FullResult = A & B; // and From 4ecfa1bad31b191d1202aebeb382d48e38737d2b Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 20 Mar 2023 14:19:39 -0700 Subject: [PATCH 167/231] added bitmanip 64 tests to updated regression script + alu structural mux changes --- sim/regression-wally | 2 +- src/ieu/alu.sv | 7 +++---- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index 311104540..565f4f6d9 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -126,7 +126,7 @@ for test in ahbTests: grepstr="All tests ran without failures") configs.append(tc) -tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] +tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] if (coverage): # delete all but 64gc tests when running coverage configs = [] coverStr = '-coverage' diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index de649b5e0..110ca4181 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -77,7 +77,7 @@ module alu #(parameter WIDTH=32) ( if (`ZBS_SUPPORTED) begin: zbsdec decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); - assign CondMaskB = (Mask) ? MaskB : B; + mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB); end else assign CondMaskB = B; if (WIDTH == 64) begin @@ -89,9 +89,8 @@ module alu #(parameter WIDTH=32) ( end // shifter rotate source select mux - if (`ZBB_SUPPORTED) begin - if (WIDTH == 64) assign rotA = (W64) ? {A[31:0], A[31:0]} : A; - else assign rotA = A; + if (`ZBB_SUPPORTED & WIDTH == 64) begin + mux2 #(WIDTH) rotmux(A, {A[31:0], A[31:0]}, W64, rotA); end else assign rotA = A; if (`ZBA_SUPPORTED) begin: zbamuxes From 2ad807728cb0b5f495345713766e657559386c5c Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 20 Mar 2023 14:23:54 -0700 Subject: [PATCH 168/231] more structural mux changes --- src/ieu/bmu/byte.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index 19b71fc1e..524802358 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -42,6 +42,6 @@ module byteUnit #(parameter WIDTH=32) ( assign Rev8Result[WIDTH-i-1:WIDTH-i-8] = A[i+7:i]; end - assign ByteResult = (ByteSelect) ? OrcBResult : Rev8Result; + mux2 #(WIDTH) bytemux(Rev8Result, OrcBResult, ByteSelect, ByteResult); endmodule \ No newline at end of file From 72a8b25272f6b792efeb87d8f5489b426bcdcc35 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Mon, 20 Mar 2023 14:25:05 -0700 Subject: [PATCH 169/231] formatting --- src/ieu/bmu/byte.sv | 1 - src/ieu/bmu/clmul.sv | 1 - 2 files changed, 2 deletions(-) diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index 524802358..8cf3f0e56 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -43,5 +43,4 @@ module byteUnit #(parameter WIDTH=32) ( end mux2 #(WIDTH) bytemux(Rev8Result, OrcBResult, ByteSelect, ByteResult); - endmodule \ No newline at end of file diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index 16d600b43..85d427ed3 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -47,7 +47,6 @@ module clmul #(parameter WIDTH=32) ( ClmulResult[i] = s[WIDTH*i+j-1]; end end - endmodule From c8a5514ca570b06a4c7a49f4aaabe1536a92419a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 22 Mar 2023 10:14:12 -0700 Subject: [PATCH 170/231] formatting --- src/ieu/bmu/bitreverse.sv | 6 +++--- src/ieu/bmu/clmul.sv | 3 +-- src/ieu/bmu/cnt.sv | 6 +++--- src/ieu/bmu/popcnt.sv | 2 +- src/ieu/bmu/zbc.sv | 4 ++-- 5 files changed, 10 insertions(+), 11 deletions(-) diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index 644783e57..86024a348 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -30,12 +30,12 @@ `include "wally-config.vh" module bitreverse #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] a, - output logic [WIDTH-1:0] b); + input logic [WIDTH-1:0] A, + output logic [WIDTH-1:0] RevA); genvar i; for (i=0; i Date: Wed, 22 Mar 2023 10:25:54 -0700 Subject: [PATCH 171/231] min/max mux optimize --- src/ieu/bmu/bmuctrl.sv | 24 ++++++++++++------------ src/ieu/bmu/zbb.sv | 14 +++++++------- 2 files changed, 19 insertions(+), 19 deletions(-) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 936986cf3..b09bec11b 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -84,11 +84,11 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri 17'b0010011_0100101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) - 17'b0010011_0100100_101: if (`ZBS_SUPPORTED & `ZBS_SUPPORTED) + 17'b0010011_0100100_101: if (`ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti 17'b0010011_0100101_101: if (`XLEN == 64 & `ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) - 17'b0010011_0110100_001: if (`ZBS_SUPPORTED & `ZBS_SUPPORTED) + 17'b0010011_0110100_001: if (`ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi 17'b0010011_0110101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) @@ -141,13 +141,13 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror 17'b0111011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw - 17'b0010011_0110000_101: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) - 17'b0010011_0110001_101: if (`XLEN == 64 & `ZBB_SUPPORTED) + //17'b0010011_0110000_101: if (`ZBB_SUPPORTED) + // BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) + 17'b0010011_011000?_101: if ((`XLEN == 64 | ~Funct7D[0]) & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) 17'b0011011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw - 17'b0010011_0110000_001: if (Rs2D[2] & `ZBB_SUPPORTED & (Rs2D[4:1] == 4'b0010)) + 17'b0010011_0110000_001: if (`ZBB_SUPPORTED & (Rs2D[4:1] == 4'b0010)) BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction else if (`ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))) BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction @@ -163,16 +163,16 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn 17'b0110011_0100000_100: if (`ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor - 17'b0010011_0110101_101: if (`XLEN == 64 & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) - BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv64) - 17'b0010011_0110100_101: if (`XLEN == 32 & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) - BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv32) + 17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) + BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 + //17'b0010011_0110100_101: if (`XLEN == 32 & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) + // BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv32) 17'b0010011_0010100_101: if (`ZBB_SUPPORTED & Rs2D[4:0] == 5'b00111) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b 17'b0110011_0000101_110: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // max + BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // max 17'b0110011_0000101_111: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_100_1_0_0_1_0_0_0_0_0; // maxu + BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // maxu 17'b0110011_0000101_100: if (`ZBB_SUPPORTED) BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min 17'b0110011_0000101_101: if (`ZBB_SUPPORTED) diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index ddf96b113..89ae7beb4 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -39,17 +39,17 @@ module zbb #(parameter WIDTH=32) ( output logic [WIDTH-1:0] ZBBResult); // ZBB result logic [WIDTH-1:0] CntResult; // count result - logic [WIDTH-1:0] MinResult,MaxResult; // min,max result + logic [WIDTH-1:0] MinResult,MaxResult, MinMaxResult; // min,max result logic [WIDTH-1:0] ByteResult; // byte results logic [WIDTH-1:0] ExtResult; // sign/zero extend results - cnt #(WIDTH) cnt(.A(A), .RevA(RevA), .B(B[4:0]), .W64(W64), .CntResult(CntResult)); - byteUnit #(WIDTH) bu(.A(A), .ByteSelect(B[0]), .ByteResult(ByteResult)); - ext #(WIDTH) ext(.A(A), .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult(ExtResult)); + cnt #(WIDTH) cnt(.A, .RevA, .B(B[4:0]), .W64, .CntResult); + byteUnit #(WIDTH) bu(.A, .ByteSelect(B[0]), .ByteResult); + ext #(WIDTH) ext(.A, .ExtSelect({~B[2], {B[2] & B[0]}}), .ExtResult); - mux2 #(WIDTH) maxmux(A, B, lt, MaxResult); - mux2 #(WIDTH) minmux(B, A, lt, MinResult); + // ZBBSelect[2] differentiates between min(u) vs max(u) instruction + mux2 #(WIDTH) minmaxmux(B, A, lt^ZBBSelect[2], MinMaxResult); // ZBB Result select mux - mux5 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinResult, MaxResult, ZBBSelect, ZBBResult); + mux4 #(WIDTH) zbbresultmux(CntResult, ExtResult, ByteResult, MinMaxResult, ZBBSelect[1:0], ZBBResult); endmodule \ No newline at end of file From fce62fc2136af02198cdd52a743f4223a754f56a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 22 Mar 2023 10:26:04 -0700 Subject: [PATCH 172/231] formatting --- src/ieu/alu.sv | 12 ++++++------ src/ieu/controller.sv | 4 +++- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 110ca4181..7e38b1a65 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -93,7 +93,7 @@ module alu #(parameter WIDTH=32) ( mux2 #(WIDTH) rotmux(A, {A[31:0], A[31:0]}, W64, rotA); end else assign rotA = A; - if (`ZBA_SUPPORTED) begin: zbamuxes + if (`ZBA_SUPPORTED) begin: zbapreshift // Pre-Shift assign CondShiftA = CondExtA << (PreShiftAmt); end else assign CondShiftA = A; @@ -103,7 +103,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) - shifter sh(.shA(CondExtA), .Sign(shSignA), .rotA(rotA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64(W64), .Y(Shift), .Rotate(Rotate)); + shifter sh(.shA(CondExtA), .Sign(shSignA), .rotA, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .Y(Shift), .Rotate); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign @@ -125,9 +125,9 @@ module alu #(parameter WIDTH=32) ( 3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt 3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv + 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}};// bext 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset 3'b111: FullResult = A & CondMaskInvB; // and, bclr - 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}};// bext endcase end else begin @@ -145,15 +145,15 @@ module alu #(parameter WIDTH=32) ( end if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse - bitreverse #(WIDTH) brA(.a(A), .b(RevA)); + bitreverse #(WIDTH) brA(.A, .RevA); end if (`ZBC_SUPPORTED) begin: zbc - zbc #(WIDTH) ZBC(.A(A), .RevA(RevA), .B(B), .Funct3(Funct3), .ZBCResult(ZBCResult)); + zbc #(WIDTH) ZBC(.A, .RevA, .B, .Funct3, .ZBCResult); end else assign ZBCResult = 0; if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A(A), .RevA(RevA), .B(B), .ALUResult(ALUResult), .W64(W64), .lt(CompFlags[0]), .ZBBSelect(ZBBSelect), .ZBBResult(ZBBResult)); + zbb #(WIDTH) ZBB(.A, .RevA, .B, .ALUResult, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult); end else assign ZBBResult = 0; // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 168f6af11..5c397d157 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -260,7 +260,9 @@ module controller( // bit manipulation Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BALUSrcBD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, + .BRegWriteD, .BALUSrcBD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, + .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); if (`ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; From f7a915a71a742a9b80a2c06b0a37c5cd30857073 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 22 Mar 2023 10:27:59 -0700 Subject: [PATCH 173/231] remove helper python script --- src/ieu/bmu/bitfieldedit.py | 32 -------------------------------- 1 file changed, 32 deletions(-) delete mode 100644 src/ieu/bmu/bitfieldedit.py diff --git a/src/ieu/bmu/bitfieldedit.py b/src/ieu/bmu/bitfieldedit.py deleted file mode 100644 index a9f604a33..000000000 --- a/src/ieu/bmu/bitfieldedit.py +++ /dev/null @@ -1,32 +0,0 @@ -""" - bitfieldedit.py - Script that appends 0 just before the "illegal instruction" field of the bitstring - Written by Kevin Kim -""" -def addZero(s): - try: - indexSemicolon = s.index(";") - newS = s[:indexSemicolon-1]+"0_"+s[indexSemicolon-1:] - return newS - except: return s - -def main(): - filename = input("Enter full filename: ") - n1 = int(input("Line number to begin: ")) - n2 = int(input("Line number to end: ")) - f = open(filename, "r") - flines = f.readlines() - - #create list of lines from line n1 to n2, inclusive - lines = flines[(n1-1):(n2-1)] - - #string to be printed - out = "" - - for i in range(len(lines)): - lines[i] = addZero(lines[i]) - out += lines[i] - print(out) - -if __name__ == "__main__": - main() \ No newline at end of file From efa9f0986470d2df997772e173c620e302579ec8 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 22 Mar 2023 10:31:21 -0700 Subject: [PATCH 174/231] updated header comments to indicate chapter 15 --- src/ieu/bmu/bitreverse.sv | 2 +- src/ieu/bmu/bmuctrl.sv | 4 +--- src/ieu/bmu/byte.sv | 2 +- src/ieu/bmu/clmul.sv | 2 +- src/ieu/bmu/cnt.sv | 2 +- src/ieu/bmu/ext.sv | 2 +- src/ieu/bmu/popcnt.sv | 2 ++ src/ieu/bmu/zbb.sv | 2 +- src/ieu/bmu/zbc.sv | 2 +- 9 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/ieu/bmu/bitreverse.sv b/src/ieu/bmu/bitreverse.sv index 86024a348..e2afb0c95 100644 --- a/src/ieu/bmu/bitreverse.sv +++ b/src/ieu/bmu/bitreverse.sv @@ -8,7 +8,7 @@ // // Purpose: Bit reverse submodule // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index b09bec11b..ae401ef88 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -7,7 +7,7 @@ // // Purpose: Top level bit manipulation instruction decoder // -// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5) +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // @@ -165,8 +165,6 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor 17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 - //17'b0010011_0110100_101: if (`XLEN == 32 & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) - // BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 (rv32) 17'b0010011_0010100_101: if (`ZBB_SUPPORTED & Rs2D[4:0] == 5'b00111) BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b 17'b0110011_0000101_110: if (`ZBB_SUPPORTED) diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index 8cf3f0e56..db7a3b45c 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -7,7 +7,7 @@ // // Purpose: RISCV bitmanip byte-wise operation unit // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/clmul.sv b/src/ieu/bmu/clmul.sv index b96f3af60..904c64238 100644 --- a/src/ieu/bmu/clmul.sv +++ b/src/ieu/bmu/clmul.sv @@ -7,7 +7,7 @@ // // Purpose: Carry-Less multiplication unit // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 296e6d383..13ff1e15f 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -8,7 +8,7 @@ // // Purpose: Count Instruction Submodule // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 250616b58..12e690436 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -8,7 +8,7 @@ // // Purpose: Sign/Zero Extension Submodule // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index f7e18b151..77c4b6158 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -6,6 +6,8 @@ // // Purpose: Population Count // +// Documentation: RISC-V System on Chip Design Chapter 15 +// // A component of the CORE-V-WALLY configurable RISC-V project. // // Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 89ae7beb4..1e2c8437b 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -8,7 +8,7 @@ // // Purpose: RISC-V ZBB top level unit // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // diff --git a/src/ieu/bmu/zbc.sv b/src/ieu/bmu/zbc.sv index 5ed04bc02..05e05d38f 100644 --- a/src/ieu/bmu/zbc.sv +++ b/src/ieu/bmu/zbc.sv @@ -7,7 +7,7 @@ // // Purpose: RISC-V ZBC top-level unit // -// Documentation: RISC-V System on Chip Design Chapter *** +// Documentation: RISC-V System on Chip Design Chapter 15 // // A component of the CORE-V-WALLY configurable RISC-V project. // From fd00e386b5d0c967a00cb2df980ceda9db61549f Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Wed, 22 Mar 2023 10:34:17 -0700 Subject: [PATCH 175/231] remove outdated --- src/ieu/bmu/zbb.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ieu/bmu/zbb.sv b/src/ieu/bmu/zbb.sv index 1e2c8437b..5d1c52f1d 100644 --- a/src/ieu/bmu/zbb.sv +++ b/src/ieu/bmu/zbb.sv @@ -39,7 +39,7 @@ module zbb #(parameter WIDTH=32) ( output logic [WIDTH-1:0] ZBBResult); // ZBB result logic [WIDTH-1:0] CntResult; // count result - logic [WIDTH-1:0] MinResult,MaxResult, MinMaxResult; // min,max result + logic [WIDTH-1:0] MinMaxResult; // min,max result logic [WIDTH-1:0] ByteResult; // byte results logic [WIDTH-1:0] ExtResult; // sign/zero extend results From 31021265b85b1a1f8ecf988a874273baf2020516 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 22 Mar 2023 11:17:17 -0700 Subject: [PATCH 176/231] Makefile improvements --- .gitignore | 2 ++ tests/coverage/Makefile | 28 +++++++++++++++++++++------- tests/coverage/badinstr.S | 12 ------------ 3 files changed, 23 insertions(+), 19 deletions(-) diff --git a/.gitignore b/.gitignore index 38d466cd8..1f8e8b158 100644 --- a/.gitignore +++ b/.gitignore @@ -112,3 +112,5 @@ sim/results-error/ sim/test1.rep sim/vsim.log tests/coverage/*.S +tests/coverage/*.elf +*.elf.memfile \ No newline at end of file diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index e026fa41b..57a8a1b51 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -1,13 +1,27 @@ -SRCS = $(wildcard *.S) -PROGS = $(patsubst %.S,%,$(SRCS)) +CEXT := c +CPPEXT := cpp +AEXT := s +SEXT := S +SRCEXT := \([$(CEXT)$(AEXT)$(SEXT)]\|$(CPPEXT)\) +#SRCS = $(wildcard *.S) +#PROGS = $(patsubst %.S,%,$(SRCS)) +SRCDIR = . +SRCEXT = S +SOURCES ?= $(shell find $(SRCDIR) -type f -regex ".*\.$(SRCEXT)" | sort) +OBJEXT = elf +OBJECTS := $(SOURCES:.$(SEXT)=.$(OBJEXT)) -all: $(PROGS) +all: $(OBJECTS) -%: %.S WALLY-init-lib.h Makefile +%.elf.objdump: %.elf + +%.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile echo $@ - riscv64-unknown-elf-gcc -g -o $@.elf -march=rv64gc -mabi=lp64 -mcmodel=medany \ - -nostartfiles -T../../examples/link/link.ld $@.S - riscv64-unknown-elf-objdump -D $@.elf > $@.objdump + riscv64-unknown-elf-gcc -g -o $@ -march=rv64gc -mabi=lp64 -mcmodel=medany \ + -nostartfiles -T../../examples/link/link.ld $< + riscv64-unknown-elf-objdump -D $@ > $@.objdump + riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv64,$*),64,32) --input $@ --output $@.memfile + extractFunctionRadix.sh $@.objdump sim: %.elf spike +signature=%.signature.output +signature-granularity=8 %.elf diff --git a/tests/coverage/badinstr.S b/tests/coverage/badinstr.S index e77f5c980..ec875eaac 100644 --- a/tests/coverage/badinstr.S +++ b/tests/coverage/badinstr.S @@ -33,16 +33,4 @@ main: .word 0x00000000 // illegal instruction j done -/* -main: - # Change to user mode - li a0, 0 # a0 = 0: argument to enter user mode - ecall # System call to enter user mode - # Wait for timer interrupts - li t0, 0x1000 # loop counter start value -loop: - addi t0, t0, -1 # decrement counter - bne t0, zero, loop # and repeat until zero - -*/ \ No newline at end of file From 3b3aa942c75744fd6fe610769a91442b68d7c273 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 22 Mar 2023 13:00:10 -0700 Subject: [PATCH 177/231] Added coverage tests to regression coverage --- sim/regression-wally | 3 +-- testbench/testbench.sv | 31 +++++++++++++++++-------------- testbench/tests.vh | 18 +++++++++++------- tests/coverage/Makefile | 5 +++-- 4 files changed, 32 insertions(+), 25 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index 683f30a93..9be1839a6 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -130,8 +130,7 @@ for test in ahbTests: tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] if (coverage): # delete all but 64gc tests when running coverage configs = [] - tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv", "imperas64f", "imperas64d", "imperas64c", "imperas64i"] -# tests64gc.append(["imperas64f", "imperas64d", "imperas64c", "imperas64i"]) + tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv", "imperas64f", "imperas64d", "imperas64c", "imperas64i"] coverStr = '-coverage' else: coverStr = '' diff --git a/testbench/testbench.sv b/testbench/testbench.sv index fe3875cbb..cef2d986f 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -106,6 +106,7 @@ logic [3:0] dummy; "coremark": tests = coremark; "fpga": tests = fpga; "ahb" : tests = ahb; + "coverage64gc" : tests = coverage64gc; endcase end else begin // RV32 case (TEST) @@ -299,20 +300,22 @@ logic [3:0] dummy; testadrNoBase = (begin_signature_addr - `UNCORE_RAM_BASE)/(`XLEN/8); #600; // give time for instructions in pipeline to finish if (TEST == "embench") begin - // Writes contents of begin_signature to .sim.output file - // this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score - // also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking - $display("Embench Benchmark: %s is done.", tests[test]); - if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"}; - else outputfile = {pathname, tests[test], ".sim.output"}; - outputFilePointer = $fopen(outputfile); - i = 0; - while ($unsigned(i) < $unsigned(5'd5)) begin - $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]); - i = i + 1; - end - $fclose(outputFilePointer); - $display("Embench Benchmark: created output file: %s", outputfile); + // Writes contents of begin_signature to .sim.output file + // this contains instret and cycles for start and end of test run, used by embench python speed script to calculate embench speed score + // also begin_signature contains the results of the self checking mechanism, which will be read by the python script for error checking + $display("Embench Benchmark: %s is done.", tests[test]); + if (riscofTest) outputfile = {pathname, tests[test], "/ref/ref.sim.output"}; + else outputfile = {pathname, tests[test], ".sim.output"}; + outputFilePointer = $fopen(outputfile); + i = 0; + while ($unsigned(i) < $unsigned(5'd5)) begin + $fdisplayh(outputFilePointer, DCacheFlushFSM.ShadowRAM[testadr+i]); + i = i + 1; + end + $fclose(outputFilePointer); + $display("Embench Benchmark: created output file: %s", outputfile); + end else if (TEST == "coverage64gc") begin + $display("Coverage tests don't get checked"); end else begin // for tests with no self checking mechanism, read .signature.output file and compare to check for errors // clear signature to prevent contamination from previous tests diff --git a/testbench/tests.vh b/testbench/tests.vh index eff013a5b..4ca08a5e0 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -27,22 +27,26 @@ `define IMPERASTEST "0" `define RISCVARCHTEST "1" `define WALLYTEST "2" -`define MYIMPERASTEST "3" -`define COREMARK "4" -`define EMBENCH "5" -`define CUSTOM "6" -// *** remove MYIMPERASTEST cases when ported +`define COREMARK "3" +`define EMBENCH "4" +`define CUSTOM "5" +`define COVERAGE "6" string tvpaths[] = '{ "$RISCV/imperas-riscv-tests/work/", "../tests/riscof/work/riscv-arch-test/", "../tests/riscof/work/wally-riscv-arch-test/", - "../tests/imperas-riscv-tests/work/", "../benchmarks/coremark/work/", "../addins/embench-iot/", - "../tests/custom/work/" + "../tests/custom/work/", + "../tests/coverage/" }; + string coverage64gc[] = '{ + `COVERAGE, + "badinstr" + }; + string coremark[] = '{ `COREMARK, "coremark.bare.riscv" diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index 57a8a1b51..8742dee63 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -16,11 +16,12 @@ all: $(OBJECTS) %.elf.objdump: %.elf %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile + # Change many things if bit width isn't 64 echo $@ riscv64-unknown-elf-gcc -g -o $@ -march=rv64gc -mabi=lp64 -mcmodel=medany \ -nostartfiles -T../../examples/link/link.ld $< riscv64-unknown-elf-objdump -D $@ > $@.objdump - riscv64-unknown-elf-elf2hex --bit-width $(if $(findstring rv64,$*),64,32) --input $@ --output $@.memfile + riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile extractFunctionRadix.sh $@.objdump sim: %.elf @@ -29,7 +30,7 @@ sim: %.elf echo "Signature matches! Success!" clean: - rm -f *.elf *.objdump *.signature.output + rm -f *.elf *.objdump *.signature.output *.addr *.lab *.memfile From 44b5e234bdfb30266afc23c4d8248eb37094caae Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 13:23:52 -0700 Subject: [PATCH 178/231] Removed unused ISA string from spike YAML --- tests/riscof/spike/spike_rv32gc_isa.yaml | 1 - tests/riscof/spike/spike_rv64gc_isa.yaml | 1 - 2 files changed, 2 deletions(-) diff --git a/tests/riscof/spike/spike_rv32gc_isa.yaml b/tests/riscof/spike/spike_rv32gc_isa.yaml index 05fc6f60e..3438e17a0 100644 --- a/tests/riscof/spike/spike_rv32gc_isa.yaml +++ b/tests/riscof/spike/spike_rv32gc_isa.yaml @@ -1,6 +1,5 @@ hart_ids: [0] hart0: - #ISA: RV32IMAFDCZicsr_Zifencei ISA: RV32IMAFDCZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 32 User_Spec_Version: '2.3' diff --git a/tests/riscof/spike/spike_rv64gc_isa.yaml b/tests/riscof/spike/spike_rv64gc_isa.yaml index e6bfc72ef..a8837ac76 100644 --- a/tests/riscof/spike/spike_rv64gc_isa.yaml +++ b/tests/riscof/spike/spike_rv64gc_isa.yaml @@ -1,6 +1,5 @@ hart_ids: [0] hart0: -# ISA: RV64IMAFDCSUZicsr_Zifencei ISA: RV64IMAFDCSUZicsr_Zifencei_Zba_Zbb_Zbc_Zbs physical_addr_sz: 56 User_Spec_Version: '2.3' From 03472ec7bb2d7c27685a0ca7e0f35e1ceefa5989 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 13:32:24 -0700 Subject: [PATCH 179/231] restored sim-wally-batch to existing tests --- sim/sim-wally-batch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/sim-wally-batch b/sim/sim-wally-batch index 95fc677c6..4fa06d3cf 100755 --- a/sim/sim-wally-batch +++ b/sim/sim-wally-batch @@ -1 +1 @@ -vsim -c -do "do wally-batch.do rv64gc arch64b" +vsim -c -do "do wally-batch.do rv32gc wally32priv" \ No newline at end of file From da2037f89318ea3d73fa555091a38853b3105dfb Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 14:11:42 -0700 Subject: [PATCH 180/231] restored Imperas test names --- testbench/tests.vh | 1455 +++++++++++++++++++++----------------------- 1 file changed, 698 insertions(+), 757 deletions(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 106332765..17d9fea0c 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -98,755 +98,755 @@ string tvpaths[] = '{ string imperas32f[] = '{ `IMPERASTEST, - "rv32i_m/F/FSQRT-S-DYN-RDN-01.S", - "rv32i_m/F/FADD-S-DYN-RDN-01.S", - "rv32i_m/F/FADD-S-DYN-RMM-01.S", - "rv32i_m/F/FADD-S-DYN-RNE-01.S", - "rv32i_m/F/FADD-S-DYN-RTZ-01.S", - "rv32i_m/F/FADD-S-DYN-RUP-01.S", - "rv32i_m/F/FADD-S-RDN-01.S", - "rv32i_m/F/FADD-S-RMM-01.S", - "rv32i_m/F/FADD-S-RNE-01.S", - "rv32i_m/F/FADD-S-RTZ-01.S", - "rv32i_m/F/FADD-S-RUP-01.S", - "rv32i_m/F/FCLASS-S-01.S", - "rv32i_m/F/FCVT-S-W-DYN-RDN-01.S", - "rv32i_m/F/FCVT-S-W-DYN-RMM-01.S", - "rv32i_m/F/FCVT-S-W-DYN-RNE-01.S", - "rv32i_m/F/FCVT-S-W-DYN-RTZ-01.S", - "rv32i_m/F/FCVT-S-W-DYN-RUP-01.S", - "rv32i_m/F/FCVT-S-W-RDN-01.S", - "rv32i_m/F/FCVT-S-W-RMM-01.S", - "rv32i_m/F/FCVT-S-W-RNE-01.S", - "rv32i_m/F/FCVT-S-W-RTZ-01.S", - "rv32i_m/F/FCVT-S-W-RUP-01.S", - "rv32i_m/F/FCVT-S-WU-DYN-RDN-01.S", - "rv32i_m/F/FCVT-S-WU-DYN-RMM-01.S", - "rv32i_m/F/FCVT-S-WU-DYN-RNE-01.S", - "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01.S", - "rv32i_m/F/FCVT-S-WU-DYN-RUP-01.S", - "rv32i_m/F/FCVT-S-WU-RDN-01.S", - "rv32i_m/F/FCVT-S-WU-RMM-01.S", - "rv32i_m/F/FCVT-S-WU-RNE-01.S", - "rv32i_m/F/FCVT-S-WU-RTZ-01.S", - "rv32i_m/F/FCVT-S-WU-RUP-01.S", - "rv32i_m/F/FCVT-W-S-DYN-RDN-01.S", - "rv32i_m/F/FCVT-W-S-DYN-RMM-01.S", - "rv32i_m/F/FCVT-W-S-DYN-RNE-01.S", - "rv32i_m/F/FCVT-W-S-DYN-RTZ-01.S", - "rv32i_m/F/FCVT-W-S-DYN-RUP-01.S", - "rv32i_m/F/FCVT-W-S-RDN-01.S", - "rv32i_m/F/FCVT-W-S-RMM-01.S", - "rv32i_m/F/FCVT-W-S-RNE-01.S", - "rv32i_m/F/FCVT-W-S-RTZ-01.S", - "rv32i_m/F/FCVT-W-S-RUP-01.S", - "rv32i_m/F/FCVT-WU-S-DYN-RDN-01.S", - "rv32i_m/F/FCVT-WU-S-DYN-RMM-01.S", - "rv32i_m/F/FCVT-WU-S-DYN-RNE-01.S", - "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01.S", - "rv32i_m/F/FCVT-WU-S-DYN-RUP-01.S", - "rv32i_m/F/FCVT-WU-S-RDN-01.S", - "rv32i_m/F/FCVT-WU-S-RMM-01.S", - "rv32i_m/F/FCVT-WU-S-RNE-01.S", - "rv32i_m/F/FCVT-WU-S-RTZ-01.S", - "rv32i_m/F/FCVT-WU-S-RUP-01.S", - "rv32i_m/F/FDIV-S-DYN-RDN-01.S", - "rv32i_m/F/FDIV-S-DYN-RMM-01.S", - "rv32i_m/F/FDIV-S-DYN-RNE-01.S", - "rv32i_m/F/FDIV-S-DYN-RTZ-01.S", - "rv32i_m/F/FDIV-S-DYN-RUP-01.S", - "rv32i_m/F/FDIV-S-RDN-01.S", - "rv32i_m/F/FDIV-S-RMM-01.S", - "rv32i_m/F/FDIV-S-RNE-01.S", - "rv32i_m/F/FDIV-S-RTZ-01.S", - "rv32i_m/F/FDIV-S-RUP-01.S", - "rv32i_m/F/FEQ-S-01.S", - "rv32i_m/F/FLE-S-01.S", - "rv32i_m/F/FLT-S-01.S", - "rv32i_m/F/FLW-01.S", - "rv32i_m/F/FMADD-S-DYN-RDN-01.S", - "rv32i_m/F/FMADD-S-DYN-RMM-01.S", - "rv32i_m/F/FMADD-S-DYN-RNE-01.S", - "rv32i_m/F/FMADD-S-DYN-RTZ-01.S", - "rv32i_m/F/FMADD-S-DYN-RUP-01.S", - "rv32i_m/F/FMADD-S-RDN-01.S", - "rv32i_m/F/FMADD-S-RMM-01.S", - "rv32i_m/F/FMADD-S-RNE-01.S", - "rv32i_m/F/FMADD-S-RTZ-01.S", - "rv32i_m/F/FMADD-S-RUP-01.S", - "rv32i_m/F/FMAX-S-01.S", - "rv32i_m/F/FMIN-S-01.S", - "rv32i_m/F/FMSUB-S-DYN-RDN-01.S", - "rv32i_m/F/FMSUB-S-DYN-RMM-01.S", - "rv32i_m/F/FMSUB-S-DYN-RNE-01.S", - "rv32i_m/F/FMSUB-S-DYN-RTZ-01.S", - "rv32i_m/F/FMSUB-S-DYN-RUP-01.S", - "rv32i_m/F/FMSUB-S-RDN-01.S", - "rv32i_m/F/FMSUB-S-RMM-01.S", - "rv32i_m/F/FMSUB-S-RNE-01.S", - "rv32i_m/F/FMSUB-S-RTZ-01.S", - "rv32i_m/F/FMSUB-S-RUP-01.S", - "rv32i_m/F/FMUL-S-DYN-RDN-01.S", - "rv32i_m/F/FMUL-S-DYN-RMM-01.S", - "rv32i_m/F/FMUL-S-DYN-RNE-01.S", - "rv32i_m/F/FMUL-S-DYN-RTZ-01.S", - "rv32i_m/F/FMUL-S-DYN-RUP-01.S", - "rv32i_m/F/FMUL-S-RDN-01.S", - "rv32i_m/F/FMUL-S-RMM-01.S", - "rv32i_m/F/FMUL-S-RNE-01.S", - "rv32i_m/F/FMUL-S-RTZ-01.S", - "rv32i_m/F/FMUL-S-RUP-01.S", - "rv32i_m/F/FMV-W-X-01.S", - "rv32i_m/F/FMV-X-W-01.S", - "rv32i_m/F/FNMADD-S-DYN-RDN-01.S", - "rv32i_m/F/FNMADD-S-DYN-RMM-01.S", - "rv32i_m/F/FNMADD-S-DYN-RNE-01.S", - "rv32i_m/F/FNMADD-S-DYN-RTZ-01.S", - "rv32i_m/F/FNMADD-S-DYN-RUP-01.S", - "rv32i_m/F/FNMADD-S-RDN-01.S", - "rv32i_m/F/FNMADD-S-RMM-01.S", - "rv32i_m/F/FNMADD-S-RNE-01.S", - "rv32i_m/F/FNMADD-S-RTZ-01.S", - "rv32i_m/F/FNMADD-S-RUP-01.S", - "rv32i_m/F/FNMSUB-S-DYN-RDN-01.S", - "rv32i_m/F/FNMSUB-S-DYN-RMM-01.S", - "rv32i_m/F/FNMSUB-S-DYN-RNE-01.S", - "rv32i_m/F/FNMSUB-S-DYN-RTZ-01.S", - "rv32i_m/F/FNMSUB-S-DYN-RUP-01.S", - "rv32i_m/F/FNMSUB-S-RDN-01.S", - "rv32i_m/F/FNMSUB-S-RMM-01.S", - "rv32i_m/F/FNMSUB-S-RNE-01.S", - "rv32i_m/F/FNMSUB-S-RTZ-01.S", - "rv32i_m/F/FNMSUB-S-RUP-01.S", - "rv32i_m/F/FSGNJN-S-01.S", - "rv32i_m/F/FSGNJ-S-01.S", - "rv32i_m/F/FSGNJX-S-01.S", - "rv32i_m/F/FSQRT-S-DYN-RDN-01.S", - "rv32i_m/F/FSQRT-S-DYN-RMM-01.S", - "rv32i_m/F/FSQRT-S-DYN-RNE-01.S", - "rv32i_m/F/FSQRT-S-DYN-RTZ-01.S", - "rv32i_m/F/FSQRT-S-DYN-RUP-01.S", - "rv32i_m/F/FSQRT-S-RDN-01.S", - "rv32i_m/F/FSQRT-S-RMM-01.S", - "rv32i_m/F/FSQRT-S-RNE-01.S", - "rv32i_m/F/FSQRT-S-RTZ-01.S", - "rv32i_m/F/FSQRT-S-RUP-01.S", - "rv32i_m/F/FSUB-S-DYN-RDN-01.S", - "rv32i_m/F/FSUB-S-DYN-RMM-01.S", - "rv32i_m/F/FSUB-S-DYN-RNE-01.S", - "rv32i_m/F/FSUB-S-DYN-RTZ-01.S", - "rv32i_m/F/FSUB-S-DYN-RUP-01.S", - "rv32i_m/F/FSUB-S-RDN-01.S", - "rv32i_m/F/FSUB-S-RMM-01.S", - "rv32i_m/F/FSUB-S-RNE-01.S", - "rv32i_m/F/FSUB-S-RTZ-01.S", - "rv32i_m/F/FSUB-S-RUP-01.S", - "rv32i_m/F/FSW-01.S" + "rv32i_m/F/FSQRT-S-DYN-RDN-01", + "rv32i_m/F/FADD-S-DYN-RDN-01", + "rv32i_m/F/FADD-S-DYN-RMM-01", + "rv32i_m/F/FADD-S-DYN-RNE-01", + "rv32i_m/F/FADD-S-DYN-RTZ-01", + "rv32i_m/F/FADD-S-DYN-RUP-01", + "rv32i_m/F/FADD-S-RDN-01", + "rv32i_m/F/FADD-S-RMM-01", + "rv32i_m/F/FADD-S-RNE-01", + "rv32i_m/F/FADD-S-RTZ-01", + "rv32i_m/F/FADD-S-RUP-01", + "rv32i_m/F/FCLASS-S-01", + "rv32i_m/F/FCVT-S-W-DYN-RDN-01", + "rv32i_m/F/FCVT-S-W-DYN-RMM-01", + "rv32i_m/F/FCVT-S-W-DYN-RNE-01", + "rv32i_m/F/FCVT-S-W-DYN-RTZ-01", + "rv32i_m/F/FCVT-S-W-DYN-RUP-01", + "rv32i_m/F/FCVT-S-W-RDN-01", + "rv32i_m/F/FCVT-S-W-RMM-01", + "rv32i_m/F/FCVT-S-W-RNE-01", + "rv32i_m/F/FCVT-S-W-RTZ-01", + "rv32i_m/F/FCVT-S-W-RUP-01", + "rv32i_m/F/FCVT-S-WU-DYN-RDN-01", + "rv32i_m/F/FCVT-S-WU-DYN-RMM-01", + "rv32i_m/F/FCVT-S-WU-DYN-RNE-01", + "rv32i_m/F/FCVT-S-WU-DYN-RTZ-01", + "rv32i_m/F/FCVT-S-WU-DYN-RUP-01", + "rv32i_m/F/FCVT-S-WU-RDN-01", + "rv32i_m/F/FCVT-S-WU-RMM-01", + "rv32i_m/F/FCVT-S-WU-RNE-01", + "rv32i_m/F/FCVT-S-WU-RTZ-01", + "rv32i_m/F/FCVT-S-WU-RUP-01", + "rv32i_m/F/FCVT-W-S-DYN-RDN-01", + "rv32i_m/F/FCVT-W-S-DYN-RMM-01", + "rv32i_m/F/FCVT-W-S-DYN-RNE-01", + "rv32i_m/F/FCVT-W-S-DYN-RTZ-01", + "rv32i_m/F/FCVT-W-S-DYN-RUP-01", + "rv32i_m/F/FCVT-W-S-RDN-01", + "rv32i_m/F/FCVT-W-S-RMM-01", + "rv32i_m/F/FCVT-W-S-RNE-01", + "rv32i_m/F/FCVT-W-S-RTZ-01", + "rv32i_m/F/FCVT-W-S-RUP-01", + "rv32i_m/F/FCVT-WU-S-DYN-RDN-01", + "rv32i_m/F/FCVT-WU-S-DYN-RMM-01", + "rv32i_m/F/FCVT-WU-S-DYN-RNE-01", + "rv32i_m/F/FCVT-WU-S-DYN-RTZ-01", + "rv32i_m/F/FCVT-WU-S-DYN-RUP-01", + "rv32i_m/F/FCVT-WU-S-RDN-01", + "rv32i_m/F/FCVT-WU-S-RMM-01", + "rv32i_m/F/FCVT-WU-S-RNE-01", + "rv32i_m/F/FCVT-WU-S-RTZ-01", + "rv32i_m/F/FCVT-WU-S-RUP-01", + "rv32i_m/F/FDIV-S-DYN-RDN-01", + "rv32i_m/F/FDIV-S-DYN-RMM-01", + "rv32i_m/F/FDIV-S-DYN-RNE-01", + "rv32i_m/F/FDIV-S-DYN-RTZ-01", + "rv32i_m/F/FDIV-S-DYN-RUP-01", + "rv32i_m/F/FDIV-S-RDN-01", + "rv32i_m/F/FDIV-S-RMM-01", + "rv32i_m/F/FDIV-S-RNE-01", + "rv32i_m/F/FDIV-S-RTZ-01", + "rv32i_m/F/FDIV-S-RUP-01", + "rv32i_m/F/FEQ-S-01", + "rv32i_m/F/FLE-S-01", + "rv32i_m/F/FLT-S-01", + "rv32i_m/F/FLW-01", + "rv32i_m/F/FMADD-S-DYN-RDN-01", + "rv32i_m/F/FMADD-S-DYN-RMM-01", + "rv32i_m/F/FMADD-S-DYN-RNE-01", + "rv32i_m/F/FMADD-S-DYN-RTZ-01", + "rv32i_m/F/FMADD-S-DYN-RUP-01", + "rv32i_m/F/FMADD-S-RDN-01", + "rv32i_m/F/FMADD-S-RMM-01", + "rv32i_m/F/FMADD-S-RNE-01", + "rv32i_m/F/FMADD-S-RTZ-01", + "rv32i_m/F/FMADD-S-RUP-01", + "rv32i_m/F/FMAX-S-01", + "rv32i_m/F/FMIN-S-01", + "rv32i_m/F/FMSUB-S-DYN-RDN-01", + "rv32i_m/F/FMSUB-S-DYN-RMM-01", + "rv32i_m/F/FMSUB-S-DYN-RNE-01", + "rv32i_m/F/FMSUB-S-DYN-RTZ-01", + "rv32i_m/F/FMSUB-S-DYN-RUP-01", + "rv32i_m/F/FMSUB-S-RDN-01", + "rv32i_m/F/FMSUB-S-RMM-01", + "rv32i_m/F/FMSUB-S-RNE-01", + "rv32i_m/F/FMSUB-S-RTZ-01", + "rv32i_m/F/FMSUB-S-RUP-01", + "rv32i_m/F/FMUL-S-DYN-RDN-01", + "rv32i_m/F/FMUL-S-DYN-RMM-01", + "rv32i_m/F/FMUL-S-DYN-RNE-01", + "rv32i_m/F/FMUL-S-DYN-RTZ-01", + "rv32i_m/F/FMUL-S-DYN-RUP-01", + "rv32i_m/F/FMUL-S-RDN-01", + "rv32i_m/F/FMUL-S-RMM-01", + "rv32i_m/F/FMUL-S-RNE-01", + "rv32i_m/F/FMUL-S-RTZ-01", + "rv32i_m/F/FMUL-S-RUP-01", + "rv32i_m/F/FMV-W-X-01", + "rv32i_m/F/FMV-X-W-01", + "rv32i_m/F/FNMADD-S-DYN-RDN-01", + "rv32i_m/F/FNMADD-S-DYN-RMM-01", + "rv32i_m/F/FNMADD-S-DYN-RNE-01", + "rv32i_m/F/FNMADD-S-DYN-RTZ-01", + "rv32i_m/F/FNMADD-S-DYN-RUP-01", + "rv32i_m/F/FNMADD-S-RDN-01", + "rv32i_m/F/FNMADD-S-RMM-01", + "rv32i_m/F/FNMADD-S-RNE-01", + "rv32i_m/F/FNMADD-S-RTZ-01", + "rv32i_m/F/FNMADD-S-RUP-01", + "rv32i_m/F/FNMSUB-S-DYN-RDN-01", + "rv32i_m/F/FNMSUB-S-DYN-RMM-01", + "rv32i_m/F/FNMSUB-S-DYN-RNE-01", + "rv32i_m/F/FNMSUB-S-DYN-RTZ-01", + "rv32i_m/F/FNMSUB-S-DYN-RUP-01", + "rv32i_m/F/FNMSUB-S-RDN-01", + "rv32i_m/F/FNMSUB-S-RMM-01", + "rv32i_m/F/FNMSUB-S-RNE-01", + "rv32i_m/F/FNMSUB-S-RTZ-01", + "rv32i_m/F/FNMSUB-S-RUP-01", + "rv32i_m/F/FSGNJN-S-01", + "rv32i_m/F/FSGNJ-S-01", + "rv32i_m/F/FSGNJX-S-01", + "rv32i_m/F/FSQRT-S-DYN-RDN-01", + "rv32i_m/F/FSQRT-S-DYN-RMM-01", + "rv32i_m/F/FSQRT-S-DYN-RNE-01", + "rv32i_m/F/FSQRT-S-DYN-RTZ-01", + "rv32i_m/F/FSQRT-S-DYN-RUP-01", + "rv32i_m/F/FSQRT-S-RDN-01", + "rv32i_m/F/FSQRT-S-RMM-01", + "rv32i_m/F/FSQRT-S-RNE-01", + "rv32i_m/F/FSQRT-S-RTZ-01", + "rv32i_m/F/FSQRT-S-RUP-01", + "rv32i_m/F/FSUB-S-DYN-RDN-01", + "rv32i_m/F/FSUB-S-DYN-RMM-01", + "rv32i_m/F/FSUB-S-DYN-RNE-01", + "rv32i_m/F/FSUB-S-DYN-RTZ-01", + "rv32i_m/F/FSUB-S-DYN-RUP-01", + "rv32i_m/F/FSUB-S-RDN-01", + "rv32i_m/F/FSUB-S-RMM-01", + "rv32i_m/F/FSUB-S-RNE-01", + "rv32i_m/F/FSUB-S-RTZ-01", + "rv32i_m/F/FSUB-S-RUP-01", + "rv32i_m/F/FSW-01" }; string imperas64f[] = '{ `IMPERASTEST, - "rv64i_m/F/FADD-S-DYN-RDN-01.S", - "rv64i_m/F/FADD-S-DYN-RMM-01.S", - "rv64i_m/F/FADD-S-DYN-RNE-01.S", - "rv64i_m/F/FADD-S-DYN-RTZ-01.S", - "rv64i_m/F/FADD-S-DYN-RUP-01.S", - "rv64i_m/F/FADD-S-RDN-01.S", - "rv64i_m/F/FADD-S-RMM-01.S", - "rv64i_m/F/FADD-S-RNE-01.S", - "rv64i_m/F/FADD-S-RTZ-01.S", - "rv64i_m/F/FADD-S-RUP-01.S", - "rv64i_m/F/FCLASS-S-01.S", - "rv64i_m/F/FCVT-L-S-DYN-RDN-01.S", - "rv64i_m/F/FCVT-L-S-DYN-RMM-01.S", - "rv64i_m/F/FCVT-L-S-DYN-RNE-01.S", - "rv64i_m/F/FCVT-L-S-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-L-S-DYN-RUP-01.S", - "rv64i_m/F/FCVT-L-S-RDN-01.S", - "rv64i_m/F/FCVT-L-S-RMM-01.S", - "rv64i_m/F/FCVT-L-S-RNE-01.S", - "rv64i_m/F/FCVT-L-S-RTZ-01.S", - "rv64i_m/F/FCVT-L-S-RUP-01.S", - "rv64i_m/F/FCVT-LU-S-DYN-RDN-01.S", - "rv64i_m/F/FCVT-LU-S-DYN-RMM-01.S", - "rv64i_m/F/FCVT-LU-S-DYN-RNE-01.S", - "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-LU-S-DYN-RUP-01.S", - "rv64i_m/F/FCVT-LU-S-RDN-01.S", - "rv64i_m/F/FCVT-LU-S-RMM-01.S", - "rv64i_m/F/FCVT-LU-S-RNE-01.S", - "rv64i_m/F/FCVT-LU-S-RTZ-01.S", - "rv64i_m/F/FCVT-LU-S-RUP-01.S", - "rv64i_m/F/FCVT-S-L-DYN-RDN-01.S", - "rv64i_m/F/FCVT-S-L-DYN-RMM-01.S", - "rv64i_m/F/FCVT-S-L-DYN-RNE-01.S", - "rv64i_m/F/FCVT-S-L-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-S-L-DYN-RUP-01.S", - "rv64i_m/F/FCVT-S-L-RDN-01.S", - "rv64i_m/F/FCVT-S-L-RMM-01.S", - "rv64i_m/F/FCVT-S-L-RNE-01.S", - "rv64i_m/F/FCVT-S-L-RTZ-01.S", - "rv64i_m/F/FCVT-S-L-RUP-01.S", - "rv64i_m/F/FCVT-S-LU-DYN-RDN-01.S", - "rv64i_m/F/FCVT-S-LU-DYN-RMM-01.S", - "rv64i_m/F/FCVT-S-LU-DYN-RNE-01.S", - "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-S-LU-DYN-RUP-01.S", - "rv64i_m/F/FCVT-S-LU-RDN-01.S", - "rv64i_m/F/FCVT-S-LU-RMM-01.S", - "rv64i_m/F/FCVT-S-LU-RNE-01.S", - "rv64i_m/F/FCVT-S-LU-RTZ-01.S", - "rv64i_m/F/FCVT-S-LU-RUP-01.S", - "rv64i_m/F/FCVT-S-W-DYN-RDN-01.S", - "rv64i_m/F/FCVT-S-W-DYN-RMM-01.S", - "rv64i_m/F/FCVT-S-W-DYN-RNE-01.S", - "rv64i_m/F/FCVT-S-W-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-S-W-DYN-RUP-01.S", - "rv64i_m/F/FCVT-S-W-RDN-01.S", - "rv64i_m/F/FCVT-S-W-RMM-01.S", - "rv64i_m/F/FCVT-S-W-RNE-01.S", - "rv64i_m/F/FCVT-S-W-RTZ-01.S", - "rv64i_m/F/FCVT-S-W-RUP-01.S", - "rv64i_m/F/FCVT-S-WU-DYN-RDN-01.S", - "rv64i_m/F/FCVT-S-WU-DYN-RMM-01.S", - "rv64i_m/F/FCVT-S-WU-DYN-RNE-01.S", - "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-S-WU-DYN-RUP-01.S", - "rv64i_m/F/FCVT-S-WU-RDN-01.S", - "rv64i_m/F/FCVT-S-WU-RMM-01.S", - "rv64i_m/F/FCVT-S-WU-RNE-01.S", - "rv64i_m/F/FCVT-S-WU-RTZ-01.S", - "rv64i_m/F/FCVT-S-WU-RUP-01.S", - "rv64i_m/F/FCVT-W-S-DYN-RDN-01.S", - "rv64i_m/F/FCVT-W-S-DYN-RMM-01.S", - "rv64i_m/F/FCVT-W-S-DYN-RNE-01.S", - "rv64i_m/F/FCVT-W-S-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-W-S-DYN-RUP-01.S", - "rv64i_m/F/FCVT-W-S-RDN-01.S", - "rv64i_m/F/FCVT-W-S-RMM-01.S", - "rv64i_m/F/FCVT-W-S-RNE-01.S", - "rv64i_m/F/FCVT-W-S-RTZ-01.S", - "rv64i_m/F/FCVT-W-S-RUP-01.S", - "rv64i_m/F/FCVT-WU-S-DYN-RDN-01.S", - "rv64i_m/F/FCVT-WU-S-DYN-RMM-01.S", - "rv64i_m/F/FCVT-WU-S-DYN-RNE-01.S", - "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01.S", - "rv64i_m/F/FCVT-WU-S-DYN-RUP-01.S", - "rv64i_m/F/FCVT-WU-S-RDN-01.S", - "rv64i_m/F/FCVT-WU-S-RMM-01.S", - "rv64i_m/F/FCVT-WU-S-RNE-01.S", - "rv64i_m/F/FCVT-WU-S-RTZ-01.S", - "rv64i_m/F/FCVT-WU-S-RUP-01.S", - "rv64i_m/F/FDIV-S-DYN-RDN-01.S", - "rv64i_m/F/FDIV-S-DYN-RMM-01.S", - "rv64i_m/F/FDIV-S-DYN-RNE-01.S", - "rv64i_m/F/FDIV-S-DYN-RTZ-01.S", - "rv64i_m/F/FDIV-S-DYN-RUP-01.S", - "rv64i_m/F/FDIV-S-RDN-01.S", - "rv64i_m/F/FDIV-S-RMM-01.S", - "rv64i_m/F/FDIV-S-RNE-01.S", - "rv64i_m/F/FDIV-S-RTZ-01.S", - "rv64i_m/F/FDIV-S-RUP-01.S", - "rv64i_m/F/FEQ-S-01.S", - "rv64i_m/F/FLE-S-01.S", - "rv64i_m/F/FLT-S-01.S", - "rv64i_m/F/FLW-01.S", - "rv64i_m/F/FMADD-S-DYN-RDN-01.S", - "rv64i_m/F/FMADD-S-DYN-RMM-01.S", - "rv64i_m/F/FMADD-S-DYN-RNE-01.S", - "rv64i_m/F/FMADD-S-DYN-RTZ-01.S", - "rv64i_m/F/FMADD-S-DYN-RUP-01.S", - "rv64i_m/F/FMADD-S-RDN-01.S", - "rv64i_m/F/FMADD-S-RMM-01.S", - "rv64i_m/F/FMADD-S-RNE-01.S", - "rv64i_m/F/FMADD-S-RTZ-01.S", - "rv64i_m/F/FMADD-S-RUP-01.S", - "rv64i_m/F/FMAX-S-01.S", - "rv64i_m/F/FMIN-S-01.S", - "rv64i_m/F/FMSUB-S-DYN-RDN-01.S", - "rv64i_m/F/FMSUB-S-DYN-RMM-01.S", - "rv64i_m/F/FMSUB-S-DYN-RNE-01.S", - "rv64i_m/F/FMSUB-S-DYN-RTZ-01.S", - "rv64i_m/F/FMSUB-S-DYN-RUP-01.S", - "rv64i_m/F/FMSUB-S-RDN-01.S", - "rv64i_m/F/FMSUB-S-RMM-01.S", - "rv64i_m/F/FMSUB-S-RNE-01.S", - "rv64i_m/F/FMSUB-S-RTZ-01.S", - "rv64i_m/F/FMSUB-S-RUP-01.S", - "rv64i_m/F/FMUL-S-DYN-RDN-01.S", - "rv64i_m/F/FMUL-S-DYN-RMM-01.S", - "rv64i_m/F/FMUL-S-DYN-RNE-01.S", - "rv64i_m/F/FMUL-S-DYN-RTZ-01.S", - "rv64i_m/F/FMUL-S-DYN-RUP-01.S", - "rv64i_m/F/FMUL-S-RDN-01.S", - "rv64i_m/F/FMUL-S-RMM-01.S", - "rv64i_m/F/FMUL-S-RNE-01.S", - "rv64i_m/F/FMUL-S-RTZ-01.S", - "rv64i_m/F/FMUL-S-RUP-01.S", - "rv64i_m/F/FMV-W-X-01.S", - "rv64i_m/F/FMV-X-W-01.S", - "rv64i_m/F/FNMADD-S-DYN-RDN-01.S", - "rv64i_m/F/FNMADD-S-DYN-RMM-01.S", - "rv64i_m/F/FNMADD-S-DYN-RNE-01.S", - "rv64i_m/F/FNMADD-S-DYN-RTZ-01.S", - "rv64i_m/F/FNMADD-S-DYN-RUP-01.S", - "rv64i_m/F/FNMADD-S-RDN-01.S", - "rv64i_m/F/FNMADD-S-RMM-01.S", - "rv64i_m/F/FNMADD-S-RNE-01.S", - "rv64i_m/F/FNMADD-S-RTZ-01.S", - "rv64i_m/F/FNMADD-S-RUP-01.S", - "rv64i_m/F/FNMSUB-S-DYN-RDN-01.S", - "rv64i_m/F/FNMSUB-S-DYN-RMM-01.S", - "rv64i_m/F/FNMSUB-S-DYN-RNE-01.S", - "rv64i_m/F/FNMSUB-S-DYN-RTZ-01.S", - "rv64i_m/F/FNMSUB-S-DYN-RUP-01.S", - "rv64i_m/F/FNMSUB-S-RDN-01.S", - "rv64i_m/F/FNMSUB-S-RMM-01.S", - "rv64i_m/F/FNMSUB-S-RNE-01.S", - "rv64i_m/F/FNMSUB-S-RTZ-01.S", - "rv64i_m/F/FNMSUB-S-RUP-01.S", - "rv64i_m/F/FSGNJN-S-01.S", - "rv64i_m/F/FSGNJ-S-01.S", - "rv64i_m/F/FSGNJX-S-01.S", - "rv64i_m/F/FSQRT-S-DYN-RDN-01.S", - "rv64i_m/F/FSQRT-S-DYN-RMM-01.S", - "rv64i_m/F/FSQRT-S-DYN-RNE-01.S", - "rv64i_m/F/FSQRT-S-DYN-RTZ-01.S", - "rv64i_m/F/FSQRT-S-DYN-RUP-01.S", - "rv64i_m/F/FSQRT-S-RDN-01.S", - "rv64i_m/F/FSQRT-S-RMM-01.S", - "rv64i_m/F/FSQRT-S-RNE-01.S", - "rv64i_m/F/FSQRT-S-RTZ-01.S", - "rv64i_m/F/FSQRT-S-RUP-01.S", - "rv64i_m/F/FSUB-S-DYN-RDN-01.S", - "rv64i_m/F/FSUB-S-DYN-RMM-01.S", - "rv64i_m/F/FSUB-S-DYN-RNE-01.S", - "rv64i_m/F/FSUB-S-DYN-RTZ-01.S", - "rv64i_m/F/FSUB-S-DYN-RUP-01.S", - "rv64i_m/F/FSUB-S-RDN-01.S", - "rv64i_m/F/FSUB-S-RMM-01.S", - "rv64i_m/F/FSUB-S-RNE-01.S", - "rv64i_m/F/FSUB-S-RTZ-01.S", - "rv64i_m/F/FSUB-S-RUP-01.S", - "rv64i_m/F/FSW-01.S" + "rv64i_m/F/FADD-S-DYN-RDN-01", + "rv64i_m/F/FADD-S-DYN-RMM-01", + "rv64i_m/F/FADD-S-DYN-RNE-01", + "rv64i_m/F/FADD-S-DYN-RTZ-01", + "rv64i_m/F/FADD-S-DYN-RUP-01", + "rv64i_m/F/FADD-S-RDN-01", + "rv64i_m/F/FADD-S-RMM-01", + "rv64i_m/F/FADD-S-RNE-01", + "rv64i_m/F/FADD-S-RTZ-01", + "rv64i_m/F/FADD-S-RUP-01", + "rv64i_m/F/FCLASS-S-01", + "rv64i_m/F/FCVT-L-S-DYN-RDN-01", + "rv64i_m/F/FCVT-L-S-DYN-RMM-01", + "rv64i_m/F/FCVT-L-S-DYN-RNE-01", + "rv64i_m/F/FCVT-L-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-L-S-DYN-RUP-01", + "rv64i_m/F/FCVT-L-S-RDN-01", + "rv64i_m/F/FCVT-L-S-RMM-01", + "rv64i_m/F/FCVT-L-S-RNE-01", + "rv64i_m/F/FCVT-L-S-RTZ-01", + "rv64i_m/F/FCVT-L-S-RUP-01", + "rv64i_m/F/FCVT-LU-S-DYN-RDN-01", + "rv64i_m/F/FCVT-LU-S-DYN-RMM-01", + "rv64i_m/F/FCVT-LU-S-DYN-RNE-01", + "rv64i_m/F/FCVT-LU-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-LU-S-DYN-RUP-01", + "rv64i_m/F/FCVT-LU-S-RDN-01", + "rv64i_m/F/FCVT-LU-S-RMM-01", + "rv64i_m/F/FCVT-LU-S-RNE-01", + "rv64i_m/F/FCVT-LU-S-RTZ-01", + "rv64i_m/F/FCVT-LU-S-RUP-01", + "rv64i_m/F/FCVT-S-L-DYN-RDN-01", + "rv64i_m/F/FCVT-S-L-DYN-RMM-01", + "rv64i_m/F/FCVT-S-L-DYN-RNE-01", + "rv64i_m/F/FCVT-S-L-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-L-DYN-RUP-01", + "rv64i_m/F/FCVT-S-L-RDN-01", + "rv64i_m/F/FCVT-S-L-RMM-01", + "rv64i_m/F/FCVT-S-L-RNE-01", + "rv64i_m/F/FCVT-S-L-RTZ-01", + "rv64i_m/F/FCVT-S-L-RUP-01", + "rv64i_m/F/FCVT-S-LU-DYN-RDN-01", + "rv64i_m/F/FCVT-S-LU-DYN-RMM-01", + "rv64i_m/F/FCVT-S-LU-DYN-RNE-01", + "rv64i_m/F/FCVT-S-LU-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-LU-DYN-RUP-01", + "rv64i_m/F/FCVT-S-LU-RDN-01", + "rv64i_m/F/FCVT-S-LU-RMM-01", + "rv64i_m/F/FCVT-S-LU-RNE-01", + "rv64i_m/F/FCVT-S-LU-RTZ-01", + "rv64i_m/F/FCVT-S-LU-RUP-01", + "rv64i_m/F/FCVT-S-W-DYN-RDN-01", + "rv64i_m/F/FCVT-S-W-DYN-RMM-01", + "rv64i_m/F/FCVT-S-W-DYN-RNE-01", + "rv64i_m/F/FCVT-S-W-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-W-DYN-RUP-01", + "rv64i_m/F/FCVT-S-W-RDN-01", + "rv64i_m/F/FCVT-S-W-RMM-01", + "rv64i_m/F/FCVT-S-W-RNE-01", + "rv64i_m/F/FCVT-S-W-RTZ-01", + "rv64i_m/F/FCVT-S-W-RUP-01", + "rv64i_m/F/FCVT-S-WU-DYN-RDN-01", + "rv64i_m/F/FCVT-S-WU-DYN-RMM-01", + "rv64i_m/F/FCVT-S-WU-DYN-RNE-01", + "rv64i_m/F/FCVT-S-WU-DYN-RTZ-01", + "rv64i_m/F/FCVT-S-WU-DYN-RUP-01", + "rv64i_m/F/FCVT-S-WU-RDN-01", + "rv64i_m/F/FCVT-S-WU-RMM-01", + "rv64i_m/F/FCVT-S-WU-RNE-01", + "rv64i_m/F/FCVT-S-WU-RTZ-01", + "rv64i_m/F/FCVT-S-WU-RUP-01", + "rv64i_m/F/FCVT-W-S-DYN-RDN-01", + "rv64i_m/F/FCVT-W-S-DYN-RMM-01", + "rv64i_m/F/FCVT-W-S-DYN-RNE-01", + "rv64i_m/F/FCVT-W-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-W-S-DYN-RUP-01", + "rv64i_m/F/FCVT-W-S-RDN-01", + "rv64i_m/F/FCVT-W-S-RMM-01", + "rv64i_m/F/FCVT-W-S-RNE-01", + "rv64i_m/F/FCVT-W-S-RTZ-01", + "rv64i_m/F/FCVT-W-S-RUP-01", + "rv64i_m/F/FCVT-WU-S-DYN-RDN-01", + "rv64i_m/F/FCVT-WU-S-DYN-RMM-01", + "rv64i_m/F/FCVT-WU-S-DYN-RNE-01", + "rv64i_m/F/FCVT-WU-S-DYN-RTZ-01", + "rv64i_m/F/FCVT-WU-S-DYN-RUP-01", + "rv64i_m/F/FCVT-WU-S-RDN-01", + "rv64i_m/F/FCVT-WU-S-RMM-01", + "rv64i_m/F/FCVT-WU-S-RNE-01", + "rv64i_m/F/FCVT-WU-S-RTZ-01", + "rv64i_m/F/FCVT-WU-S-RUP-01", + "rv64i_m/F/FDIV-S-DYN-RDN-01", + "rv64i_m/F/FDIV-S-DYN-RMM-01", + "rv64i_m/F/FDIV-S-DYN-RNE-01", + "rv64i_m/F/FDIV-S-DYN-RTZ-01", + "rv64i_m/F/FDIV-S-DYN-RUP-01", + "rv64i_m/F/FDIV-S-RDN-01", + "rv64i_m/F/FDIV-S-RMM-01", + "rv64i_m/F/FDIV-S-RNE-01", + "rv64i_m/F/FDIV-S-RTZ-01", + "rv64i_m/F/FDIV-S-RUP-01", + "rv64i_m/F/FEQ-S-01", + "rv64i_m/F/FLE-S-01", + "rv64i_m/F/FLT-S-01", + "rv64i_m/F/FLW-01", + "rv64i_m/F/FMADD-S-DYN-RDN-01", + "rv64i_m/F/FMADD-S-DYN-RMM-01", + "rv64i_m/F/FMADD-S-DYN-RNE-01", + "rv64i_m/F/FMADD-S-DYN-RTZ-01", + "rv64i_m/F/FMADD-S-DYN-RUP-01", + "rv64i_m/F/FMADD-S-RDN-01", + "rv64i_m/F/FMADD-S-RMM-01", + "rv64i_m/F/FMADD-S-RNE-01", + "rv64i_m/F/FMADD-S-RTZ-01", + "rv64i_m/F/FMADD-S-RUP-01", + "rv64i_m/F/FMAX-S-01", + "rv64i_m/F/FMIN-S-01", + "rv64i_m/F/FMSUB-S-DYN-RDN-01", + "rv64i_m/F/FMSUB-S-DYN-RMM-01", + "rv64i_m/F/FMSUB-S-DYN-RNE-01", + "rv64i_m/F/FMSUB-S-DYN-RTZ-01", + "rv64i_m/F/FMSUB-S-DYN-RUP-01", + "rv64i_m/F/FMSUB-S-RDN-01", + "rv64i_m/F/FMSUB-S-RMM-01", + "rv64i_m/F/FMSUB-S-RNE-01", + "rv64i_m/F/FMSUB-S-RTZ-01", + "rv64i_m/F/FMSUB-S-RUP-01", + "rv64i_m/F/FMUL-S-DYN-RDN-01", + "rv64i_m/F/FMUL-S-DYN-RMM-01", + "rv64i_m/F/FMUL-S-DYN-RNE-01", + "rv64i_m/F/FMUL-S-DYN-RTZ-01", + "rv64i_m/F/FMUL-S-DYN-RUP-01", + "rv64i_m/F/FMUL-S-RDN-01", + "rv64i_m/F/FMUL-S-RMM-01", + "rv64i_m/F/FMUL-S-RNE-01", + "rv64i_m/F/FMUL-S-RTZ-01", + "rv64i_m/F/FMUL-S-RUP-01", + "rv64i_m/F/FMV-W-X-01", + "rv64i_m/F/FMV-X-W-01", + "rv64i_m/F/FNMADD-S-DYN-RDN-01", + "rv64i_m/F/FNMADD-S-DYN-RMM-01", + "rv64i_m/F/FNMADD-S-DYN-RNE-01", + "rv64i_m/F/FNMADD-S-DYN-RTZ-01", + "rv64i_m/F/FNMADD-S-DYN-RUP-01", + "rv64i_m/F/FNMADD-S-RDN-01", + "rv64i_m/F/FNMADD-S-RMM-01", + "rv64i_m/F/FNMADD-S-RNE-01", + "rv64i_m/F/FNMADD-S-RTZ-01", + "rv64i_m/F/FNMADD-S-RUP-01", + "rv64i_m/F/FNMSUB-S-DYN-RDN-01", + "rv64i_m/F/FNMSUB-S-DYN-RMM-01", + "rv64i_m/F/FNMSUB-S-DYN-RNE-01", + "rv64i_m/F/FNMSUB-S-DYN-RTZ-01", + "rv64i_m/F/FNMSUB-S-DYN-RUP-01", + "rv64i_m/F/FNMSUB-S-RDN-01", + "rv64i_m/F/FNMSUB-S-RMM-01", + "rv64i_m/F/FNMSUB-S-RNE-01", + "rv64i_m/F/FNMSUB-S-RTZ-01", + "rv64i_m/F/FNMSUB-S-RUP-01", + "rv64i_m/F/FSGNJN-S-01", + "rv64i_m/F/FSGNJ-S-01", + "rv64i_m/F/FSGNJX-S-01", + "rv64i_m/F/FSQRT-S-DYN-RDN-01", + "rv64i_m/F/FSQRT-S-DYN-RMM-01", + "rv64i_m/F/FSQRT-S-DYN-RNE-01", + "rv64i_m/F/FSQRT-S-DYN-RTZ-01", + "rv64i_m/F/FSQRT-S-DYN-RUP-01", + "rv64i_m/F/FSQRT-S-RDN-01", + "rv64i_m/F/FSQRT-S-RMM-01", + "rv64i_m/F/FSQRT-S-RNE-01", + "rv64i_m/F/FSQRT-S-RTZ-01", + "rv64i_m/F/FSQRT-S-RUP-01", + "rv64i_m/F/FSUB-S-DYN-RDN-01", + "rv64i_m/F/FSUB-S-DYN-RMM-01", + "rv64i_m/F/FSUB-S-DYN-RNE-01", + "rv64i_m/F/FSUB-S-DYN-RTZ-01", + "rv64i_m/F/FSUB-S-DYN-RUP-01", + "rv64i_m/F/FSUB-S-RDN-01", + "rv64i_m/F/FSUB-S-RMM-01", + "rv64i_m/F/FSUB-S-RNE-01", + "rv64i_m/F/FSUB-S-RTZ-01", + "rv64i_m/F/FSUB-S-RUP-01", + "rv64i_m/F/FSW-01" }; string imperas64d[] = '{ `IMPERASTEST, - "rv64i_m/D/FADD-D-DYN-RDN-01.S", - "rv64i_m/D/FADD-D-DYN-RMM-01.S", - "rv64i_m/D/FADD-D-DYN-RNE-01.S", - "rv64i_m/D/FADD-D-DYN-RTZ-01.S", - "rv64i_m/D/FADD-D-DYN-RUP-01.S", - "rv64i_m/D/FADD-D-RDN-01.S", - "rv64i_m/D/FADD-D-RMM-01.S", - "rv64i_m/D/FADD-D-RNE-01.S", - "rv64i_m/D/FADD-D-RTZ-01.S", - "rv64i_m/D/FADD-D-RUP-01.S", - "rv64i_m/D/FCLASS-D-01.S", - "rv64i_m/D/FCVT-D-L-DYN-RDN-01.S", - "rv64i_m/D/FCVT-D-L-DYN-RMM-01.S", - "rv64i_m/D/FCVT-D-L-DYN-RNE-01.S", - "rv64i_m/D/FCVT-D-L-DYN-RTZ-01.S", - "rv64i_m/D/FCVT-D-L-DYN-RUP-01.S", - "rv64i_m/D/FCVT-D-L-RDN-01.S", - "rv64i_m/D/FCVT-D-L-RMM-01.S", - "rv64i_m/D/FCVT-D-L-RNE-01.S", - "rv64i_m/D/FCVT-D-L-RTZ-01.S", - "rv64i_m/D/FCVT-D-L-RUP-01.S", - "rv64i_m/D/FCVT-D-LU-DYN-RDN-01.S", - "rv64i_m/D/FCVT-D-LU-DYN-RMM-01.S", - "rv64i_m/D/FCVT-D-LU-DYN-RNE-01.S", - "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01.S", - "rv64i_m/D/FCVT-D-LU-DYN-RUP-01.S", - "rv64i_m/D/FCVT-D-LU-RDN-01.S", - "rv64i_m/D/FCVT-D-LU-RMM-01.S", - "rv64i_m/D/FCVT-D-LU-RNE-01.S", - "rv64i_m/D/FCVT-D-LU-RTZ-01.S", - "rv64i_m/D/FCVT-D-LU-RUP-01.S", - "rv64i_m/D/FCVT-D-S-01.S", - "rv64i_m/D/FCVT-D-W-01.S", - "rv64i_m/D/FCVT-D-WU-01.S", - "rv64i_m/D/FCVT-L-D-DYN-RDN-01.S", - "rv64i_m/D/FCVT-L-D-DYN-RMM-01.S", - "rv64i_m/D/FCVT-L-D-DYN-RNE-01.S", - "rv64i_m/D/FCVT-L-D-DYN-RTZ-01.S", - "rv64i_m/D/FCVT-L-D-DYN-RUP-01.S", - "rv64i_m/D/FCVT-L-D-RDN-01.S", - "rv64i_m/D/FCVT-L-D-RMM-01.S", - "rv64i_m/D/FCVT-L-D-RNE-01.S", - "rv64i_m/D/FCVT-L-D-RTZ-01.S", - "rv64i_m/D/FCVT-L-D-RUP-01.S", - "rv64i_m/D/FCVT-LU-D-DYN-RDN-01.S", - "rv64i_m/D/FCVT-LU-D-DYN-RMM-01.S", - "rv64i_m/D/FCVT-LU-D-DYN-RNE-01.S", - "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01.S", - "rv64i_m/D/FCVT-LU-D-DYN-RUP-01.S", - "rv64i_m/D/FCVT-LU-D-RDN-01.S", - "rv64i_m/D/FCVT-LU-D-RMM-01.S", - "rv64i_m/D/FCVT-LU-D-RNE-01.S", - "rv64i_m/D/FCVT-LU-D-RTZ-01.S", - "rv64i_m/D/FCVT-LU-D-RUP-01.S", - "rv64i_m/D/FCVT-S-D-DYN-RDN-01.S", - "rv64i_m/D/FCVT-S-D-DYN-RMM-01.S", - "rv64i_m/D/FCVT-S-D-DYN-RNE-01.S", - "rv64i_m/D/FCVT-S-D-DYN-RTZ-01.S", - "rv64i_m/D/FCVT-S-D-DYN-RUP-01.S", - "rv64i_m/D/FCVT-S-D-RDN-01.S", - "rv64i_m/D/FCVT-S-D-RMM-01.S", - "rv64i_m/D/FCVT-S-D-RNE-01.S", - "rv64i_m/D/FCVT-S-D-RTZ-01.S", - "rv64i_m/D/FCVT-S-D-RUP-01.S", - "rv64i_m/D/FCVT-W-D-DYN-RDN-01.S", - "rv64i_m/D/FCVT-W-D-DYN-RMM-01.S", - "rv64i_m/D/FCVT-W-D-DYN-RNE-01.S", - "rv64i_m/D/FCVT-W-D-DYN-RTZ-01.S", - "rv64i_m/D/FCVT-W-D-DYN-RUP-01.S", - "rv64i_m/D/FCVT-W-D-RDN-01.S", - "rv64i_m/D/FCVT-W-D-RMM-01.S", - "rv64i_m/D/FCVT-W-D-RNE-01.S", - "rv64i_m/D/FCVT-W-D-RTZ-01.S", - "rv64i_m/D/FCVT-W-D-RUP-01.S", - "rv64i_m/D/FCVT-WU-D-DYN-RDN-01.S", - "rv64i_m/D/FCVT-WU-D-DYN-RMM-01.S", - "rv64i_m/D/FCVT-WU-D-DYN-RNE-01.S", - "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01.S", - "rv64i_m/D/FCVT-WU-D-DYN-RUP-01.S", - "rv64i_m/D/FCVT-WU-D-RDN-01.S", - "rv64i_m/D/FCVT-WU-D-RMM-01.S", - "rv64i_m/D/FCVT-WU-D-RNE-01.S", - "rv64i_m/D/FCVT-WU-D-RTZ-01.S", - "rv64i_m/D/FCVT-WU-D-RUP-01.S", - "rv64i_m/D/FDIV-D-DYN-RDN-01.S", - "rv64i_m/D/FDIV-D-DYN-RMM-01.S", - "rv64i_m/D/FDIV-D-DYN-RNE-01.S", - "rv64i_m/D/FDIV-D-DYN-RTZ-01.S", - "rv64i_m/D/FDIV-D-DYN-RUP-01.S", - "rv64i_m/D/FDIV-D-RDN-01.S", - "rv64i_m/D/FDIV-D-RMM-01.S", - "rv64i_m/D/FDIV-D-RNE-01.S", - "rv64i_m/D/FDIV-D-RTZ-01.S", - "rv64i_m/D/FDIV-D-RUP-01.S", - "rv64i_m/D/FEQ-D-01.S", - "rv64i_m/D/FLD-01.S", - "rv64i_m/D/FLE-D-01.S", - "rv64i_m/D/FLT-D-01.S", - "rv64i_m/D/FMADD-D-DYN-RDN-01.S", - "rv64i_m/D/FMADD-D-DYN-RMM-01.S", - "rv64i_m/D/FMADD-D-DYN-RNE-01.S", - "rv64i_m/D/FMADD-D-DYN-RTZ-01.S", - "rv64i_m/D/FMADD-D-DYN-RUP-01.S", - "rv64i_m/D/FMADD-D-RDN-01.S", - "rv64i_m/D/FMADD-D-RMM-01.S", - "rv64i_m/D/FMADD-D-RNE-01.S", - "rv64i_m/D/FMADD-D-RTZ-01.S", - "rv64i_m/D/FMADD-D-RUP-01.S", - "rv64i_m/D/FMAX-D-01.S", - "rv64i_m/D/FMIN-D-01.S", - "rv64i_m/D/FMSUB-D-DYN-RDN-01.S", - "rv64i_m/D/FMSUB-D-DYN-RMM-01.S", - "rv64i_m/D/FMSUB-D-DYN-RNE-01.S", - "rv64i_m/D/FMSUB-D-DYN-RTZ-01.S", - "rv64i_m/D/FMSUB-D-DYN-RUP-01.S", - "rv64i_m/D/FMSUB-D-RDN-01.S", - "rv64i_m/D/FMSUB-D-RMM-01.S", - "rv64i_m/D/FMSUB-D-RNE-01.S", - "rv64i_m/D/FMSUB-D-RTZ-01.S", - "rv64i_m/D/FMSUB-D-RUP-01.S", - "rv64i_m/D/FMUL-D-DYN-RDN-01.S", - "rv64i_m/D/FMUL-D-DYN-RMM-01.S", - "rv64i_m/D/FMUL-D-DYN-RNE-01.S", - "rv64i_m/D/FMUL-D-DYN-RTZ-01.S", - "rv64i_m/D/FMUL-D-DYN-RUP-01.S", - "rv64i_m/D/FMUL-D-RDN-01.S", - "rv64i_m/D/FMUL-D-RMM-01.S", - "rv64i_m/D/FMUL-D-RNE-01.S", - "rv64i_m/D/FMUL-D-RTZ-01.S", - "rv64i_m/D/FMUL-D-RUP-01.S", - "rv64i_m/D/FMV-D-X-01.S", - "rv64i_m/D/FMV-X-D-01.S", - "rv64i_m/D/FNMADD-D-DYN-RDN-01.S", - "rv64i_m/D/FNMADD-D-DYN-RMM-01.S", - "rv64i_m/D/FNMADD-D-DYN-RNE-01.S", - "rv64i_m/D/FNMADD-D-DYN-RTZ-01.S", - "rv64i_m/D/FNMADD-D-DYN-RUP-01.S", - "rv64i_m/D/FNMADD-D-RDN-01.S", - "rv64i_m/D/FNMADD-D-RMM-01.S", - "rv64i_m/D/FNMADD-D-RNE-01.S", - "rv64i_m/D/FNMADD-D-RTZ-01.S", - "rv64i_m/D/FNMADD-D-RUP-01.S", - "rv64i_m/D/FNMSUB-D-DYN-RDN-01.S", - "rv64i_m/D/FNMSUB-D-DYN-RMM-01.S", - "rv64i_m/D/FNMSUB-D-DYN-RNE-01.S", - "rv64i_m/D/FNMSUB-D-DYN-RTZ-01.S", - "rv64i_m/D/FNMSUB-D-DYN-RUP-01.S", - "rv64i_m/D/FNMSUB-D-RDN-01.S", - "rv64i_m/D/FNMSUB-D-RMM-01.S", - "rv64i_m/D/FNMSUB-D-RNE-01.S", - "rv64i_m/D/FNMSUB-D-RTZ-01.S", - "rv64i_m/D/FNMSUB-D-RUP-01.S", - "rv64i_m/D/FSD-01.S", - "rv64i_m/D/FSGNJ-D-01.S", - "rv64i_m/D/FSGNJN-D-01.S", - "rv64i_m/D/FSGNJX-D-01.S", - "rv64i_m/D/FSQRT-D-DYN-RDN-01.S", - "rv64i_m/D/FSQRT-D-DYN-RMM-01.S", - "rv64i_m/D/FSQRT-D-DYN-RNE-01.S", - "rv64i_m/D/FSQRT-D-DYN-RTZ-01.S", - "rv64i_m/D/FSQRT-D-DYN-RUP-01.S", - "rv64i_m/D/FSQRT-D-RDN-01.S", - "rv64i_m/D/FSQRT-D-RMM-01.S", - "rv64i_m/D/FSQRT-D-RNE-01.S", - "rv64i_m/D/FSQRT-D-RTZ-01.S", - "rv64i_m/D/FSQRT-D-RUP-01.S", - "rv64i_m/D/FSUB-D-DYN-RDN-01.S", - "rv64i_m/D/FSUB-D-DYN-RMM-01.S", - "rv64i_m/D/FSUB-D-DYN-RNE-01.S", - "rv64i_m/D/FSUB-D-DYN-RTZ-01.S", - "rv64i_m/D/FSUB-D-DYN-RUP-01.S", - "rv64i_m/D/FSUB-D-RDN-01.S", - "rv64i_m/D/FSUB-D-RMM-01.S", - "rv64i_m/D/FSUB-D-RNE-01.S", - "rv64i_m/D/FSUB-D-RTZ-01.S", - "rv64i_m/D/FSUB-D-RUP-01.S" + "rv64i_m/D/FADD-D-DYN-RDN-01", + "rv64i_m/D/FADD-D-DYN-RMM-01", + "rv64i_m/D/FADD-D-DYN-RNE-01", + "rv64i_m/D/FADD-D-DYN-RTZ-01", + "rv64i_m/D/FADD-D-DYN-RUP-01", + "rv64i_m/D/FADD-D-RDN-01", + "rv64i_m/D/FADD-D-RMM-01", + "rv64i_m/D/FADD-D-RNE-01", + "rv64i_m/D/FADD-D-RTZ-01", + "rv64i_m/D/FADD-D-RUP-01", + "rv64i_m/D/FCLASS-D-01", + "rv64i_m/D/FCVT-D-L-DYN-RDN-01", + "rv64i_m/D/FCVT-D-L-DYN-RMM-01", + "rv64i_m/D/FCVT-D-L-DYN-RNE-01", + "rv64i_m/D/FCVT-D-L-DYN-RTZ-01", + "rv64i_m/D/FCVT-D-L-DYN-RUP-01", + "rv64i_m/D/FCVT-D-L-RDN-01", + "rv64i_m/D/FCVT-D-L-RMM-01", + "rv64i_m/D/FCVT-D-L-RNE-01", + "rv64i_m/D/FCVT-D-L-RTZ-01", + "rv64i_m/D/FCVT-D-L-RUP-01", + "rv64i_m/D/FCVT-D-LU-DYN-RDN-01", + "rv64i_m/D/FCVT-D-LU-DYN-RMM-01", + "rv64i_m/D/FCVT-D-LU-DYN-RNE-01", + "rv64i_m/D/FCVT-D-LU-DYN-RTZ-01", + "rv64i_m/D/FCVT-D-LU-DYN-RUP-01", + "rv64i_m/D/FCVT-D-LU-RDN-01", + "rv64i_m/D/FCVT-D-LU-RMM-01", + "rv64i_m/D/FCVT-D-LU-RNE-01", + "rv64i_m/D/FCVT-D-LU-RTZ-01", + "rv64i_m/D/FCVT-D-LU-RUP-01", + "rv64i_m/D/FCVT-D-S-01", + "rv64i_m/D/FCVT-D-W-01", + "rv64i_m/D/FCVT-D-WU-01", + "rv64i_m/D/FCVT-L-D-DYN-RDN-01", + "rv64i_m/D/FCVT-L-D-DYN-RMM-01", + "rv64i_m/D/FCVT-L-D-DYN-RNE-01", + "rv64i_m/D/FCVT-L-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-L-D-DYN-RUP-01", + "rv64i_m/D/FCVT-L-D-RDN-01", + "rv64i_m/D/FCVT-L-D-RMM-01", + "rv64i_m/D/FCVT-L-D-RNE-01", + "rv64i_m/D/FCVT-L-D-RTZ-01", + "rv64i_m/D/FCVT-L-D-RUP-01", + "rv64i_m/D/FCVT-LU-D-DYN-RDN-01", + "rv64i_m/D/FCVT-LU-D-DYN-RMM-01", + "rv64i_m/D/FCVT-LU-D-DYN-RNE-01", + "rv64i_m/D/FCVT-LU-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-LU-D-DYN-RUP-01", + "rv64i_m/D/FCVT-LU-D-RDN-01", + "rv64i_m/D/FCVT-LU-D-RMM-01", + "rv64i_m/D/FCVT-LU-D-RNE-01", + "rv64i_m/D/FCVT-LU-D-RTZ-01", + "rv64i_m/D/FCVT-LU-D-RUP-01", + "rv64i_m/D/FCVT-S-D-DYN-RDN-01", + "rv64i_m/D/FCVT-S-D-DYN-RMM-01", + "rv64i_m/D/FCVT-S-D-DYN-RNE-01", + "rv64i_m/D/FCVT-S-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-S-D-DYN-RUP-01", + "rv64i_m/D/FCVT-S-D-RDN-01", + "rv64i_m/D/FCVT-S-D-RMM-01", + "rv64i_m/D/FCVT-S-D-RNE-01", + "rv64i_m/D/FCVT-S-D-RTZ-01", + "rv64i_m/D/FCVT-S-D-RUP-01", + "rv64i_m/D/FCVT-W-D-DYN-RDN-01", + "rv64i_m/D/FCVT-W-D-DYN-RMM-01", + "rv64i_m/D/FCVT-W-D-DYN-RNE-01", + "rv64i_m/D/FCVT-W-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-W-D-DYN-RUP-01", + "rv64i_m/D/FCVT-W-D-RDN-01", + "rv64i_m/D/FCVT-W-D-RMM-01", + "rv64i_m/D/FCVT-W-D-RNE-01", + "rv64i_m/D/FCVT-W-D-RTZ-01", + "rv64i_m/D/FCVT-W-D-RUP-01", + "rv64i_m/D/FCVT-WU-D-DYN-RDN-01", + "rv64i_m/D/FCVT-WU-D-DYN-RMM-01", + "rv64i_m/D/FCVT-WU-D-DYN-RNE-01", + "rv64i_m/D/FCVT-WU-D-DYN-RTZ-01", + "rv64i_m/D/FCVT-WU-D-DYN-RUP-01", + "rv64i_m/D/FCVT-WU-D-RDN-01", + "rv64i_m/D/FCVT-WU-D-RMM-01", + "rv64i_m/D/FCVT-WU-D-RNE-01", + "rv64i_m/D/FCVT-WU-D-RTZ-01", + "rv64i_m/D/FCVT-WU-D-RUP-01", + "rv64i_m/D/FDIV-D-DYN-RDN-01", + "rv64i_m/D/FDIV-D-DYN-RMM-01", + "rv64i_m/D/FDIV-D-DYN-RNE-01", + "rv64i_m/D/FDIV-D-DYN-RTZ-01", + "rv64i_m/D/FDIV-D-DYN-RUP-01", + "rv64i_m/D/FDIV-D-RDN-01", + "rv64i_m/D/FDIV-D-RMM-01", + "rv64i_m/D/FDIV-D-RNE-01", + "rv64i_m/D/FDIV-D-RTZ-01", + "rv64i_m/D/FDIV-D-RUP-01", + "rv64i_m/D/FEQ-D-01", + "rv64i_m/D/FLD-01", + "rv64i_m/D/FLE-D-01", + "rv64i_m/D/FLT-D-01", + "rv64i_m/D/FMADD-D-DYN-RDN-01", + "rv64i_m/D/FMADD-D-DYN-RMM-01", + "rv64i_m/D/FMADD-D-DYN-RNE-01", + "rv64i_m/D/FMADD-D-DYN-RTZ-01", + "rv64i_m/D/FMADD-D-DYN-RUP-01", + "rv64i_m/D/FMADD-D-RDN-01", + "rv64i_m/D/FMADD-D-RMM-01", + "rv64i_m/D/FMADD-D-RNE-01", + "rv64i_m/D/FMADD-D-RTZ-01", + "rv64i_m/D/FMADD-D-RUP-01", + "rv64i_m/D/FMAX-D-01", + "rv64i_m/D/FMIN-D-01", + "rv64i_m/D/FMSUB-D-DYN-RDN-01", + "rv64i_m/D/FMSUB-D-DYN-RMM-01", + "rv64i_m/D/FMSUB-D-DYN-RNE-01", + "rv64i_m/D/FMSUB-D-DYN-RTZ-01", + "rv64i_m/D/FMSUB-D-DYN-RUP-01", + "rv64i_m/D/FMSUB-D-RDN-01", + "rv64i_m/D/FMSUB-D-RMM-01", + "rv64i_m/D/FMSUB-D-RNE-01", + "rv64i_m/D/FMSUB-D-RTZ-01", + "rv64i_m/D/FMSUB-D-RUP-01", + "rv64i_m/D/FMUL-D-DYN-RDN-01", + "rv64i_m/D/FMUL-D-DYN-RMM-01", + "rv64i_m/D/FMUL-D-DYN-RNE-01", + "rv64i_m/D/FMUL-D-DYN-RTZ-01", + "rv64i_m/D/FMUL-D-DYN-RUP-01", + "rv64i_m/D/FMUL-D-RDN-01", + "rv64i_m/D/FMUL-D-RMM-01", + "rv64i_m/D/FMUL-D-RNE-01", + "rv64i_m/D/FMUL-D-RTZ-01", + "rv64i_m/D/FMUL-D-RUP-01", + "rv64i_m/D/FMV-D-X-01", + "rv64i_m/D/FMV-X-D-01", + "rv64i_m/D/FNMADD-D-DYN-RDN-01", + "rv64i_m/D/FNMADD-D-DYN-RMM-01", + "rv64i_m/D/FNMADD-D-DYN-RNE-01", + "rv64i_m/D/FNMADD-D-DYN-RTZ-01", + "rv64i_m/D/FNMADD-D-DYN-RUP-01", + "rv64i_m/D/FNMADD-D-RDN-01", + "rv64i_m/D/FNMADD-D-RMM-01", + "rv64i_m/D/FNMADD-D-RNE-01", + "rv64i_m/D/FNMADD-D-RTZ-01", + "rv64i_m/D/FNMADD-D-RUP-01", + "rv64i_m/D/FNMSUB-D-DYN-RDN-01", + "rv64i_m/D/FNMSUB-D-DYN-RMM-01", + "rv64i_m/D/FNMSUB-D-DYN-RNE-01", + "rv64i_m/D/FNMSUB-D-DYN-RTZ-01", + "rv64i_m/D/FNMSUB-D-DYN-RUP-01", + "rv64i_m/D/FNMSUB-D-RDN-01", + "rv64i_m/D/FNMSUB-D-RMM-01", + "rv64i_m/D/FNMSUB-D-RNE-01", + "rv64i_m/D/FNMSUB-D-RTZ-01", + "rv64i_m/D/FNMSUB-D-RUP-01", + "rv64i_m/D/FSD-01", + "rv64i_m/D/FSGNJ-D-01", + "rv64i_m/D/FSGNJN-D-01", + "rv64i_m/D/FSGNJX-D-01", + "rv64i_m/D/FSQRT-D-DYN-RDN-01", + "rv64i_m/D/FSQRT-D-DYN-RMM-01", + "rv64i_m/D/FSQRT-D-DYN-RNE-01", + "rv64i_m/D/FSQRT-D-DYN-RTZ-01", + "rv64i_m/D/FSQRT-D-DYN-RUP-01", + "rv64i_m/D/FSQRT-D-RDN-01", + "rv64i_m/D/FSQRT-D-RMM-01", + "rv64i_m/D/FSQRT-D-RNE-01", + "rv64i_m/D/FSQRT-D-RTZ-01", + "rv64i_m/D/FSQRT-D-RUP-01", + "rv64i_m/D/FSUB-D-DYN-RDN-01", + "rv64i_m/D/FSUB-D-DYN-RMM-01", + "rv64i_m/D/FSUB-D-DYN-RNE-01", + "rv64i_m/D/FSUB-D-DYN-RTZ-01", + "rv64i_m/D/FSUB-D-DYN-RUP-01", + "rv64i_m/D/FSUB-D-RDN-01", + "rv64i_m/D/FSUB-D-RMM-01", + "rv64i_m/D/FSUB-D-RNE-01", + "rv64i_m/D/FSUB-D-RTZ-01", + "rv64i_m/D/FSUB-D-RUP-01" }; string imperas64m[] = '{ `IMPERASTEST, - "rv64i_m/M/DIV-01.S", - "rv64i_m/M/DIVU-01.S", - "rv64i_m/M/DIVUW-01.S", - "rv64i_m/M/DIVW-01.S", - "rv64i_m/M/MUL-01.S", - "rv64i_m/M/MULH-01.S", - "rv64i_m/M/MULHSU-01.S", - "rv64i_m/M/MULHU-01.S", - "rv64i_m/M/MULW-01.S", - "rv64i_m/M/REM-01.S", - "rv64i_m/M/REMU-01.S", - "rv64i_m/M/REMUW-01.S", - "rv64i_m/M/REMW-01.S" + "rv64i_m/M/DIV-01", + "rv64i_m/M/DIVU-01", + "rv64i_m/M/DIVUW-01", + "rv64i_m/M/DIVW-01", + "rv64i_m/M/MUL-01", + "rv64i_m/M/MULH-01", + "rv64i_m/M/MULHSU-01", + "rv64i_m/M/MULHU-01", + "rv64i_m/M/MULW-01", + "rv64i_m/M/REM-01", + "rv64i_m/M/REMU-01", + "rv64i_m/M/REMUW-01", + "rv64i_m/M/REMW-01" }; string imperas64c[] = '{ `IMPERASTEST, - "rv64i_m/C/C-ADD-01.S", - "rv64i_m/C/C-ADDI-01.S", - "rv64i_m/C/C-ADDI16SP-01.S", - "rv64i_m/C/C-ADDI4SPN-01.S", - "rv64i_m/C/C-ADDIW-01.S", - "rv64i_m/C/C-ADDW-01.S", - "rv64i_m/C/C-AND-01.S", - "rv64i_m/C/C-ANDI-01.S", - "rv64i_m/C/C-BEQZ-01.S", - "rv64i_m/C/C-BNEZ-01.S", - "rv64i_m/C/C-J-01.S", - "rv64i_m/C/C-JALR-01.S", - "rv64i_m/C/C-JR-01.S", - "rv64i_m/C/C-LD-01.S", - "rv64i_m/C/C-LDSP-01.S", - "rv64i_m/C/C-LI-01.S", - "rv64i_m/C/C-LUI-01.S", - "rv64i_m/C/C-LW-01.S", - "rv64i_m/C/C-LWSP-01.S", - "rv64i_m/C/C-MV-01.S", - "rv64i_m/C/C-OR-01.S", - "rv64i_m/C/C-SD-01.S", - "rv64i_m/C/C-SDSP-01.S", - "rv64i_m/C/C-SLLI-01.S", - "rv64i_m/C/C-SRAI-01.S", - "rv64i_m/C/C-SRLI-01.S", - "rv64i_m/C/C-SUB-01.S", - "rv64i_m/C/C-SUBW-01.S", - "rv64i_m/C/C-SW-01.S", - "rv64i_m/C/C-SWSP-01.S", - "rv64i_m/C/C-XOR-01.S", - "rv64i_m/C/I-C-EBREAK-01.S", - "rv64i_m/C/I-C-NOP-01.S" + "rv64i_m/C/C-ADD-01", + "rv64i_m/C/C-ADDI-01", + "rv64i_m/C/C-ADDI16SP-01", + "rv64i_m/C/C-ADDI4SPN-01", + "rv64i_m/C/C-ADDIW-01", + "rv64i_m/C/C-ADDW-01", + "rv64i_m/C/C-AND-01", + "rv64i_m/C/C-ANDI-01", + "rv64i_m/C/C-BEQZ-01", + "rv64i_m/C/C-BNEZ-01", + "rv64i_m/C/C-J-01", + "rv64i_m/C/C-JALR-01", + "rv64i_m/C/C-JR-01", + "rv64i_m/C/C-LD-01", + "rv64i_m/C/C-LDSP-01", + "rv64i_m/C/C-LI-01", + "rv64i_m/C/C-LUI-01", + "rv64i_m/C/C-LW-01", + "rv64i_m/C/C-LWSP-01", + "rv64i_m/C/C-MV-01", + "rv64i_m/C/C-OR-01", + "rv64i_m/C/C-SD-01", + "rv64i_m/C/C-SDSP-01", + "rv64i_m/C/C-SLLI-01", + "rv64i_m/C/C-SRAI-01", + "rv64i_m/C/C-SRLI-01", + "rv64i_m/C/C-SUB-01", + "rv64i_m/C/C-SUBW-01", + "rv64i_m/C/C-SW-01", + "rv64i_m/C/C-SWSP-01", + "rv64i_m/C/C-XOR-01", + "rv64i_m/C/I-C-EBREAK-01", + "rv64i_m/C/I-C-NOP-01" }; string imperas64iNOc[] = { `IMPERASTEST, - "rv64i_m/I/I-MISALIGN_JMP-01.S" + "rv64i_m/I/I-MISALIGN_JMP-01" }; string imperas64i[] = '{ `IMPERASTEST, - "rv64i_m/I/I-DELAY_SLOTS-01.S", - "rv64i_m/I/ADD-01.S", - "rv64i_m/I/ADDI-01.S", - "rv64i_m/I/ADDIW-01.S", - "rv64i_m/I/ADDW-01.S", - "rv64i_m/I/AND-01.S", - "rv64i_m/I/ANDI-01.S", - "rv64i_m/I/AUIPC-01.S", - "rv64i_m/I/BEQ-01.S", - "rv64i_m/I/BGE-01.S", - "rv64i_m/I/BGEU-01.S", - "rv64i_m/I/BLT-01.S", - "rv64i_m/I/BLTU-01.S", - "rv64i_m/I/BNE-01.S", - "rv64i_m/I/I-DELAY_SLOTS-01.S", - "rv64i_m/I/I-EBREAK-01.S", - "rv64i_m/I/I-ECALL-01.S", - "rv64i_m/I/I-ENDIANESS-01.S", - "rv64i_m/I/I-IO-01.S", -// "rv64i_m/I/I-MISALIGN_JMP-01.S", - "rv64i_m/I/I-MISALIGN_LDST-01.S", - "rv64i_m/I/I-NOP-01.S", - "rv64i_m/I/I-RF_size-01.S", - "rv64i_m/I/I-RF_width-01.S", - "rv64i_m/I/I-RF_x0-01.S", - "rv64i_m/I/JAL-01.S", - "rv64i_m/I/JALR-01.S", - "rv64i_m/I/LB-01.S", - "rv64i_m/I/LBU-01.S", - "rv64i_m/I/LD-01.S", - "rv64i_m/I/LH-01.S", - "rv64i_m/I/LHU-01.S", - "rv64i_m/I/LUI-01.S", - "rv64i_m/I/LW-01.S", - "rv64i_m/I/LWU-01.S", - "rv64i_m/I/OR-01.S", - "rv64i_m/I/ORI-01.S", - "rv64i_m/I/SB-01.S", - "rv64i_m/I/SD-01.S", - "rv64i_m/I/SH-01.S", - "rv64i_m/I/SLL-01.S", - "rv64i_m/I/SLLI-01.S", - "rv64i_m/I/SLLIW-01.S", - "rv64i_m/I/SLLW-01.S", - "rv64i_m/I/SLT-01.S", - "rv64i_m/I/SLTI-01.S", - "rv64i_m/I/SLTIU-01.S", - "rv64i_m/I/SLTU-01.S", - "rv64i_m/I/SRA-01.S", - "rv64i_m/I/SRAI-01.S", - "rv64i_m/I/SRAIW-01.S", - "rv64i_m/I/SRAW-01.S", - "rv64i_m/I/SRL-01.S", - "rv64i_m/I/SRLI-01.S", - "rv64i_m/I/SRLIW-01.S", - "rv64i_m/I/SRLW-01.S", - "rv64i_m/I/SUB-01.S", - "rv64i_m/I/SUBW-01.S", - "rv64i_m/I/SW-01.S", - "rv64i_m/I/XOR-01.S", - "rv64i_m/I/XORI-01.S" + "rv64i_m/I/I-DELAY_SLOTS-01", + "rv64i_m/I/ADD-01", + "rv64i_m/I/ADDI-01", + "rv64i_m/I/ADDIW-01", + "rv64i_m/I/ADDW-01", + "rv64i_m/I/AND-01", + "rv64i_m/I/ANDI-01", + "rv64i_m/I/AUIPC-01", + "rv64i_m/I/BEQ-01", + "rv64i_m/I/BGE-01", + "rv64i_m/I/BGEU-01", + "rv64i_m/I/BLT-01", + "rv64i_m/I/BLTU-01", + "rv64i_m/I/BNE-01", + "rv64i_m/I/I-DELAY_SLOTS-01", + "rv64i_m/I/I-EBREAK-01", + "rv64i_m/I/I-ECALL-01", + "rv64i_m/I/I-ENDIANESS-01", + "rv64i_m/I/I-IO-01", +// "rv64i_m/I/I-MISALIGN_JMP-01", + "rv64i_m/I/I-MISALIGN_LDST-01", + "rv64i_m/I/I-NOP-01", + "rv64i_m/I/I-RF_size-01", + "rv64i_m/I/I-RF_width-01", + "rv64i_m/I/I-RF_x0-01", + "rv64i_m/I/JAL-01", + "rv64i_m/I/JALR-01", + "rv64i_m/I/LB-01", + "rv64i_m/I/LBU-01", + "rv64i_m/I/LD-01", + "rv64i_m/I/LH-01", + "rv64i_m/I/LHU-01", + "rv64i_m/I/LUI-01", + "rv64i_m/I/LW-01", + "rv64i_m/I/LWU-01", + "rv64i_m/I/OR-01", + "rv64i_m/I/ORI-01", + "rv64i_m/I/SB-01", + "rv64i_m/I/SD-01", + "rv64i_m/I/SH-01", + "rv64i_m/I/SLL-01", + "rv64i_m/I/SLLI-01", + "rv64i_m/I/SLLIW-01", + "rv64i_m/I/SLLW-01", + "rv64i_m/I/SLT-01", + "rv64i_m/I/SLTI-01", + "rv64i_m/I/SLTIU-01", + "rv64i_m/I/SLTU-01", + "rv64i_m/I/SRA-01", + "rv64i_m/I/SRAI-01", + "rv64i_m/I/SRAIW-01", + "rv64i_m/I/SRAW-01", + "rv64i_m/I/SRL-01", + "rv64i_m/I/SRLI-01", + "rv64i_m/I/SRLIW-01", + "rv64i_m/I/SRLW-01", + "rv64i_m/I/SUB-01", + "rv64i_m/I/SUBW-01", + "rv64i_m/I/SW-01", + "rv64i_m/I/XOR-01", + "rv64i_m/I/XORI-01" }; string imperas32m[] = '{ `IMPERASTEST, - "rv32i_m/M/DIV-01.S", - "rv32i_m/M/DIVU-01.S", - "rv32i_m/M/MUL-01.S", - "rv32i_m/M/MULH-01.S", - "rv32i_m/M/MULHSU-01.S", - "rv32i_m/M/MULHU-01.S", - "rv32i_m/M/REM-01.S", - "rv32i_m/M/REMU-01.S" + "rv32i_m/M/DIV-01", + "rv32i_m/M/DIVU-01", + "rv32i_m/M/MUL-01", + "rv32i_m/M/MULH-01", + "rv32i_m/M/MULHSU-01", + "rv32i_m/M/MULHU-01", + "rv32i_m/M/REM-01", + "rv32i_m/M/REMU-01" }; string imperas32c[] = '{ `IMPERASTEST, - "rv32i_m/C/C-ADD-01.S", - "rv32i_m/C/C-ADDI-01.S", - "rv32i_m/C/C-ADDI16SP-01.S", - "rv32i_m/C/C-ADDI4SPN-01.S", - "rv32i_m/C/C-AND-01.S", - "rv32i_m/C/C-ANDI-01.S", - "rv32i_m/C/C-BEQZ-01.S", - "rv32i_m/C/C-BNEZ-01.S", - "rv32i_m/C/C-J-01.S", - "rv32i_m/C/C-JAL-01.S", - "rv32i_m/C/C-JALR-01.S", - "rv32i_m/C/C-JR-01.S", - "rv32i_m/C/C-LI-01.S", - "rv32i_m/C/C-LUI-01.S", - "rv32i_m/C/C-LW-01.S", - "rv32i_m/C/C-LWSP-01.S", - "rv32i_m/C/C-MV-01.S", - "rv32i_m/C/C-OR-01.S", - "rv32i_m/C/C-SLLI-01.S", - "rv32i_m/C/C-SRAI-01.S", - "rv32i_m/C/C-SRLI-01.S", - "rv32i_m/C/C-SUB-01.S", - "rv32i_m/C/C-SW-01.S", - "rv32i_m/C/C-SWSP-01.S", - "rv32i_m/C/C-XOR-01.S", - "rv32i_m/C/I-C-EBREAK-01.S", - "rv32i_m/C/I-C-NOP-01.S" + "rv32i_m/C/C-ADD-01", + "rv32i_m/C/C-ADDI-01", + "rv32i_m/C/C-ADDI16SP-01", + "rv32i_m/C/C-ADDI4SPN-01", + "rv32i_m/C/C-AND-01", + "rv32i_m/C/C-ANDI-01", + "rv32i_m/C/C-BEQZ-01", + "rv32i_m/C/C-BNEZ-01", + "rv32i_m/C/C-J-01", + "rv32i_m/C/C-JAL-01", + "rv32i_m/C/C-JALR-01", + "rv32i_m/C/C-JR-01", + "rv32i_m/C/C-LI-01", + "rv32i_m/C/C-LUI-01", + "rv32i_m/C/C-LW-01", + "rv32i_m/C/C-LWSP-01", + "rv32i_m/C/C-MV-01", + "rv32i_m/C/C-OR-01", + "rv32i_m/C/C-SLLI-01", + "rv32i_m/C/C-SRAI-01", + "rv32i_m/C/C-SRLI-01", + "rv32i_m/C/C-SUB-01", + "rv32i_m/C/C-SW-01", + "rv32i_m/C/C-SWSP-01", + "rv32i_m/C/C-XOR-01", + "rv32i_m/C/I-C-EBREAK-01", + "rv32i_m/C/I-C-NOP-01" }; string imperas32iNOc[] = { `IMPERASTEST, - "rv32i_m/I/I-MISALIGN_JMP-01.S" + "rv32i_m/I/I-MISALIGN_JMP-01" }; string imperas32i[] = { `IMPERASTEST, - "rv32i_m/I/ADD-01.S", - "rv32i_m/I/ADDI-01.S", - "rv32i_m/I/AND-01.S", - "rv32i_m/I/ANDI-01.S", - "rv32i_m/I/AUIPC-01.S", - "rv32i_m/I/BEQ-01.S", - "rv32i_m/I/BGE-01.S", - "rv32i_m/I/BGEU-01.S", - "rv32i_m/I/BLT-01.S", - "rv32i_m/I/BLTU-01.S", - "rv32i_m/I/BNE-01.S", - "rv32i_m/I/I-DELAY_SLOTS-01.S", - "rv32i_m/I/I-EBREAK-01.S", - "rv32i_m/I/I-ECALL-01.S", - "rv32i_m/I/I-ENDIANESS-01.S", - "rv32i_m/I/I-IO-01.S", -// "rv32i_m/I/I-MISALIGN_JMP-01.S", - "rv32i_m/I/I-MISALIGN_LDST-01.S", - "rv32i_m/I/I-NOP-01.S", - "rv32i_m/I/I-RF_size-01.S", - "rv32i_m/I/I-RF_width-01.S", - "rv32i_m/I/I-RF_x0-01.S", - "rv32i_m/I/JAL-01.S", - "rv32i_m/I/JALR-01.S", - "rv32i_m/I/LB-01.S", - "rv32i_m/I/LBU-01.S", - "rv32i_m/I/LH-01.S", - "rv32i_m/I/LHU-01.S", - "rv32i_m/I/LUI-01.S", - "rv32i_m/I/LW-01.S", - "rv32i_m/I/OR-01.S", - "rv32i_m/I/ORI-01.S", - "rv32i_m/I/SB-01.S", - "rv32i_m/I/SH-01.S", - "rv32i_m/I/SLL-01.S", - "rv32i_m/I/SLLI-01.S", - "rv32i_m/I/SLT-01.S", - "rv32i_m/I/SLTI-01.S", - "rv32i_m/I/SLTIU-01.S", - "rv32i_m/I/SLTU-01.S", - "rv32i_m/I/SRA-01.S", - "rv32i_m/I/SRAI-01.S", - "rv32i_m/I/SRL-01.S", - "rv32i_m/I/SRLI-01.S", - "rv32i_m/I/SUB-01.S", - "rv32i_m/I/SW-01.S", - "rv32i_m/I/XOR-01.S", - "rv32i_m/I/XORI-01.S" + "rv32i_m/I/ADD-01", + "rv32i_m/I/ADDI-01", + "rv32i_m/I/AND-01", + "rv32i_m/I/ANDI-01", + "rv32i_m/I/AUIPC-01", + "rv32i_m/I/BEQ-01", + "rv32i_m/I/BGE-01", + "rv32i_m/I/BGEU-01", + "rv32i_m/I/BLT-01", + "rv32i_m/I/BLTU-01", + "rv32i_m/I/BNE-01", + "rv32i_m/I/I-DELAY_SLOTS-01", + "rv32i_m/I/I-EBREAK-01", + "rv32i_m/I/I-ECALL-01", + "rv32i_m/I/I-ENDIANESS-01", + "rv32i_m/I/I-IO-01", +// "rv32i_m/I/I-MISALIGN_JMP-01", + "rv32i_m/I/I-MISALIGN_LDST-01", + "rv32i_m/I/I-NOP-01", + "rv32i_m/I/I-RF_size-01", + "rv32i_m/I/I-RF_width-01", + "rv32i_m/I/I-RF_x0-01", + "rv32i_m/I/JAL-01", + "rv32i_m/I/JALR-01", + "rv32i_m/I/LB-01", + "rv32i_m/I/LBU-01", + "rv32i_m/I/LH-01", + "rv32i_m/I/LHU-01", + "rv32i_m/I/LUI-01", + "rv32i_m/I/LW-01", + "rv32i_m/I/OR-01", + "rv32i_m/I/ORI-01", + "rv32i_m/I/SB-01", + "rv32i_m/I/SH-01", + "rv32i_m/I/SLL-01", + "rv32i_m/I/SLLI-01", + "rv32i_m/I/SLT-01", + "rv32i_m/I/SLTI-01", + "rv32i_m/I/SLTIU-01", + "rv32i_m/I/SLTU-01", + "rv32i_m/I/SRA-01", + "rv32i_m/I/SRAI-01", + "rv32i_m/I/SRL-01", + "rv32i_m/I/SRLI-01", + "rv32i_m/I/SUB-01", + "rv32i_m/I/SW-01", + "rv32i_m/I/XOR-01", + "rv32i_m/I/XORI-01" }; - string wally64a[] = '{ + string wally64a[] = '{ `WALLYTEST, "rv64i_m/privilege/src/WALLY-amo-01.S", "rv64i_m/privilege/src/WALLY-lrsc-01.S" }; - string wally32a[] = '{ + string wally32a[] = '{ `WALLYTEST, "rv32i_m/privilege/src/WALLY-amo-01.S", "rv32i_m/privilege/src/WALLY-lrsc-01.S" - }; + }; string arch64priv[] = '{ `RISCVARCHTEST, @@ -1366,65 +1366,6 @@ string imperas32f[] = '{ "rv64i_m/D/src/fssub.d_b8-01.S" }; - string arch64zba[] = '{ - `RISCVARCHTEST, - "rv64i_m/B/src/slli.uw-01.S", - "rv64i_m/B/src/add.uw-01.S", - "rv64i_m/B/src/sh1add-01.S", - "rv64i_m/B/src/sh2add-01.S", - "rv64i_m/B/src/sh3add-01.S", - "rv64i_m/B/src/sh1add.uw-01.S", - "rv64i_m/B/src/sh2add.uw-01.S", - "rv64i_m/B/src/sh3add.uw-01.S" - }; - -string arch64zbb[] = '{ - `RISCVARCHTEST, - "rv64i_m/B/src/max-01.S", - "rv64i_m/B/src/maxu-01.S", - "rv64i_m/B/src/min-01.S", - "rv64i_m/B/src/minu-01.S", - "rv64i_m/B/src/orcb_64-01.S", - "rv64i_m/B/src/rev8-01.S", - "rv64i_m/B/src/andn-01.S", - "rv64i_m/B/src/orn-01.S", - "rv64i_m/B/src/xnor-01.S", - "rv64i_m/B/src/zext.h-01.S", - "rv64i_m/B/src/sext.b-01.S", - "rv64i_m/B/src/sext.h-01.S", - "rv64i_m/B/src/clz-01.S", - "rv64i_m/B/src/clzw-01.S", - "rv64i_m/B/src/cpop-01.S", - "rv64i_m/B/src/cpopw-01.S", - "rv64i_m/B/src/ctz-01.S", - "rv64i_m/B/src/ctzw-01.S", - "rv64i_m/B/src/rolw-01.S", - "rv64i_m/B/src/ror-01.S", - "rv64i_m/B/src/rori-01.S", - "rv64i_m/B/src/roriw-01.S", - "rv64i_m/B/src/rorw-01.S", - "rv64i_m/B/src/rol-01.S" -}; - -string arch64zbc[] = '{ - `RISCVARCHTEST, - "rv64i_m/B/src/clmul-01.S", - "rv64i_m/B/src/clmulh-01.S", - "rv64i_m/B/src/clmulr-01.S" -}; - -string arch64zbs[] = '{ - `RISCVARCHTEST, - "rv64i_m/B/src/bclr-01.S", - "rv64i_m/B/src/bclri-01.S", - "rv64i_m/B/src/bext-01.S", - "rv64i_m/B/src/bexti-01.S", - "rv64i_m/B/src/binv-01.S", - "rv64i_m/B/src/binvi-01.S", - "rv64i_m/B/src/bset-01.S", - "rv64i_m/B/src/bseti-01.S" -}; - string arch32priv[] = '{ `RISCVARCHTEST, "rv32i_m/privilege/src/ebreak.S", From 8ef5422f67e5cd1e067dac91b9453a9bcb9e3332 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 14:16:07 -0700 Subject: [PATCH 181/231] fixed sim-wally-batch --- sim/sim-wally-batch | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/sim-wally-batch b/sim/sim-wally-batch index 4fa06d3cf..46c35c75c 100755 --- a/sim/sim-wally-batch +++ b/sim/sim-wally-batch @@ -1 +1 @@ -vsim -c -do "do wally-batch.do rv32gc wally32priv" \ No newline at end of file +vsim -c -do "do wally-batch.do rv32gc wally32priv" From a4e5abad22c4e08e957837c9d2e39e9ba380d177 Mon Sep 17 00:00:00 2001 From: James Stine Date: Wed, 22 Mar 2023 16:23:27 -0500 Subject: [PATCH 182/231] Change order of coverage and all in sim directory - order causing issue with compilation process of regression tests --- sim/Makefile | 33 +++++++++++++++++---------------- 1 file changed, 17 insertions(+), 16 deletions(-) diff --git a/sim/Makefile b/sim/Makefile index 1c31e1f24..bf6255b33 100644 --- a/sim/Makefile +++ b/sim/Makefile @@ -1,3 +1,20 @@ + +all: riscoftests memfiles + # *** Build old tests/imperas-riscv-tests for now; + # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test + # DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired + #make -C ../tests/imperas-riscv-tests --jobs + #make -C ../tests/imperas-riscv-tests XLEN=64 --jobs + # Only compile Imperas tests if they are installed locally. + # They are usually a symlink to $RISCV/imperas-riscv-tests and only + # get compiled there manually during installation + #make -C ../addins/imperas-riscv-tests + #make -C ../addins/imperas-riscv-tests XLEN=64 + #cd ../addins/imperas-riscv-tests; elf2hex.sh + #cd ../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump + # Link Linux test vectors + #cd ../tests/linux-testgen/linux-testvectors/;./tvLinker.sh + coverage: #make -C ../tests/coverage --jobs #iter-elf.bash --cover --search ../tests/coverage @@ -21,22 +38,6 @@ coverage: # vcover report -recursive cov/cov.ucdb > cov/rv64gc_recursive.rpt vcover report -details -threshH 100 -html cov/cov.ucdb -all: riscoftests memfiles - # *** Build old tests/imperas-riscv-tests for now; - # Delete this part when the privileged tests transition over to tests/wally-riscv-arch-test - # DH: 2/27/22 temporarily commented out imperas-riscv-tests because license expired - #make -C ../tests/imperas-riscv-tests --jobs - #make -C ../tests/imperas-riscv-tests XLEN=64 --jobs - # Only compile Imperas tests if they are installed locally. - # They are usually a symlink to $RISCV/imperas-riscv-tests and only - # get compiled there manually during installation - #make -C ../addins/imperas-riscv-tests - #make -C ../addins/imperas-riscv-tests XLEN=64 - #cd ../addins/imperas-riscv-tests; elf2hex.sh - #cd ../addins/imperas-riscv-tests; extractFunctionRadix.sh work/*/*/*.elf.objdump - # Link Linux test vectors - #cd ../tests/linux-testgen/linux-testvectors/;./tvLinker.sh - allclean: clean all clean: From 3a581c95a5760d0c4348c52bc2798015b4330618 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 15:44:26 -0700 Subject: [PATCH 183/231] restored arch 64 bit manip tests --- testbench/tests.vh | 59 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/testbench/tests.vh b/testbench/tests.vh index 17d9fea0c..668da4b7b 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1366,6 +1366,65 @@ string imperas32f[] = '{ "rv64i_m/D/src/fssub.d_b8-01.S" }; +string arch64zba[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/slli.uw-01.S", + "rv64i_m/B/src/add.uw-01.S", + "rv64i_m/B/src/sh1add-01.S", + "rv64i_m/B/src/sh2add-01.S", + "rv64i_m/B/src/sh3add-01.S", + "rv64i_m/B/src/sh1add.uw-01.S", + "rv64i_m/B/src/sh2add.uw-01.S", + "rv64i_m/B/src/sh3add.uw-01.S" + }; + +string arch64zbb[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/max-01.S", + "rv64i_m/B/src/maxu-01.S", + "rv64i_m/B/src/min-01.S", + "rv64i_m/B/src/minu-01.S", + "rv64i_m/B/src/orcb_64-01.S", + "rv64i_m/B/src/rev8-01.S", + "rv64i_m/B/src/andn-01.S", + "rv64i_m/B/src/orn-01.S", + "rv64i_m/B/src/xnor-01.S", + "rv64i_m/B/src/zext.h-01.S", + "rv64i_m/B/src/sext.b-01.S", + "rv64i_m/B/src/sext.h-01.S", + "rv64i_m/B/src/clz-01.S", + "rv64i_m/B/src/clzw-01.S", + "rv64i_m/B/src/cpop-01.S", + "rv64i_m/B/src/cpopw-01.S", + "rv64i_m/B/src/ctz-01.S", + "rv64i_m/B/src/ctzw-01.S", + "rv64i_m/B/src/rolw-01.S", + "rv64i_m/B/src/ror-01.S", + "rv64i_m/B/src/rori-01.S", + "rv64i_m/B/src/roriw-01.S", + "rv64i_m/B/src/rorw-01.S", + "rv64i_m/B/src/rol-01.S" +}; + +string arch64zbc[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/clmul-01.S", + "rv64i_m/B/src/clmulh-01.S", + "rv64i_m/B/src/clmulr-01.S" +}; + +string arch64zbs[] = '{ + `RISCVARCHTEST, + "rv64i_m/B/src/bclr-01.S", + "rv64i_m/B/src/bclri-01.S", + "rv64i_m/B/src/bext-01.S", + "rv64i_m/B/src/bexti-01.S", + "rv64i_m/B/src/binv-01.S", + "rv64i_m/B/src/binvi-01.S", + "rv64i_m/B/src/bset-01.S", + "rv64i_m/B/src/bseti-01.S" +}; + string arch32priv[] = '{ `RISCVARCHTEST, "rv32i_m/privilege/src/ebreak.S", From f73ba47bfd6dd4878c35414567d0b77094bdea75 Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Wed, 22 Mar 2023 15:51:08 -0700 Subject: [PATCH 184/231] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index f7abf0ba1..03893ca0d 100644 --- a/README.md +++ b/README.md @@ -62,7 +62,7 @@ This section describes the open source toolchain installation. These steps shou ## TL;DR Open Source Tool-chain Installation -The full instalation details are involved can be be skipped using the following script, wally-tool-chain-install.sh. +The full installation details are involved can be be skipped using the following script, wally-tool-chain-install.sh. The script installs the open source tools to /opt/riscv by default. This can be changed by supply the path as the first argument. This script does not install buildroot (see the Detailed Tool-chain Install Guide in the following section) and does not install commercial EDA tools; Siemens Questa, Synopsys Design Compiler, or Cadence Innovus (see section Installing IDA Tools). It must be run as root or with sudo. This script is tested for Ubuntu, 20.04 and 22.04. Fedora and Red Hat can be installed in the Detailed Tool-chain Install Guide. $ sudo wally-tool-chain-install.sh From b11764026646d69ec2c576ee08d55d5990239c51 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 22 Mar 2023 16:11:59 -0700 Subject: [PATCH 185/231] Updating install instructions --- Install | 333 -------------------------------- README.md | 2 +- bin/wally-tool-chain-install.sh | 5 + 3 files changed, 6 insertions(+), 334 deletions(-) delete mode 100644 Install diff --git a/Install b/Install deleted file mode 100644 index 47a91dddd..000000000 --- a/Install +++ /dev/null @@ -1,333 +0,0 @@ -Complete Wally Installation guide -Formally RISC-V System on Chip Design Appendix D - -Sections: -1. RISC-V Tool Installation (Sys Admin) -2. Core-v-wally Repo Installation -3. Build and Run Regression Tests - -Section 1 tool install should be done once by a system admin with root access. The specific details may need to be -adjusted as some tools may already be present on the system. This guide assumes all compiled from source tools are -installed at base diretory $RISCV. - -* Tool-chain Installation (Sys Admin) - -** TL;DR Open Source Tool-chain Installation - - The installing details are involved, but can be skipped using the following script. wally-tool-chain-install.sh installs the open source tools to RISCV=/opt/riscv by default. Change by supplying an alternate path as an argument, (ie. wally-tool-chain-install.sh /mnt/disk1/riscv). - This install script does NOT install buildroot or commercial EDA tools; Questa, Design Compiler, or Innovus. - It must be run as root or with sudo. - This script is tested for Ubuntu, 20.04 and 22.04 - - wally-tool-chain-install.sh - - The step by step instructions include Red Hat 8 / Fedora. - -** Detailed Tool-chain Instal Guide - Section 2.1 described Wally platform requirements and Section 2.2 describes how a user gets started using Wally on a Linux server. This appendix describes how the system administrator installs RISC-V tools. Superuser privileges are necessary for many of the tools. Setting up all of the tools can be time-consuming and fussy, so this appendix also describes a fallback flow with Docker and Podman. - -*** Open Source Software Installation - -Compiling, assembling, and simulating RISC-V programs requires downloading and installing the following free tools: - -1. The GCC cross-compiler -2. A RISC-V simulator such as Spike, Sail, and/or QEMU -3. Spike is easy to use but doesn’t support peripherals to boot Linux -4. QEMU is faster and can boot Linux -5. Sail is presently the official golden reference for RISC-V and is used by the riscof verification suite, but runs slowly and is painful to instal - -This setup needs to be done once by the administrator - -Note: The following directions assume you have an account called cad to install shared software and files. You can substitute a different user for cad if you prefer. - -Note: Installing software in Linux is unreasonably touchy and varies with the flavor and version of your Linux distribution. Don’t be surprised if the installation directions have changed since the book was written or don’t work on your machine; you may need some ingenuity to adjust them. Browse the openhwgroup/core-v-wally repo and look at the README.md for the latest build instructions. - -*** Create the $RISCV Directory - -First, set up a directory for riscv software in some place such as /opt/riscv. We will call this shared directory $RISCV. - -$ export RISCV=/opt/riscv -$ sudo mkdir $RISCV -$ sudo chown cad $RISCV -$ sudo su cad (or root, if you don’t have a cad account) -$ export RISCV=/opt/riscv -$ chmod 755 $RISCV -$ umask 0002 -$ cd $RISCV - -*** Update Tools - -Ubuntu users may need to install and update various tools. - -$ sudo apt update -$ sudo apt upgrade -$ sudo apt install git gawk make texinfo bison flex build-essential python libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libglib2.56-dev libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog - -*** Install RISC-V GCC Cross-Compiler - -To install GCC from source can take hours to compile. This configuration enables multilib to target many flavors of RISC-V. This book is tested with GCC 12.2 (tagged 2022.09.21), but will likely work with newer versions as well. - -$ git clone https://github.com/riscv/riscv-gnu-toolchain -$ cd riscv-gnu-toolchain -$ git checkout 2022.09.21 -$ ./configure --prefix=$RISCV --enable-multilib --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" -$ make --jobs - -Note: make --jobs will reduce compile time by compiling in parallel. However, adding this option could dramatically increase the memory utilization of your local machine. - -*** Install elf2hex - -We also need the elf2hex utility to convert executable files into hexadecimal files for Verilog simulation. Install with: - -$ cd $RISCV -$ export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH -$ git clone https://github.com/sifive/elf2hex.git -$ cd elf2hex -$ autoreconf -i -$ ./configure --target=riscv64-unknown-elf --prefix=$RISCV -$ make -$ make install - -Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t handle programs that start at 0x80000000. The SiFive version above is touchy to install. For example, if Python version 2.x is in your path, it won’t install correctly. Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin at the time of compilation, or elf2hex won’t work properly. - -*** Install RISC-V Spike Simulator - -Spike also takes a while to install and compile, but this can be done concurrently with the GCC installation. After the build, we need to change two Makefiles to support atomic instructions . - -$ cd $RISCV -$ git clone https://github.com/riscv-software-src/riscv-isa-sim -$ mkdir riscv-isa-sim/build -$ cd riscv-isa-sim/build -$ ../configure --prefix=$RISCV --enable-commitlog -$ make --jobs -$ make install -$ cd ../arch_test_target/spike/device -$ sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include -$ sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include - -*** Install Sail Simulator - -Sail is the new golden reference model for RISC-V. Sail is written in OCaml, which is an object-oriented extension of ML, which in turn is a functional programming language suited to formal verification. OCaml is installed with the opam OCcaml package manager. Sail has so many dependencies that it can be difficult to install. - -On Ubuntu, apt-get makes opam installation fairly simple. - -$ sudo apt-get install opam build-essential libgmp-dev z3 pkg-config zlib1g-dev - -If you are on RedHat/Rocky Linux 8, installation is much more difficult because packages are not available in the default package manager and some need to be built from source. - -$ sudo bash -c "sh <(curl -fsSL https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh)" - When prompted, put it in /usr/bin -$ sudo yum groupinstall 'Development Tools' -$ sudo yum -y install gmp-devel -$ sudo yum -y install zlib-devel -$ git clone https://github.com/Z3Prover/z3.git -$ cd z3 -$ python scripts/mk_make.py -$ cd build -$ make -$ sudo make install -$ cd ../.. -$ sudo pip3 install chardet==3.0.4 -$ sudo pip3 install urllib3==1.22 - -Once you have installed the packages on either Ubuntu or RedHat, use opam to install the OCaml compiler and Sail. Run as the cad user because you will be installing Sail in $RISCV. - -$ sudo su cad -$ opam init -y --disable-sandboxing -$ opam switch create ocaml-base-compiler.4.06.1 -$ opam install sail -y - -Now you can clone and compile Sail-RISCV. This will take a while. - -$ eval $(opam config env) -$ cd $RISCV -$ git clone https://github.com/riscv/sail-riscv.git -$ cd sail-riscv -$ make -$ ARCH=RV32 make -$ ARCH=RV64 make -$ exit -$ sudo su -$ export RISCV=/opt/riscv -$ ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64 -$ ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 -$ exit - -*** Install riscof - -riscof is a Python library used as the RISC-V compatibility framework test an implementation such as Wally or Spike against the Sail golden reference. It will be used to compile the riscv-arch-test suite. - -It is most convenient if the sysadmin installs riscof into the server’s Python libraries: - -$ sudo pip3 install testresources -$ sudo pip3 install riscof --ignore-installed PyYAML - -However, riscof can also be installed and run locally by individual users. - -*** Install Verilator - -Verilator is a free Verilog simulator with a good Lint tool used to catch errors in the SystemVerilog code. It is needed to run regression. -$ sudo apt install verilator - -*** Install QEMU Simulator - -QEMU is another simulator used when booting Linux in Chapter 17. You can optionally install it using the following commands. - - -The QEMU patch changes the VirtIO driver to match the Wally peripherals, and also adds print statements to log the state of the CSRs (see Section 2.5XREF). - - -$ cd $RISCV -$ git clone --recurse-submodules https://github.com/qemu/qemu -$ cd qemu -$ git checkout v6.2.0 # last version tested; newer versions might be ok -$ ./configure --target-list=riscv64-softmmu --prefix=$RISCV -$ make --jobs -$ make install - -*** Cross-Compile Buildroot Linux - -Building Linux is only necessary for exploring the boot process in Chapter 17. Building and generating a trace is a time-consuming operation that could be skipped for now; you can return to this section later if you are interested in the Linux details. - -Buildroot depends on configuration files in riscv-wally, so the cad user must install Wally first according to the instructions in Section 2.2.2. However, don’t source ~/wally-riscv/setup.sh because it will set LD_LIBRARY_PATH in a way to cause make to fail on buildroot. - -To configure and build Buildroot: - -$ cd $RISCV -$ export WALLY=~/riscv-wally # make sure you haven’t sourced ~/riscv-wally/setup.sh by now -$ git clone https://github.com/buildroot/buildroot.git -$ cd buildroot -$ git checkout 2021.05 # last tested working version -$ cp -r $WALLY/linux/buildroot-config-src/wally ./board -$ cp ./board/wally/main.config .config -$ make --jobs - -To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb. - -$ source ~/riscv-wally/setup.sh -$ cd $WALLY/linux/buildroot-scripts -$ make all - -Note: When the make tasks complete, you’ll find source code in $RISCV/buildroot/output/build and the executables in $RISCV/buildroot/output/images. - -*** Download Synthesis Libraries - -For logic synthesis, we need a synthesis tool (see Section 3.XREF) and a cell library. Clone the OSU 12-track cell library for the Skywater 130 nm process: - -$ cd $RISCV -$ mkdir cad -$ mkdir cad/lib -$ cd cad/lib -$ git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12 - -** Installing EDA Tools - -Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs. Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text. The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally. It is anticipated that additional tools may be documented later after this is text is published to improve use and access. - -Siemens Quest is the primary tool utilized for simulating and validating Wally. For logic synthesis, you will need Synopsys Design Compiler. Questa and Design Compiler are commercial tools that require an educational or commercial license. - -Note: Some EDA tools utilize LM_LICENSE_FILE for their environmental variable to point to their license server. Some operating systems may also utilize MGLS_LICENSE_FILE instead, therefore, it is important to read the user manual on the preferred environmental variable required to point to a user’s license file. Although there are different mechanisms to allow licenses to work, many companies commonly utilize the FlexLM (i.e., Flex-enabled) license server manager that runs off a node locked license. - -Although most EDA tools are Linux-friendly, they tend to have issues when not installed on recommended OS flavors. Both Red Hat Enterprise Linux and SUSE Linux products typically tend to be recommended for installing commercial-based EDA tools and are recommended for utilizing complex simulation and architecture exploration. Questa can also be installed on Microsoft Windows as well as Mac OS with a Virtual Machine such as Parallels. - -Siemens Questa - -Siemens Questa simulates behavioral, RTL and gate-level HDL. To install Siemens Questa first go to a web browser and navigate to -https://eda.sw.siemens.com/en-US/ic/questa/simulation/advanced-simulator/. Click Sign In and log in with your credentials and the product can easily be downloaded and installed. Some Windows-based installations also require gcc libraries that are typically provided as a compressed zip download through Siemens. - -Synopsys Design Compiler (DC) - -Many commercial synthesis and place and route tools require a common installer. These installers are provided by the EDA vendor and Synopsys has one called Synopsys Installer. To use Synopsys Installer, you will need to acquire a license through Synopsys that is typically Called Synopsys Common Licensing (SCL). Both the Synopsys Installer, license key file, and Design Compiler can all be downloaded through Synopsys Solvnet. First open a web browser, log into Synsopsy Solvnet, and download the installer and Design Compiler installation files. Then, install the Installer - -$ firefox & -Navigate to https://solvnet.synopsys.com -Log in with your institution’s username and password -Click on Downloads, then scroll down to Synopsys Installer -Select the latest version (currently 5.4). Click Download Here, agree, -Click on SynopsysInstaller_v5.4.run -Return to downloads and also get Design Compiler (synthesis) latest version, and any others you want. - Click on all parts and the .spf file, then click Download Files near the top -move the SynopsysIntaller into /cad/synopsys/Installer_5.4 with 755 permission for cad, -move other files into /cad/synopsys/downloads and work as user cad from here on -$ cd /cad/synopsys/installer_5.4 -$ ./SynopsysInstaller_v5.4.run -Accept default installation directory -$ ./installer -Enter source path as /cad/synopsys/downloads, and installation path as /cad/synopsys -When prompted, enter your site ID -Follow prompts - -Installer can be utilized in graphical or text-based modes. It is far easier to use the text-based installation tool. To install DC, navigate to the location where your downloaded DC files are and type installer. You should be prompted with questions related to where you wish to have your files installed. - -The Synopsys Installer automatically installs all downloaded product files into a single top-level target directory. You do not need to specify the installation directory for each product. For example, if you specify /import/programs/synopsys as the target directory, your installation directory structure might look like this after installation: - -/import/programs/synopsys/syn/S-2021.06-SP1 - -Note: Although most parts of Wally, including the software used in this chapter and Questa simulation, will work on most modern Linux platforms, as of 2022, the Synopsys CAD tools for SoC design are only supported on RedHat Enterprise Linux 7.4 or 8 or SUSE Linux Enterprise Server (SLES) 12 or 15. Moreover, the RISC-V formal specification (sail-riscv) does not build gracefully on RHEL7. - -The Verilog simulation has been tested with Siemens Questa/ModelSim. This package is available to universities worldwide as part of the Design Verification Bundle through the Siemens Academic Partner Program members for $990/year. - -If you want to implement your own version of the chip, your tool and license complexity rises significantly. Logic synthesis uses Synopsys Design Compiler. Placement and routing uses Cadence Innovus. Both Synopsys and Cadence offer their tools at a steep discount to their university program members, but the cost is still several thousand dollars per year. Most research universities with integrated circuit design programs have Siemens, Synopsys, and Cadence licenses. You also need a process design kit (PDK) for a specific integrated circuit technology and its libraries. The open-source Google Skywater 130 nm PDK is sufficient to synthesize the core but lacks memories. Google presently funds some fabrication runs for universities. IMEC and Muse Semiconductor offers full access to multiproject wafer fabrication on the TSMC 28 nm process including logic, I/O, and memory libraries; this involves three non-disclosure agreements. Fabrication costs on the order of $10,000 for a batch of 1 mm2 chips. - -Startups can expect to spend more than $1 million on CAD tools to get a chip to market. Commercial CAD tools are not realistically available to individuals without a university or company connection. - -* Core-v-wally Repo Installation -** TL;DR Repo Install -cd -git clone --recurse-submodules https://github.com/davidharrishmc/riscv-wally -cd riscv-wally -source ./setup.sh # may require some modification for your system. Always run once after opening a new terminal. - -** Detailed Repo Install Guide - -1. cd - Return to home directory. The home directory is sufficent a location for students. - However more advanced users may choose to clone wally into another directory. - -2. git clone --recurse-submodules https://github.com/davidharrishmc/riscv-wally - Clone the wally repository and all dependent submodules into subdirectory riscv-wally. - -3. cd riscv-wally - Change directory to the wally repos riscv-wally. - -4. source ./setup.sh - setup.sh is s configuration script which creates several environment variables. - WALLY: Absolute directory path to this repo clone. - MGLS_LICENSE_FILE: Siemens license server for questa sim (modelsim). If your computer - is already configured for questa remove variable. - SNPSLMD_LICENSE_FILE: Synopsys license server. If remove if already setup. - PATH: PATH is extended to include the installation directories for Siemens questa and - Synopsys design compiler. Remove if already setup. - Adds riscv-gnu-toolchain and spike to PATH. Adjust if installed in another location. - Or remove if already in the PATH variable. - Adds path to wally repo specific tools. (Must include.) - Adds path to verilator. Remove if already in path. - RISCV: This is the location of the riscv tool chain and other wally requirements. - See the Sys Admin section for details. - - If using ubuntu 22.04 setup.sh can be reduced to - - echo "Executing Wally setup.sh" - - # Path to Wally repository - #!/bin/bash - - WALLY=$(dirname ${BASH_SOURCE[0]:-$0}) - export WALLY=$(cd "$WALLY" && pwd) - echo \$WALLY set to ${WALLY} - - # Path to RISC-V Tools - export RISCV=/opt/riscv # change this if you installed the tools in a different location - - # utility functions in Wally repository - export PATH=$PATH:$RISCV/bin - export PATH=$WALLY/bin:$PATH - -* Build and Run Regression Tests - Ensure the system tools are installed. - - cd - make - cd sim - ./regression-wally #(depends on having Questa installed) - diff --git a/README.md b/README.md index d8c2432d4..668510a82 100644 --- a/README.md +++ b/README.md @@ -65,7 +65,7 @@ This section describes the open source toolchain installation. These steps shou The full instalation details are involved can be be skipped using the following script, wally-tool-chain-install.sh. The script installs the open source tools to /opt/riscv by default. This can be changed by supply the path as the first argument. This script does not install buildroot (see the Detailed Tool-chain Install Guide in the following section) and does not install commercial EDA tools; Siemens Questa, Synopsys Design Compiler, or Cadence Innovus (see section Installing IDA Tools). It must be run as root or with sudo. This script is tested for Ubuntu, 20.04 and 22.04. Fedora and Red Hat can be installed in the Detailed Tool-chain Install Guide. - $ sudo wally-tool-chain-install.sh + $ sudo bin/wally-tool-chain-install.sh ## Detailed Toolchain Install Guide diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 331ca13d6..eaaac1455 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -39,6 +39,7 @@ sudo mkdir -p $RISCV # UPDATE / UPGRADE apt update +apt upgrade # INSTALL apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev @@ -134,3 +135,7 @@ curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo && echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \ && sudo apt update \ && sudo apt install gh -y + +# Other python libraries used through the book. +sudo pip3 install matplotlib scipy sklearn adjustText leif + From a29769b7baba23f6b4b4cb317b2d48ee6960b4be Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 06:37:48 -0700 Subject: [PATCH 186/231] Updated README for upstream repo --- README.md | 1 + 1 file changed, 1 insertion(+) diff --git a/README.md b/README.md index f7abf0ba1..5a93b1a19 100644 --- a/README.md +++ b/README.md @@ -40,6 +40,7 @@ Clone your fork of the repo, run the setup script, and build the tests: $ cd $ git clone --recurse-submodules https://github.com//cvw + $ git remote add upstream https://github.com/openhwgroup/cvw $ cd cvw $ source ./setup.sh $ make From 610b50a693e736e2fa65d261ba4ead4e84d04631 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 06:38:00 -0700 Subject: [PATCH 187/231] Added new tests from class --- tests/coverage/badinstr.S | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tests/coverage/badinstr.S b/tests/coverage/badinstr.S index ec875eaac..7714ab07b 100644 --- a/tests/coverage/badinstr.S +++ b/tests/coverage/badinstr.S @@ -30,7 +30,12 @@ main: .word 0x00000033 // legal R-type instruction .word 0x80000033 // illegal R-type instruction .word 0x00007003 // illegal Load instruction + .word 0x80005013 // illegal I-type instruction: srli: op = 0010011, funct3 = 101, funct7 = 1000000 .word 0x00000000 // illegal instruction + .word 0x0000701B // Illegal IW instruction + .word 0x00004023 // Illegal store instruction + .word 0x0400003B // Illegal RW or MulDivW instruction + .word 0x00007067 // Illegal JALR instruction j done From 0f9ecd5003876c242fd9d910610573b4936e6438 Mon Sep 17 00:00:00 2001 From: James Stine Date: Thu, 23 Mar 2023 09:13:40 -0500 Subject: [PATCH 188/231] Update README by removing install instructions since script is now available --- README.md | 224 ++---------------------------------------------------- 1 file changed, 6 insertions(+), 218 deletions(-) diff --git a/README.md b/README.md index 695700907..5339eca0a 100644 --- a/README.md +++ b/README.md @@ -58,224 +58,12 @@ Run a regression simulation with Questa to prove everything is installed. # Toolchain Installation (Sys Admin) -This section describes the open source toolchain installation. These steps should only be done once by the system admin. - -## TL;DR Open Source Tool-chain Installation - -The full installation details are involved can be be skipped using the following script, wally-tool-chain-install.sh. -The script installs the open source tools to /opt/riscv by default. This can be changed by supply the path as the first argument. This script does not install buildroot (see the Detailed Tool-chain Install Guide in the following section) and does not install commercial EDA tools; Siemens Questa, Synopsys Design Compiler, or Cadence Innovus (see section Installing IDA Tools). It must be run as root or with sudo. This script is tested for Ubuntu, 20.04 and 22.04. Fedora and Red Hat can be installed in the Detailed Tool-chain Install Guide. - - $ sudo bin/wally-tool-chain-install.sh - -## Detailed Toolchain Install Guide - -This section describes how to install the tools needed for CORE-V-Wally. Superuser privileges are necessary for many of the tools. Setting up all of the tools can be time-consuming and fussy, so Appendix D also describes an option with a Docker container. - -### Open Source Software Installation - -Compiling, assembling, and simulating RISC-V programs requires downloading and installing the following free tools: - -1. The GCC cross-compiler -2. A RISC-V simulator such as Spike, Sail, and/or QEMU -3. Spike is easy to use but doesn’t support peripherals to boot Linux -4. QEMU is faster and can boot Linux -5. Sail is presently the official golden reference for RISC-V and is used by the riscof verification suite, but runs slowly and is painful to instal - -This setup needs to be done once by the administrator - -Note: The following directions assume you have an account called cad to install shared software and files. You can substitute a different user for cad if you prefer. - -Note: Installing software in Linux is unreasonably touchy and varies with the flavor and version of your Linux distribution. Don’t be surprised if the installation directions have changed since the book was written or don’t work on your machine; you may need some ingenuity to adjust them. Browse the openhwgroup/core-v-wally repo and look at the README.md for the latest build instructions. - -### Create the $RISCV Directory - -First, set up a directory for riscv software in some place such as /opt/riscv. We will call this shared directory $RISCV. - - $ export RISCV=/opt/riscv - $ sudo mkdir $RISCV - $ sudo chown cad $RISCV - $ sudo su cad (or root, if you don’t have a cad account) - $ export RISCV=/opt/riscv - $ chmod 755 $RISCV - $ umask 0002 - $ cd $RISCV - -### Update Tools - -Ubuntu users may need to install and update various tools. Beware when cutting and pasting that some lines are long! - - $ sudo apt update - $ sudo apt upgrade - $ sudo apt install git gawk make texinfo bison flex build-essential python3 zlib1g-dev libexpat-dev autoconf device-tree-compiler ninja-build libglib2.0-dev libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog - -### Install RISC-V GCC Cross-Compiler - -To install GCC from source can take hours to compile. This configuration enables multilib to target many flavors of RISC-V. This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well. - - $ git clone https://github.com/riscv/riscv-gnu-toolchain - $ cd riscv-gnu-toolchain - $ git checkout 2023.01.31 - $ ./configure --prefix=$RISCV --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" - $ make --jobs - -Note: make --jobs will reduce compile time by compiling in parallel. However, adding this option could dramatically increase the memory utilization of your local machine. - -### Install elf2hex - -We also need the elf2hex utility to convert executable files into hexadecimal files for Verilog simulation. Install with: - - $ cd $RISCV - $ export PATH=$RISCV/bin:$PATH - $ git clone https://github.com/sifive/elf2hex.git - $ cd elf2hex - $ autoreconf -i - $ ./configure --target=riscv64-unknown-elf --prefix=$RISCV - $ make - $ make install - -Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t handle programs that start at 0x80000000. The SiFive version above is touchy to install. For example, if Python version 2.x is in your path, it won’t install correctly. Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin at the time of compilation, or elf2hex won’t work properly. - -### Install RISC-V Spike Simulator - -Spike also takes a while to install and compile, but this can be done concurrently with the GCC installation. After the build, we need to change two Makefiles to support atomic instructions . - - $ cd $RISCV - $ git clone https://github.com/riscv-software-src/riscv-isa-sim - $ mkdir riscv-isa-sim/build - $ cd riscv-isa-sim/build - $ ../configure --prefix=$RISCV - $ make --jobs - $ make install - $ cd ../arch_test_target/spike/device - $ sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include - $ sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include - -### Install Sail Simulator - -Sail is the new golden reference model for RISC-V. Sail is written in OCaml, which is an object-oriented extension of ML, which in turn is a functional programming language suited to formal verification. OCaml is installed with the opam OCcaml package manager. Sail has so many dependencies that it can be difficult to install. - -On Ubuntu, apt-get makes opam installation fairly simple. - -$ sudo apt-get install opam build-essential libgmp-dev z3 pkg-config zlib1g-dev - -If you are on RedHat/Rocky Linux 8, installation is much more difficult because packages are not available in the default package manager and some need to be built from source. - - $ sudo bash -c "sh <(curl -fsSL https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh)" - When prompted, put it in /usr/bin - $ sudo yum groupinstall 'Development Tools' - $ sudo yum -y install gmp-devel - $ sudo yum -y install zlib-devel - $ git clone https://github.com/Z3Prover/z3.git - $ cd z3 - $ python scripts/mk_make.py - $ cd build - $ make - $ sudo make install - $ cd ../.. - $ sudo pip3 install chardet==3.0.4 - $ sudo pip3 install urllib3==1.22 - -Once you have installed the packages on either Ubuntu or RedHat, use opam to install the OCaml compiler and Sail. Run as the cad user because you will be installing Sail in $RISCV. - - $ sudo su cad - $ opam init -y --disable-sandboxing - $ opam switch create ocaml-base-compiler.4.06.1 - $ opam install sail -y - -Now you can clone and compile Sail-RISCV. This will take a while. - - $ eval $(opam config env) - $ cd $RISCV - $ git clone https://github.com/riscv/sail-riscv.git - $ cd sail-riscv - $ make - $ ARCH=RV32 make - $ ARCH=RV64 make - $ exit - $ sudo su - $ export RISCV=/opt/riscv - $ ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64 - $ ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 - $ exit - -### Install riscof - -riscof is a Python library used as the RISC-V compatibility framework test an implementation such as Wally or Spike against the Sail golden reference. It will be used to compile the riscv-arch-test suite. - -It is most convenient if the sysadmin installs riscof into the server’s Python libraries: - - $ sudo pip3 install testresources - $ sudo pip3 install riscof --ignore-installed PyYAML - -However, riscof can also be installed and run locally by individual users. - -### Other Python libraries - -While a sysadmin is installing Python libraries, it's worth doing some more that will be needed by visualization scripts. - - $ sudo pip3 install matplotlib scipy sklearn adjustText lief - -### Install Verilator - -Verilator is a free Verilog simulator with a good Lint tool used to catch errors in the SystemVerilog code. It is needed to run regression. -$ sudo apt install verilator - -### Install QEMU Simulator - -QEMU is another simulator used when booting Linux in Chapter 17. You can optionally install it using the following commands. - - -The QEMU patch changes the VirtIO driver to match the Wally peripherals, and also adds print statements to log the state of the CSRs (see Section 2.5XREF). - - - $ cd $RISCV - $ git clone --recurse-submodules https://github.com/qemu/qemu - $ cd qemu - $ git checkout v6.2.0 # last version tested; newer versions might be ok - $ ./configure --target-list=riscv64-softmmu --prefix=$RISCV - $ make --jobs - $ make install - -### Cross-Compile Buildroot Linux - -Building Linux is only necessary for exploring the boot process in Chapter 17. Building and generating a trace is a time-consuming operation that could be skipped for now; you can return to this section later if you are interested in the Linux details. - -Buildroot depends on configuration files in riscv-wally, so the cad user must install Wally first according to the instructions in Section 2.2.2. However, don’t source ~/wally-riscv/setup.sh because it will set LD_LIBRARY_PATH in a way to cause make to fail on buildroot. - -To configure and build Buildroot: - - $ cd $RISCV - $ export WALLY=~/riscv-wally # make sure you haven’t sourced ~/riscv-wally/setup.sh by now - $ git clone https://github.com/buildroot/buildroot.git - $ cd buildroot - $ git checkout 2021.05 # last tested working version - $ cp -r $WALLY/linux/buildroot-config-src/wally ./board - $ cp ./board/wally/main.config .config - $ make --jobs - -To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb. - -$ source ~/riscv-wally/setup.sh -$ cd $WALLY/linux/buildroot-scripts -$ make all - -Note: When the make tasks complete, you’ll find source code in $RISCV/buildroot/output/build and the executables in $RISCV/buildroot/output/images. - -### Generate load images for linux boot - -The Questa linux boot uses preloaded bootram and ram memory. We use QEMU to generate these preloaded memory files. Files output in $RISCV/linux-testvectors - - cd cvw/linux/testvector-generation - ./genInitMem.sh - -This may require changing file permissions to the linux-testvectors directory. - -### Generate QEMU linux trace - -The linux testbench can instruction by instruction compare Wally's committed instructions against QEMU. To do this QEMU outputs a log file consisting of all instructions executed. Interrupts are handled by forcing the testbench to generate an interrupt at the same cycle as in QEMU. Generating this trace will take more than 24 hours. - - cd cvw/linux/testvector-generation - ./genTrace.sh +This section describes the open source toolchain installation. The +current version of the toolchain has been tested on Ubuntu and Red +Hat/Rocky 8. The latter is more difficult to install and Ubuntu may +be more recommended for new users. The 
wally-tool-chain-install.sh
script inside +the bin directory can be utilized to install the toolchain on Ubuntu +using sudo. ### Download Synthesis Libraries From 628759a869c47256d8db0b492240c52ad75c0d51 Mon Sep 17 00:00:00 2001 From: James Stine Date: Thu, 23 Mar 2023 09:20:35 -0500 Subject: [PATCH 189/231] Update more information inside Wally install script --- bin/wally-tool-chain-install.sh | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 181d097af..9faff81d0 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -5,6 +5,7 @@ ## Written: Ross Thompson ross1728@gmail.com ## Created: 18 January 2023 ## Modified: 22 January 2023 +## Modified: 23 March 2023 ## ## Purpose: Open source tool chain installation script ## @@ -26,18 +27,20 @@ ## and limitations under the License. ################################################################################################ +# Use /opt/riscv for installation - may require running script with sudo export RISCV="${1:-/opt/riscv}" export PATH=$PATH:$RISCV/bin set -e # break on error +# Modify accordingly for your machine NUM_THREADS=1 # for low memory machines > 16GiB #NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=16 # for >= 64GiB sudo mkdir -p $RISCV -# UPDATE / UPGRADE +# Update and Upgrade (see https://itsfoss.com/apt-update-vs-upgrade/) apt update apt upgrade @@ -51,7 +54,7 @@ then ln -sf /usr/bin/python3 /usr/bin/python fi -# gcc cross-compiler +# gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain) cd $RISCV git clone https://github.com/riscv/riscv-gnu-toolchain cd riscv-gnu-toolchain @@ -60,9 +63,8 @@ git checkout 2023.01.31 make -j ${NUM_THREADS} make install -# elf2hex +# elf2hex (https://github.com/sifive/elf2hex) cd $RISCV -#export PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH export PATH=$RISCV/bin:$PATH git clone https://github.com/sifive/elf2hex.git cd elf2hex @@ -77,7 +79,7 @@ apt-get -y install python3-pip apt-get -y install pkg-config apt-get -y install libglib2.0-dev -# QEMU +# QEMU (https://www.qemu.org/docs/master/system/target-riscv.html) cd $RISCV git clone --recurse-submodules https://github.com/qemu/qemu cd qemu @@ -85,7 +87,7 @@ cd qemu make -j ${NUM_THREADS} make install -# Spike +# Spike (https://github.com/riscv-software-src/riscv-isa-sim) cd $RISCV git clone https://github.com/riscv-software-src/riscv-isa-sim mkdir -p riscv-isa-sim/build @@ -97,7 +99,7 @@ cd ../arch_test_target/spike/device sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include -# SAIL +# Sail (https://github.com/riscv/sail-riscv) cd $RISCV apt-get install -y opam build-essential libgmp-dev z3 pkg-config zlib1g-dev git clone https://github.com/Z3Prover/z3.git From 120da12414ee5e1be49e1b0c7259e8175ed4e8e6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 08:42:40 -0700 Subject: [PATCH 190/231] README/tool installation merge --- README.md | 33 +++++++++++++++++++-------------- bin/wally-tool-chain-install.sh | 3 +-- 2 files changed, 20 insertions(+), 16 deletions(-) diff --git a/README.md b/README.md index 3c105157e..ab9566afa 100644 --- a/README.md +++ b/README.md @@ -11,15 +11,15 @@ Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by H New users may wish to do the following setup to access the server via a GUI and use a text editor. + Git started with Git configuration and authentication: B.1 (replace with your name and email) + $ git config --global user.name "Ben Bitdiddle" + $ git config --global user.email "ben_bitdiddle@wally.edu" + $ git config --global pull.rebase false Optional: Download and install x2go - A.1.1 Optional: Download and install VSCode - A.4.2 Optional: Make sure you can log into your server via x2go and via a terminal Terminal on Mac, cmd on Windows, xterm on Linux See A.1 about ssh -Y login from a terminal - Git started with Git configuration and authentication: B.1 - $ git config --global user.name ″Ben Bitdiddle″ - $ git config --global user.email ″ben_bitdiddle@wally.edu″ - $ git config --global pull.rebase false Then clone the repo, source setup, make the tests and run regression @@ -30,21 +30,20 @@ Then clone the repo, source setup, make the tests and run regression On the Linux computer where you will be working, log in -Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in. - - if [ -f ~/cvw/setup.sh ]; then - source ~/cvw/setup.sh - fi - -Clone your fork of the repo, run the setup script, and build the tests: +Clone your fork of the repo and run the setup script. $ cd $ git clone --recurse-submodules https://github.com//cvw $ git remote add upstream https://github.com/openhwgroup/cvw $ cd cvw $ source ./setup.sh - $ make - + +Add the following lines to your .bashrc or .bash_profile to run the setup script each time you log in. + + if [ -f ~/cvw/setup.sh ]; then + source ~/cvw/setup.sh + fi + Edit setup.sh and change the following lines to point to the path and license server for your Siemens Questa and Synopsys Design Compiler installation and license server. If you only have Questa, you can still simulate but cannot run logic synthesis. export MGLS_LICENSE_FILE=1717@solidworks.eng.hmc.edu # Change this to your Siemens license server @@ -52,8 +51,11 @@ Edit setup.sh and change the following lines to point to the path and license se export QUESTAPATH=/cad/mentor/questa_sim-2021.2_1/questasim/bin # Change this for your path to Questa export SNPSPATH=/cad/synopsys/SYN/bin # Change this for your path to Design Compiler -Run a regression simulation with Questa to prove everything is installed. +If the tools are not yet installed on your server, follow the Toolchain Installation instructions in the section below. +Build the tests and run a regression simulation with Questa to prove everything is installed. Building tests will take a while. + + $ make $ cd sim $ ./regression-wally (depends on having Questa installed) @@ -66,6 +68,9 @@ This section describes the open source toolchain installation. These steps shou The full installation details are involved can be be skipped using the following script, wally-tool-chain-install.sh. The script installs the open source tools to /opt/riscv by default. This can be changed by supply the path as the first argument. This script does not install buildroot (see the Detailed Tool-chain Install Guide in the following section) and does not install commercial EDA tools; Siemens Questa, Synopsys Design Compiler, or Cadence Innovus (see section Installing IDA Tools). It must be run as root or with sudo. This script is tested for Ubuntu, 20.04 and 22.04. Fedora and Red Hat can be installed in the Detailed Tool-chain Install Guide. + modify lines 34-36 of bin/wally-tool-chain-install to increase the number of threads to 8 or 16 to speed up installation + if you are on a machine with plenty of memory. + $ sudo bin/wally-tool-chain-install.sh ## Detailed Toolchain Install Guide diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 181d097af..10dbaba2d 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -140,5 +140,4 @@ curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo && sudo apt install gh -y # Other python libraries used through the book. -sudo pip3 install matplotlib scipy sklearn adjustText leif - +pip3 install matplotlib scipy scikit-learn adjustText lief From 92908be951f652d2a08da380aae1f88cf62583bc Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 08:49:20 -0700 Subject: [PATCH 191/231] README improvement --- README.md | 233 ++---------------------------------------------------- 1 file changed, 5 insertions(+), 228 deletions(-) diff --git a/README.md b/README.md index 73b9448b5..64243248d 100644 --- a/README.md +++ b/README.md @@ -61,236 +61,13 @@ Build the tests and run a regression simulation with Questa to prove everything # Toolchain Installation (Sys Admin) -<<<<<<< HEAD -This section describes the open source toolchain installation. These steps should only be done once by the system admin. - -## TL;DR Open Source Tool-chain Installation - -The full installation details are involved can be be skipped using the following script, wally-tool-chain-install.sh. -The script installs the open source tools to /opt/riscv by default. This can be changed by supply the path as the first argument. This script does not install buildroot (see the Detailed Tool-chain Install Guide in the following section) and does not install commercial EDA tools; Siemens Questa, Synopsys Design Compiler, or Cadence Innovus (see section Installing IDA Tools). It must be run as root or with sudo. This script is tested for Ubuntu, 20.04 and 22.04. Fedora and Red Hat can be installed in the Detailed Tool-chain Install Guide. - - modify lines 34-36 of bin/wally-tool-chain-install to increase the number of threads to 8 or 16 to speed up installation - if you are on a machine with plenty of memory. - - $ sudo bin/wally-tool-chain-install.sh - -## Detailed Toolchain Install Guide - -This section describes how to install the tools needed for CORE-V-Wally. Superuser privileges are necessary for many of the tools. Setting up all of the tools can be time-consuming and fussy, so Appendix D also describes an option with a Docker container. - -### Open Source Software Installation - -Compiling, assembling, and simulating RISC-V programs requires downloading and installing the following free tools: - -1. The GCC cross-compiler -2. A RISC-V simulator such as Spike, Sail, and/or QEMU -3. Spike is easy to use but doesn’t support peripherals to boot Linux -4. QEMU is faster and can boot Linux -5. Sail is presently the official golden reference for RISC-V and is used by the riscof verification suite, but runs slowly and is painful to instal - -This setup needs to be done once by the administrator - -Note: The following directions assume you have an account called cad to install shared software and files. You can substitute a different user for cad if you prefer. - -Note: Installing software in Linux is unreasonably touchy and varies with the flavor and version of your Linux distribution. Don’t be surprised if the installation directions have changed since the book was written or don’t work on your machine; you may need some ingenuity to adjust them. Browse the openhwgroup/core-v-wally repo and look at the README.md for the latest build instructions. - -### Create the $RISCV Directory - -First, set up a directory for riscv software in some place such as /opt/riscv. We will call this shared directory $RISCV. - - $ export RISCV=/opt/riscv - $ sudo mkdir $RISCV - $ sudo chown cad $RISCV - $ sudo su cad (or root, if you don’t have a cad account) - $ export RISCV=/opt/riscv - $ chmod 755 $RISCV - $ umask 0002 - $ cd $RISCV - -### Update Tools - -Ubuntu users may need to install and update various tools. Beware when cutting and pasting that some lines are long! - - $ sudo apt update - $ sudo apt upgrade - $ sudo apt install git gawk make texinfo bison flex build-essential python3 zlib1g-dev libexpat-dev autoconf device-tree-compiler ninja-build libglib2.0-dev libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog - -### Install RISC-V GCC Cross-Compiler - -To install GCC from source can take hours to compile. This configuration enables multilib to target many flavors of RISC-V. This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well. - - $ git clone https://github.com/riscv/riscv-gnu-toolchain - $ cd riscv-gnu-toolchain - $ git checkout 2023.01.31 - $ ./configure --prefix=$RISCV --with-multilib-generator="rv32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv64imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" - $ make --jobs - -Note: make --jobs will reduce compile time by compiling in parallel. However, adding this option could dramatically increase the memory utilization of your local machine. - -### Install elf2hex - -We also need the elf2hex utility to convert executable files into hexadecimal files for Verilog simulation. Install with: - - $ cd $RISCV - $ export PATH=$RISCV/bin:$PATH - $ git clone https://github.com/sifive/elf2hex.git - $ cd elf2hex - $ autoreconf -i - $ ./configure --target=riscv64-unknown-elf --prefix=$RISCV - $ make - $ make install - -Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t handle programs that start at 0x80000000. The SiFive version above is touchy to install. For example, if Python version 2.x is in your path, it won’t install correctly. Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin at the time of compilation, or elf2hex won’t work properly. - -### Install RISC-V Spike Simulator - -Spike also takes a while to install and compile, but this can be done concurrently with the GCC installation. After the build, we need to change two Makefiles to support atomic instructions . - - $ cd $RISCV - $ git clone https://github.com/riscv-software-src/riscv-isa-sim - $ mkdir riscv-isa-sim/build - $ cd riscv-isa-sim/build - $ ../configure --prefix=$RISCV - $ make --jobs - $ make install - $ cd ../arch_test_target/spike/device - $ sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include - $ sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include - -### Install Sail Simulator - -Sail is the new golden reference model for RISC-V. Sail is written in OCaml, which is an object-oriented extension of ML, which in turn is a functional programming language suited to formal verification. OCaml is installed with the opam OCcaml package manager. Sail has so many dependencies that it can be difficult to install. - -On Ubuntu, apt-get makes opam installation fairly simple. - -$ sudo apt-get install opam build-essential libgmp-dev z3 pkg-config zlib1g-dev - -If you are on RedHat/Rocky Linux 8, installation is much more difficult because packages are not available in the default package manager and some need to be built from source. - - $ sudo bash -c "sh <(curl -fsSL https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh)" - When prompted, put it in /usr/bin - $ sudo yum groupinstall 'Development Tools' - $ sudo yum -y install gmp-devel - $ sudo yum -y install zlib-devel - $ git clone https://github.com/Z3Prover/z3.git - $ cd z3 - $ python scripts/mk_make.py - $ cd build - $ make - $ sudo make install - $ cd ../.. - $ sudo pip3 install chardet==3.0.4 - $ sudo pip3 install urllib3==1.22 - -Once you have installed the packages on either Ubuntu or RedHat, use opam to install the OCaml compiler and Sail. Run as the cad user because you will be installing Sail in $RISCV. - - $ sudo su cad - $ opam init -y --disable-sandboxing - $ opam switch create ocaml-base-compiler.4.06.1 - $ opam install sail -y - -Now you can clone and compile Sail-RISCV. This will take a while. - - $ eval $(opam config env) - $ cd $RISCV - $ git clone https://github.com/riscv/sail-riscv.git - $ cd sail-riscv - $ make - $ ARCH=RV32 make - $ ARCH=RV64 make - $ exit - $ sudo su - $ export RISCV=/opt/riscv - $ ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64 - $ ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 - $ exit - -### Install riscof - -riscof is a Python library used as the RISC-V compatibility framework test an implementation such as Wally or Spike against the Sail golden reference. It will be used to compile the riscv-arch-test suite. - -It is most convenient if the sysadmin installs riscof into the server’s Python libraries: - - $ sudo pip3 install testresources - $ sudo pip3 install riscof --ignore-installed PyYAML - -However, riscof can also be installed and run locally by individual users. - -### Other Python libraries - -While a sysadmin is installing Python libraries, it's worth doing some more that will be needed by visualization scripts. - - $ sudo pip3 install matplotlib scipy sklearn adjustText lief - -### Install Verilator - -Verilator is a free Verilog simulator with a good Lint tool used to catch errors in the SystemVerilog code. It is needed to run regression. -$ sudo apt install verilator - -### Install QEMU Simulator - -QEMU is another simulator used when booting Linux in Chapter 17. You can optionally install it using the following commands. - - -The QEMU patch changes the VirtIO driver to match the Wally peripherals, and also adds print statements to log the state of the CSRs (see Section 2.5XREF). - - - $ cd $RISCV - $ git clone --recurse-submodules https://github.com/qemu/qemu - $ cd qemu - $ git checkout v6.2.0 # last version tested; newer versions might be ok - $ ./configure --target-list=riscv64-softmmu --prefix=$RISCV - $ make --jobs - $ make install - -### Cross-Compile Buildroot Linux - -Building Linux is only necessary for exploring the boot process in Chapter 17. Building and generating a trace is a time-consuming operation that could be skipped for now; you can return to this section later if you are interested in the Linux details. - -Buildroot depends on configuration files in riscv-wally, so the cad user must install Wally first according to the instructions in Section 2.2.2. However, don’t source ~/wally-riscv/setup.sh because it will set LD_LIBRARY_PATH in a way to cause make to fail on buildroot. - -To configure and build Buildroot: - - $ cd $RISCV - $ export WALLY=~/riscv-wally # make sure you haven’t sourced ~/riscv-wally/setup.sh by now - $ git clone https://github.com/buildroot/buildroot.git - $ cd buildroot - $ git checkout 2021.05 # last tested working version - $ cp -r $WALLY/linux/buildroot-config-src/wally ./board - $ cp ./board/wally/main.config .config - $ make --jobs - -To generate disassembly files and the device tree, run another make script. Note that you can expect some warnings about phandle references while running dtc on wally-virt.dtb. - -$ source ~/riscv-wally/setup.sh -$ cd $WALLY/linux/buildroot-scripts -$ make all - -Note: When the make tasks complete, you’ll find source code in $RISCV/buildroot/output/build and the executables in $RISCV/buildroot/output/images. - -### Generate load images for linux boot - -The Questa linux boot uses preloaded bootram and ram memory. We use QEMU to generate these preloaded memory files. Files output in $RISCV/linux-testvectors - - cd cvw/linux/testvector-generation - ./genInitMem.sh - -This may require changing file permissions to the linux-testvectors directory. - -### Generate QEMU linux trace - -The linux testbench can instruction by instruction compare Wally's committed instructions against QEMU. To do this QEMU outputs a log file consisting of all instructions executed. Interrupts are handled by forcing the testbench to generate an interrupt at the same cycle as in QEMU. Generating this trace will take more than 24 hours. - - cd cvw/linux/testvector-generation - ./genTrace.sh -======= This section describes the open source toolchain installation. The current version of the toolchain has been tested on Ubuntu and Red -Hat/Rocky 8. The latter is more difficult to install and Ubuntu may -be more recommended for new users. The 
wally-tool-chain-install.sh
script inside -the bin directory can be utilized to install the toolchain on Ubuntu -using sudo. ->>>>>>> a7e00e438681f72433225abccf3aef5f3c8913e7 +Hat/Rocky 8 Linux. Ubuntu works more smoothly and is recommended +unless you have a compelling need for RedHat. +Ubuntu users can install the tools by running + + $ sudo $WALLY/bin/wally-tool-chain-install.sh ### Download Synthesis Libraries From 16d9fac00474bcecee19663f12d263f01ea2ddf6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 09:05:37 -0700 Subject: [PATCH 192/231] README updates --- README.md | 4 ++++ bin/wally-tool-chain-install.sh | 9 +++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 64243248d..b93a5fc50 100644 --- a/README.md +++ b/README.md @@ -65,10 +65,14 @@ This section describes the open source toolchain installation. The current version of the toolchain has been tested on Ubuntu and Red Hat/Rocky 8 Linux. Ubuntu works more smoothly and is recommended unless you have a compelling need for RedHat. + Ubuntu users can install the tools by running $ sudo $WALLY/bin/wally-tool-chain-install.sh +See wally-tool-chain-install.sh for a detailed description of each component, +or to issue the commands one at a time to install on the command line. + ### Download Synthesis Libraries For logic synthesis, we need a synthesis tool (see Section 3.XREF) and a cell library. Clone the OSU 12-track cell library for the Skywater 130 nm process: diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 7def96852..2f058c46f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -34,18 +34,19 @@ export PATH=$PATH:$RISCV/bin set -e # break on error # Modify accordingly for your machine +# Increasing NUM_THREADS will speed up parallel compilation of the tools NUM_THREADS=1 # for low memory machines > 16GiB #NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=16 # for >= 64GiB sudo mkdir -p $RISCV -# Update and Upgrade (see https://itsfoss.com/apt-update-vs-upgrade/) +# Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/) apt update apt upgrade # INSTALL -apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev +apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev # needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3. if ! command -v python &> /dev/null @@ -55,6 +56,10 @@ then fi # gcc cross-compiler (https://github.com/riscv-collab/riscv-gnu-toolchain) +# To install GCC from source can take hours to compile. +#This configuration enables multilib to target many flavors of RISC-V. +# This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well. + cd $RISCV git clone https://github.com/riscv/riscv-gnu-toolchain cd riscv-gnu-toolchain From f4b252522eb5fd349d1adbfa47b94258cef4c45e Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 09:06:05 -0700 Subject: [PATCH 193/231] Coverage improvements --- sim/regression-wally | 8 ++++++-- tests/coverage/badinstr.S | 1 + 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/sim/regression-wally b/sim/regression-wally index d10e35655..77ab05c15 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -126,10 +126,14 @@ for test in ahbTests: grepstr="All tests ran without failures") configs.append(tc) -tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] +tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", + "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] if (coverage): # delete all but 64gc tests when running coverage configs = [] - tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv", "imperas64f", "imperas64d", "imperas64c", "imperas64i"] + tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", + "arch64zi", "wally64a", "wally64periph", "wally64priv", + "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", + "imperas64f", "imperas64d", "imperas64c", "imperas64i"] coverStr = '-coverage' else: coverStr = '' diff --git a/tests/coverage/badinstr.S b/tests/coverage/badinstr.S index 7714ab07b..174ea0aef 100644 --- a/tests/coverage/badinstr.S +++ b/tests/coverage/badinstr.S @@ -36,6 +36,7 @@ main: .word 0x00004023 // Illegal store instruction .word 0x0400003B // Illegal RW or MulDivW instruction .word 0x00007067 // Illegal JALR instruction + .word 0x00002063 // Illegal branch instruction j done From 3a9b40ff1dc9f0f21187bb38d73a4b217fa23da6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 09:31:17 -0700 Subject: [PATCH 194/231] installation script update --- bin/wally-tool-chain-install.sh | 82 ++++++++++++++++++++++----------- synthDC/ppa/ppaAnalyze.py | 2 +- 2 files changed, 56 insertions(+), 28 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 2f058c46f..4d484be60 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -44,9 +44,10 @@ sudo mkdir -p $RISCV # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/) apt update apt upgrade +apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev verilator -# INSTALL -apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev +# Other python libraries used through the book. +pip3 install matplotlib scipy scikit-learn adjustText lief # needed for Ubuntu 22.04, gcc cross compiler expects python not python2 or python3. if ! command -v python &> /dev/null @@ -59,6 +60,10 @@ fi # To install GCC from source can take hours to compile. #This configuration enables multilib to target many flavors of RISC-V. # This book is tested with GCC 12.2 (tagged 2023.01.31), but will likely work with newer versions as well. +# Note that GCC12.2 has binutils 2.39, which has a known performance bug that causes +# objdump to run 100x slower than in previous versions, causing riscof to make versy slowly. +# However GCC12.x is needed for bit manipulation instructions. There is an open issue to fix this: +# https://github.com/riscv-collab/riscv-gnu-toolchain/issues/1188 cd $RISCV git clone https://github.com/riscv/riscv-gnu-toolchain @@ -69,6 +74,12 @@ make -j ${NUM_THREADS} make install # elf2hex (https://github.com/sifive/elf2hex) +#The elf2hex utility to converts executable files into hexadecimal files for Verilog simulation. +# Note: The exe2hex utility that comes with Spike doesn’t work for our purposes because it doesn’t +# handle programs that start at 0x80000000. The SiFive version above is touchy to install. +# For example, if Python version 2.x is in your path, it won’t install correctly. +# Also, be sure riscv64-unknown-elf-objcopy shows up in your path in $RISCV/riscv-gnu-toolchain/bin +# at the time of compilation, or elf2hex won’t work properly. cd $RISCV export PATH=$RISCV/bin:$PATH git clone https://github.com/sifive/elf2hex.git @@ -78,11 +89,6 @@ autoreconf -i make make install -# Update Python3.6 for QEMU -apt-get -y update -apt-get -y install python3-pip -apt-get -y install pkg-config -apt-get -y install libglib2.0-dev # QEMU (https://www.qemu.org/docs/master/system/target-riscv.html) cd $RISCV @@ -105,17 +111,23 @@ sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include # Sail (https://github.com/riscv/sail-riscv) -cd $RISCV -apt-get install -y opam build-essential libgmp-dev z3 pkg-config zlib1g-dev -git clone https://github.com/Z3Prover/z3.git -cd z3 -python scripts/mk_make.py -cd build -make -j ${NUM_THREADS} -make install -cd ../.. -pip3 install chardet==3.0.4 -pip3 install urllib3==1.22 +#Sail is the new golden reference model for RISC-V. Sail is written in OCaml, which +# is an object-oriented extension of ML, which in turn is a functional programming +#language suited to formal verification. OCaml is installed with the opam OCcaml +#package manager. Sail has so many dependencies that it can be difficult to install. +# This script forks for Ubuntu. + +#cd $RISCV +#git clone https://github.com/Z3Prover/z3.git +#cd z3 +#python scripts/mk_make.py +#cd build +#make -j ${NUM_THREADS} +#make install +#cd ../.. +#pip3 install chardet==3.0.4 +#pip3 install urllib3==1.22 + opam init -y --disable-sandboxing opam switch create ocaml-base-compiler.4.06.1 opam install sail -y @@ -135,16 +147,32 @@ ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 pip3 install testresources pip3 install riscof --ignore-installed PyYAML +# RedHat / Rocky 8 Linux doesn't have the packages in the default pacakge +# manager. Instead, build them form source using: +# $ sudo bash -c "sh <(curl -fsSL https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh)" +# When prompted, put it in /usr/bin +# $ sudo yum groupinstall 'Development Tools' +# $ sudo yum -y install gmp-devel +# $ sudo yum -y install zlib-devel +# $ git clone https://github.com/Z3Prover/z3.git +# $ cd z3 +# $ python scripts/mk_make.py +# $ cd build +# $ make +# $ sudo make install +# $ cd ../.. +# $ sudo pip3 install chardet==3.0.4 +# $ sudo pip3 install urllib3==1.22 + + # Verilator -apt install -y verilator +#apt install -y verilator # install github cli (gh) -type -p curl >/dev/null || sudo apt install curl -y -curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo dd of=/usr/share/keyrings/githubcli-archive-keyring.gpg \ -&& sudo chmod go+r /usr/share/keyrings/githubcli-archive-keyring.gpg \ -&& echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \ -&& sudo apt update \ -&& sudo apt install gh -y +#type -p curl >/dev/null || sudo apt install curl -y +#curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo dd of=/usr/share/keyrings/githubcli-archive-keyring.gpg \ +#&& sudo chmod go+r /usr/share/keyrings/githubcli-archive-keyring.gpg \ +#&& echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \ +#&& sudo apt update \ +#&& sudo apt install gh -y -# Other python libraries used through the book. -pip3 install matplotlib scipy scikit-learn adjustText lief diff --git a/synthDC/ppa/ppaAnalyze.py b/synthDC/ppa/ppaAnalyze.py index 2dce62ae5..03758cdf6 100755 --- a/synthDC/ppa/ppaAnalyze.py +++ b/synthDC/ppa/ppaAnalyze.py @@ -11,7 +11,7 @@ import matplotlib.lines as lines import matplotlib as mpl import numpy as np from collections import namedtuple -import sklearn.metrics as skm +import sklearn.metrics as skm # depricated, will need to replace with scikit-learn import os def synthsfromcsv(filename): From 67186c44982b9251b98668df03ec23a9b53d4f18 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 09:33:56 -0700 Subject: [PATCH 195/231] install docs --- bin/wally-tool-chain-install.sh | 40 ++++++--------------------------- 1 file changed, 7 insertions(+), 33 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 4d484be60..dfe72896f 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -99,6 +99,8 @@ make -j ${NUM_THREADS} make install # Spike (https://github.com/riscv-software-src/riscv-isa-sim) +# Spike also takes a while to install and compile, but this can be done concurrently +#with the GCC installation. After the build, we need to change two Makefiles to support atomic instructions. cd $RISCV git clone https://github.com/riscv-software-src/riscv-isa-sim mkdir -p riscv-isa-sim/build @@ -111,12 +113,13 @@ sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include # Sail (https://github.com/riscv/sail-riscv) -#Sail is the new golden reference model for RISC-V. Sail is written in OCaml, which +# Sail is the new golden reference model for RISC-V. Sail is written in OCaml, which # is an object-oriented extension of ML, which in turn is a functional programming -#language suited to formal verification. OCaml is installed with the opam OCcaml -#package manager. Sail has so many dependencies that it can be difficult to install. -# This script forks for Ubuntu. +# language suited to formal verification. OCaml is installed with the opam OCcaml +# package manager. Sail has so many dependencies that it can be difficult to install. +# This script works for Ubuntu. +# Do these commands only for RedHat / Rocky 8 to build from source. #cd $RISCV #git clone https://github.com/Z3Prover/z3.git #cd z3 @@ -147,32 +150,3 @@ ln -sf $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32 pip3 install testresources pip3 install riscof --ignore-installed PyYAML -# RedHat / Rocky 8 Linux doesn't have the packages in the default pacakge -# manager. Instead, build them form source using: -# $ sudo bash -c "sh <(curl -fsSL https://raw.githubusercontent.com/ocaml/opam/master/shell/install.sh)" -# When prompted, put it in /usr/bin -# $ sudo yum groupinstall 'Development Tools' -# $ sudo yum -y install gmp-devel -# $ sudo yum -y install zlib-devel -# $ git clone https://github.com/Z3Prover/z3.git -# $ cd z3 -# $ python scripts/mk_make.py -# $ cd build -# $ make -# $ sudo make install -# $ cd ../.. -# $ sudo pip3 install chardet==3.0.4 -# $ sudo pip3 install urllib3==1.22 - - -# Verilator -#apt install -y verilator - -# install github cli (gh) -#type -p curl >/dev/null || sudo apt install curl -y -#curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo dd of=/usr/share/keyrings/githubcli-archive-keyring.gpg \ -#&& sudo chmod go+r /usr/share/keyrings/githubcli-archive-keyring.gpg \ -#&& echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \ -#&& sudo apt update \ -#&& sudo apt install gh -y - From 533972d178a84840401d0cc2a657b232946f2c4a Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 09:36:50 -0700 Subject: [PATCH 196/231] Increased NumThreads to 0 --- bin/wally-tool-chain-install.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index dfe72896f..798fe51bb 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -35,15 +35,15 @@ set -e # break on error # Modify accordingly for your machine # Increasing NUM_THREADS will speed up parallel compilation of the tools -NUM_THREADS=1 # for low memory machines > 16GiB +NUM_THREADS=2 # for low memory machines > 16GiB #NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=16 # for >= 64GiB sudo mkdir -p $RISCV # Update and Upgrade tools (see https://itsfoss.com/apt-update-vs-upgrade/) -apt update -apt upgrade +apt update -y +apt upgrade -y apt install -y git gawk make texinfo bison flex build-essential python3 libz-dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-dev libglib2.0-dev python3-pip pkg-config opam z3 zlib1g-dev verilator # Other python libraries used through the book. From 60d807f1b080aad030a2902adeb1bfd795fb6896 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 09:39:03 -0700 Subject: [PATCH 197/231] Removed 130 nm library and cli from README --- README.md | 22 ---------------------- 1 file changed, 22 deletions(-) diff --git a/README.md b/README.md index b93a5fc50..a03625217 100644 --- a/README.md +++ b/README.md @@ -72,28 +72,6 @@ Ubuntu users can install the tools by running See wally-tool-chain-install.sh for a detailed description of each component, or to issue the commands one at a time to install on the command line. - -### Download Synthesis Libraries - -For logic synthesis, we need a synthesis tool (see Section 3.XREF) and a cell library. Clone the OSU 12-track cell library for the Skywater 130 nm process: - - $ cd $RISCV - $ mkdir cad - $ mkdir cad/lib - $ cd cad/lib - $ git clone https://foss-eda-tools.googlesource.com/skywater-pdk/libs/sky130_osu_sc_t12 - -### Install github cli - -The github cli allows users to directly issue pull requests from their fork back to openhwgroup/cvw using the command line. - - $ type -p curl >/dev/null || sudo apt install curl -y - $ curl -fsSL https://cli.github.com/packages/githubcli-archive-keyring.gpg | sudo dd of=/usr/share/keyrings/githubcli-archive-keyring.gpg \ && sudo chmod go+r /usr/share/keyrings/githubcli-archive-keyring.gpg \ - && echo "deb [arch=$(dpkg --print-architecture) signed-by=/usr/share/keyrings/githubcli-archive-keyring.gpg] https://cli.github.com/packages stable main" | sudo tee /etc/apt/sources.list.d/github-cli.list > /dev/null \ - && sudo apt update \ - && sudo apt install gh -y - - ## Installing EDA Tools Electronic Design Automation (EDA) tools are vital to implementations of System on Chip architectures as well as validating different designs. Open-source and commercial tools exist for multiple strategies and although the one can spend a lifetime using combinations of different tools, only a small subset of tools is utilized for this text. The tools are chosen because of their ease in access as well as their repeatability for accomplishing many of the tasks utilized to design Wally. It is anticipated that additional tools may be documented later after this is text is published to improve use and access. From 121d1cea62edb765a3a83483e0729b48a7b892ba Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 10:55:32 -0700 Subject: [PATCH 198/231] Added csrwrites.S test case for privileged tests --- .gitignore | 1 - sim/regression-wally | 6 +- src/ieu/bmu/bmuctrl.sv | 174 ++++++++++++++++--------------------- src/privileged/csrs.sv | 6 +- testbench/tests.vh | 3 +- tests/coverage/Makefile | 5 +- tests/coverage/csrwrites.S | 35 ++++++++ 7 files changed, 123 insertions(+), 107 deletions(-) create mode 100644 tests/coverage/csrwrites.S diff --git a/.gitignore b/.gitignore index 1f8e8b158..6e9920603 100644 --- a/.gitignore +++ b/.gitignore @@ -111,6 +111,5 @@ sim/imperas.log sim/results-error/ sim/test1.rep sim/vsim.log -tests/coverage/*.S tests/coverage/*.elf *.elf.memfile \ No newline at end of file diff --git a/sim/regression-wally b/sim/regression-wally index 77ab05c15..122b04b51 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -130,10 +130,14 @@ tests64gc = ["arch64f", "arch64d", "arch64i", "arch64zba", "arch64zbb", "arch64z "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv"] if (coverage): # delete all but 64gc tests when running coverage configs = [] - tests64gc = ["arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", + tests64gc = ["coverage64gc", "arch64i", "arch64priv", "arch64c", "arch64m", "arch64zi", "wally64a", "wally64periph", "wally64priv", "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", "imperas64f", "imperas64d", "imperas64c", "imperas64i"] +# tests64gc = ["coverage64gc", "arch64f", "arch64d", "arch64i", "arch64priv", "arch64c", "arch64m", +# "arch64zi", "wally64a", "wally64periph", "wally64priv", +# "arch64zba", "arch64zbb", "arch64zbc", "arch64zbs", +# "imperas64f", "imperas64d", "imperas64c", "imperas64i"] coverStr = '-coverage' else: coverStr = '' diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index ae401ef88..645e711cc 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -76,106 +76,84 @@ module bmuctrl( // Main Instruction Decoder always_comb begin - BMUControlsD = {Funct3D, `BMUCTRLWSUB3'b00_000_0_0_0_0_0_0_0_0_1}; // default: Illegal instruction - casez({OpD, Funct7D, Funct3D}) // ALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD - // ZBS - 17'b0010011_0100100_001: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri - 17'b0010011_0100101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) - 17'b0010011_0100100_101: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti - 17'b0010011_0100101_101: if (`XLEN == 64 & `ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) - 17'b0010011_0110100_001: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi - 17'b0010011_0110101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) - 17'b0010011_0010100_001: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti - 17'b0010011_0010101_001: if (`XLEN == 64 & `ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64) - 17'b0110011_0100100_001: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr - 17'b0110011_0100100_101: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext - 17'b0110011_0110100_001: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv - 17'b0110011_0010100_001: if (`ZBS_SUPPORTED) - BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset - 17'b0110011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll - 17'b0010011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli - 17'b0111011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw - 17'b0011011_0?0000?_?01: if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw + BMUControlsD = {Funct3D, `BMUCTRLWSUB3'b00_000_0_0_0_0_0_0_0_0_1}; // default: Illegal instruction + if (`ZBA_SUPPORTED) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add + 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add + 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add + endcase + if (`ZBA_SUPPORTED & `XLEN==64) + casez({OpD, Funct7D, Funct3D}) + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw + endcase + if (`ZBB_SUPPORTED) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol + 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror + 17'b0010011_0110000_001: if ((Rs2D[4:1] == 4'b0010)) + BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction + else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])) + BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction + 17'b0110011_0000100_100: if (`XLEN == 32) + BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) + 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn + 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn + 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor + 17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & (Rs2D == 5'b11000)) + BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 + 17'b0010011_0010100_101: if (Rs2D[4:0] == 5'b00111) + BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b + 17'b0110011_0000101_110: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // max + 17'b0110011_0000101_111: BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // maxu + 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min + 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu + endcase + if (`ZBB_SUPPORTED & `XLEN==64) + casez({OpD, Funct7D, Funct3D}) + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw + 17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) + 17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw + 17'b0011011_0110000_001: if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])) + BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction + 17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) + endcase + if (`ZBC_SUPPORTED) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction + endcase + if (`ZBS_SUPPORTED) // ZBS + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti + 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr + 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext + 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv + 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset + endcase + if (`ZBS_SUPPORTED & `XLEN==64) // ZBS 64-bit + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_0100101_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) + 17'b0010011_0100101_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) + 17'b0010011_0110101_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) + 17'b0010011_0010101_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64) + endcase + if (`ZBB_SUPPORTED | `ZBS_SUPPORTED) // rv32i/64i shift instructions need certain BMU shifter control when BMU shifter is used + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll + 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli + 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw + 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw + endcase // ZBC - 17'b0110011_0000101_0??: if (`ZBC_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction - // ZBA - 17'b0110011_0010000_010: if (`ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add - 17'b0110011_0010000_100: if (`ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add - 17'b0110011_0010000_110: if (`ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add - 17'b0111011_0010000_010: if (`XLEN == 64 & `ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw - 17'b0111011_0010000_100: if (`XLEN == 64 & `ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw - 17'b0111011_0010000_110: if (`XLEN == 64 & `ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw - 17'b0111011_0000100_000: if (`XLEN == 64 & `ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw - 17'b0011011_000010?_001: if (`XLEN == 64 & `ZBA_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw - // ZBB - 17'b0110011_0110000_001: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol - 17'b0111011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw - 17'b0110011_0110000_101: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror - 17'b0111011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw - //17'b0010011_0110000_101: if (`ZBB_SUPPORTED) - // BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) - 17'b0010011_011000?_101: if ((`XLEN == 64 | ~Funct7D[0]) & `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) - 17'b0011011_0110000_101: if (`XLEN == 64 & `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw - 17'b0010011_0110000_001: if (`ZBB_SUPPORTED & (Rs2D[4:1] == 4'b0010)) - BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction - else if (`ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))) - BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction - 17'b0011011_0110000_001: if (`XLEN == 64 & `ZBB_SUPPORTED & ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0]))) - BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction - 17'b0111011_0000100_100: if (`XLEN == 64 & `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) - 17'b0110011_0000100_100: if (`XLEN == 32 & `ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) - 17'b0110011_0100000_111: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn - 17'b0110011_0100000_110: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn - 17'b0110011_0100000_100: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor - 17'b0010011_011010?_101: if ((`XLEN == 32 ^ Funct7D[0]) & `ZBB_SUPPORTED & (Rs2D == 5'b11000)) - BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // rev8 - 17'b0010011_0010100_101: if (`ZBB_SUPPORTED & Rs2D[4:0] == 5'b00111) - BMUControlsD = `BMUCTRLW'b000_10_010_1_1_0_1_0_0_0_0_0; // orc.b - 17'b0110011_0000101_110: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // max - 17'b0110011_0000101_111: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_111_1_0_0_1_0_0_0_0_0; // maxu - 17'b0110011_0000101_100: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min - 17'b0110011_0000101_101: if (`ZBB_SUPPORTED) - BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu - endcase end // Unpack Control Signals diff --git a/src/privileged/csrs.sv b/src/privileged/csrs.sv index 1a5906653..b13b620b0 100644 --- a/src/privileged/csrs.sv +++ b/src/privileged/csrs.sv @@ -100,10 +100,10 @@ module csrs #(parameter else assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported flopenr #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, CSRWriteValM[31:0], SCOUNTEREN_REGW); - if (`SSTC_SUPPORTED) begin - if (`XLEN == 64) + if (`SSTC_SUPPORTED) begin : sstc + if (`XLEN == 64) begin : sstc64 flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 64'hFFFFFFFFFFFFFFFF, STIMECMP_REGW); - else begin + end else begin : sstc32 flopenl #(`XLEN) STIMECMPreg(clk, reset, WriteSTIMECMPM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[31:0]); flopenl #(`XLEN) STIMECMPHreg(clk, reset, WriteSTIMECMPHM, CSRWriteValM, 32'hFFFFFFFF, STIMECMP_REGW[63:32]); end diff --git a/testbench/tests.vh b/testbench/tests.vh index 67152fe7c..83729f964 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -44,7 +44,8 @@ string tvpaths[] = '{ string coverage64gc[] = '{ `COVERAGE, - "badinstr" + "badinstr", + "csrwrites" }; string coremark[] = '{ diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index 8742dee63..d3686f8eb 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -15,12 +15,11 @@ all: $(OBJECTS) %.elf.objdump: %.elf +# Change many things if bit width isn't 64 %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile - # Change many things if bit width isn't 64 - echo $@ riscv64-unknown-elf-gcc -g -o $@ -march=rv64gc -mabi=lp64 -mcmodel=medany \ -nostartfiles -T../../examples/link/link.ld $< - riscv64-unknown-elf-objdump -D $@ > $@.objdump + riscv64-unknown-elf-objdump -S $@ > $@.objdump riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile extractFunctionRadix.sh $@.objdump diff --git a/tests/coverage/csrwrites.S b/tests/coverage/csrwrites.S new file mode 100644 index 000000000..76e310e5f --- /dev/null +++ b/tests/coverage/csrwrites.S @@ -0,0 +1,35 @@ +/////////////////////////////////////////// +// csrwrites.S +// +// Written: David_Harris@hmc.edu 21 March 2023 +// +// Purpose: Test writes to CSRs +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate +#include "WALLY-init-lib.h" + +main: + csrrw t0, stimecmp, t0 + csrrw t0, satp, t0 + csrrw t0, stvec, t0 + csrrw t0, sscratch, t0 + + j done From 519a0452a55db7254fbbbd6397494a3faec742e9 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 23 Mar 2023 14:02:28 -0700 Subject: [PATCH 199/231] started bitmanip alu modularization --- src/ieu/bmu/bitmanipalu.sv | 131 +++++++++++++++++++++++++++++++++++++ 1 file changed, 131 insertions(+) create mode 100644 src/ieu/bmu/bitmanipalu.sv diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv new file mode 100644 index 000000000..eea174d3e --- /dev/null +++ b/src/ieu/bmu/bitmanipalu.sv @@ -0,0 +1,131 @@ +/////////////////////////////////////////// +// bitmanipalu.sv +// +// Written: Kevin Kim +// Created: 23 March 2023 +// Modified: 23 March 2023 +// +// Purpose: RISC-V Arithmetic/Logic Unit Bit-Manipulation Extension +// +// Documentation: RISC-V System on Chip Design Chapter 15 +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "wally-config.vh" + +module alu #(parameter WIDTH=32) ( + input logic [WIDTH-1:0] A, B, // Operands + input logic [2:0] ALUControl, // With Funct3, indicates operation to perform + input logic [2:0] ALUSelect, // ALU mux select signal + input logic [1:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction + input logic [2:0] ZBBSelect, // ZBB mux select signal + input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect + input logic [1:0] CompFlags, // Comparator flags + input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage + output logic [WIDTH-1:0] Result, // ALU result + output logic [WIDTH-1:0] Sum); // Sum of operands + + // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. + // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. + logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult,ALUResult; // Intermediate Signals + logic [WIDTH-1:0] ZBCResult, ZBBResult; // Result of ZBB, ZBC + logic [WIDTH-1:0] MaskB; // BitMask of B + logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux + logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux + logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux + logic [WIDTH-1:0] RevA; // Bit-reversed A + logic Carry, Neg; // Flags: carry out, negative + logic LT, LTU; // Less than, Less than unsigned + logic W64; // RV64 W-type instruction + logic SubArith; // Performing subtraction or arithmetic right shift + logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops + logic Asign, Bsign; // Sign bits of A, B + logic shSignA; + logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter + logic [1:0] shASelect; // select signal for shifter source generation mux + logic Rotate; // Indicates if it is Rotate instruction + logic Mask; // Indicates if it is ZBS instruction + logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction + logic [1:0] PreShiftAmt; // Amount to Pre-Shift A + + // Extract control signals from ALUControl. + assign {W64, SubArith, ALUOp} = ALUControl; + + // Extract control signals from bitmanip ALUControl. + assign {Rotate, Mask, PreShift} = BALUControl; + + // Pack control signals into shifter select + assign shASelect = {W64,SubArith}; + + assign PreShiftAmt = Funct3[2:1] & {2{PreShift}}; + + if (`ZBS_SUPPORTED) begin: zbsdec + decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); + mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB); + end else assign CondMaskB = B; + + + // shifter rotate source select mux + if (`ZBB_SUPPORTED & WIDTH == 64) begin + mux2 #(WIDTH) rotmux(A, {A[31:0], A[31:0]}, W64, rotA); + end else assign rotA = A; + + if (`ZBA_SUPPORTED) begin: zbapreshift + // Pre-Shift + assign CondShiftA = CondExtA << (PreShiftAmt); + end else assign CondShiftA = A; + + // Select appropriate ALU Result + if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) begin + always_comb + if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) + else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect + 3'b000: FullResult = Sum; // add or sub + 3'b001: FullResult = Shift; // sll, sra, or srl + 3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt + 3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu + 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv + 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}};// bext + 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset + 3'b111: FullResult = A & CondMaskInvB; // and, bclr + endcase + end + + if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse + bitreverse #(WIDTH) brA(.A, .RevA); + end + + if (`ZBC_SUPPORTED) begin: zbc + zbc #(WIDTH) ZBC(.A, .RevA, .B, .Funct3, .ZBCResult); + end else assign ZBCResult = 0; + + if (`ZBB_SUPPORTED) begin: zbb + zbb #(WIDTH) ZBB(.A, .RevA, .B, .ALUResult, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult); + end else assign ZBBResult = 0; + + // Final Result B instruction select mux +always_comb + case (BSelect) + // 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC + 2'b00: Result = ALUResult; + 2'b01: Result = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word. + 2'b10: Result = ZBBResult; + 2'b11: Result = ZBCResult; + endcase +endmodule \ No newline at end of file From 4e1bf6fbe045e111368ba92728ade4600e6421c1 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 14:24:41 -0700 Subject: [PATCH 200/231] Improved IEU and bitmanip test coverage --- src/generic/lzc.sv | 2 +- src/ieu/bmu/bmuctrl.sv | 77 +++++++++++++++------------- testbench/tests.vh | 2 +- tests/coverage/Makefile | 2 +- tests/coverage/{badinstr.S => ieu.S} | 27 ++++++++-- 5 files changed, 69 insertions(+), 41 deletions(-) rename tests/coverage/{badinstr.S => ieu.S} (66%) diff --git a/src/generic/lzc.sv b/src/generic/lzc.sv index ecfd6796a..9b7c841b2 100644 --- a/src/generic/lzc.sv +++ b/src/generic/lzc.sv @@ -32,7 +32,7 @@ module lzc #(parameter WIDTH = 1) ( always_comb begin i = 0; - while (~num[WIDTH-1-i] & (i < WIDTH)) i = i+1; // search for leading one + while ((i < WIDTH) & ~num[WIDTH-1-i]) i = i+1; // search for leading one ZeroCnt = i[$clog2(WIDTH+1)-1:0]; end endmodule diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 645e711cc..24dd22ce0 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -78,21 +78,22 @@ module bmuctrl( always_comb begin // ALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD BMUControlsD = {Funct3D, `BMUCTRLWSUB3'b00_000_0_0_0_0_0_0_0_0_1}; // default: Illegal instruction - if (`ZBA_SUPPORTED) + if (`ZBA_SUPPORTED) begin casez({OpD, Funct7D, Funct3D}) 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add 17'b0110011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh2add 17'b0110011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh3add endcase - if (`ZBA_SUPPORTED & `XLEN==64) - casez({OpD, Funct7D, Funct3D}) - 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw - 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw - 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw - 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw - 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw - endcase - if (`ZBB_SUPPORTED) + if (`XLEN==64) + casez({OpD, Funct7D, Funct3D}) + 17'b0111011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh1add.uw + 17'b0111011_0010000_100: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh2add.uw + 17'b0111011_0010000_110: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_1_0; // sh3add.uw + 17'b0111011_0000100_000: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_1_1_0_0_0_0_0; // add.uw + 17'b0011011_000010?_001: BMUControlsD = `BMUCTRLW'b001_01_000_1_1_1_1_0_0_0_0_0; // slli.uw + endcase + end + if (`ZBB_SUPPORTED) begin casez({OpD, Funct7D, Funct3D}) 17'b0110011_0110000_001: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // rol 17'b0110011_0110000_101: BMUControlsD = `BMUCTRLW'b001_01_111_1_0_0_1_0_1_0_0_0; // ror @@ -100,8 +101,6 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // sign extend instruction else if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])) BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction - 17'b0110011_0000100_100: if (`XLEN == 32) - BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor @@ -114,38 +113,47 @@ module bmuctrl( 17'b0110011_0000101_100: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // min 17'b0110011_0000101_101: BMUControlsD = `BMUCTRLW'b000_10_011_1_0_0_1_0_0_0_0_0; // minu endcase - if (`ZBB_SUPPORTED & `XLEN==64) - casez({OpD, Funct7D, Funct3D}) - 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw - 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw - 17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) - 17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw - 17'b0011011_0110000_001: if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])) - BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction - 17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) - endcase + if (`XLEN==32) + casez({OpD, Funct7D, Funct3D}) + 17'b0110011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) + endcase + else if (`XLEN==64) + casez({OpD, Funct7D, Funct3D}) + 17'b0111011_0000100_100: BMUControlsD = `BMUCTRLW'b000_10_001_1_0_0_1_0_0_0_0_0; // zexth (rv64) + 17'b0111011_0110000_001: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rolw + 17'b0111011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_0_1_1_0_1_0_0_0; // rorw + 17'b0010011_011000?_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv64) + 17'b0011011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_1_1_0_1_0_0_0; // roriw + 17'b0011011_0110000_001: if ((Rs2D[4:2]==3'b000) & ~(Rs2D[1] & Rs2D[0])) + BMUControlsD = `BMUCTRLW'b000_10_000_1_1_1_1_0_0_0_0_0; // count word instruction + endcase + end if (`ZBC_SUPPORTED) casez({OpD, Funct7D, Funct3D}) 17'b0110011_0000101_0??: BMUControlsD = `BMUCTRLW'b000_11_000_1_0_0_1_0_0_0_0_0; // ZBC instruction endcase - if (`ZBS_SUPPORTED) // ZBS + if (`ZBS_SUPPORTED) begin // ZBS casez({OpD, Funct7D, Funct3D}) - 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri - 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti - 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi - 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti 17'b0110011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_0_0_1_1_0_1_0_0; // bclr 17'b0110011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_0_0_1_1_0_1_0_0; // bext 17'b0110011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_0_0_1_0_0_1_0_0; // binv 17'b0110011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_0_0_1_0_0_1_0_0; // bset endcase - if (`ZBS_SUPPORTED & `XLEN==64) // ZBS 64-bit - casez({OpD, Funct7D, Funct3D}) - 17'b0010011_0100101_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) - 17'b0010011_0100101_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) - 17'b0010011_0110101_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) - 17'b0010011_0010101_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64) - endcase + if (`XLEN==32) // ZBS 64-bit + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_0100100_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri + 17'b0010011_0100100_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti + 17'b0010011_0110100_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi + 17'b0010011_0010100_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti + endcase + else if (`XLEN==64) // ZBS 64-bit + casez({OpD, Funct7D, Funct3D}) + 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_01_000_1_1_0_1_1_0_1_0_0; // bclri (rv64) + 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_01_000_1_1_0_1_1_0_1_0_0; // bexti (rv64) + 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_01_000_1_1_0_1_0_0_1_0_0; // binvi (rv64) + 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64) + endcase + end if (`ZBB_SUPPORTED | `ZBS_SUPPORTED) // rv32i/64i shift instructions need certain BMU shifter control when BMU shifter is used casez({OpD, Funct7D, Funct3D}) 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll @@ -153,7 +161,6 @@ module bmuctrl( 17'b0111011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_1_1_0_0_0_0_0; // sraw, srlw, sllw 17'b0011011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_1_1_0_0_0_0_0; // sraiw, srliw, slliw endcase - // ZBC end // Unpack Control Signals diff --git a/testbench/tests.vh b/testbench/tests.vh index 83729f964..f5e02290b 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -44,7 +44,7 @@ string tvpaths[] = '{ string coverage64gc[] = '{ `COVERAGE, - "badinstr", + "ieu", "csrwrites" }; diff --git a/tests/coverage/Makefile b/tests/coverage/Makefile index d3686f8eb..7d4552af2 100644 --- a/tests/coverage/Makefile +++ b/tests/coverage/Makefile @@ -17,7 +17,7 @@ all: $(OBJECTS) # Change many things if bit width isn't 64 %.elf: $(SRCDIR)/%.$(SEXT) WALLY-init-lib.h Makefile - riscv64-unknown-elf-gcc -g -o $@ -march=rv64gc -mabi=lp64 -mcmodel=medany \ + riscv64-unknown-elf-gcc -g -o $@ -march=rv64gc_zba_zbb_zbc_zbs -mabi=lp64 -mcmodel=medany \ -nostartfiles -T../../examples/link/link.ld $< riscv64-unknown-elf-objdump -S $@ > $@.objdump riscv64-unknown-elf-elf2hex --bit-width 64 --input $@ --output $@.memfile diff --git a/tests/coverage/badinstr.S b/tests/coverage/ieu.S similarity index 66% rename from tests/coverage/badinstr.S rename to tests/coverage/ieu.S index 174ea0aef..8467f2d4b 100644 --- a/tests/coverage/badinstr.S +++ b/tests/coverage/ieu.S @@ -1,9 +1,9 @@ /////////////////////////////////////////// -// badinstr.S +// ieu.S // // Written: David_Harris@hmc.edu 21 March 2023 // -// Purpose: Test illegal instruction opcodes +// Purpose: Test coverage for IEU // // A component of the CORE-V-WALLY configurable RISC-V project. // @@ -27,7 +27,19 @@ #include "WALLY-init-lib.h" main: - .word 0x00000033 // legal R-type instruction + + # Test clz with all bits being 0 + li t0, 0 + clz t1, t0 + li t0, -1 + clz t1, t0 + + # Test forwarding from store conditional + lr.w t0, 0(a0) + sc.w t0, a1, 0(a0) + addi t0, t0, 1 + + # Test illegal instructions are detected .word 0x80000033 // illegal R-type instruction .word 0x00007003 // illegal Load instruction .word 0x80005013 // illegal I-type instruction: srli: op = 0010011, funct3 = 101, funct7 = 1000000 @@ -37,6 +49,15 @@ main: .word 0x0400003B // Illegal RW or MulDivW instruction .word 0x00007067 // Illegal JALR instruction .word 0x00002063 // Illegal branch instruction + .word 0x60F01013 // Illegal BMU sign extend / count instruction + .word 0x60801013 // Illegal BMU sign extend / count instruction + .word 0x60301013 // Illegal BMU sign extend / count instruction + .word 0x6BF05013 // Illegal BMU similar to rev8 + .word 0x69805013 // Illegal BMU similar to rev8 + .word 0x28F05013 // Illegal BMU similar to or.c + .word 0x60F0101B // Illegal BMU similar to count word + .word 0x6080101B // Illegal BMU similar to count word + .word 0x6030101B // Illegal BMU similar to count word j done From 51d691215f3675426845624fe1c129d5687c598a Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 23 Mar 2023 16:02:38 -0700 Subject: [PATCH 201/231] more progress on bitmanip alu modularization --- src/ieu/alu.sv | 38 ++++++++++---------------------- src/ieu/bmu/bitmanipalu.sv | 45 ++++++++++---------------------------- 2 files changed, 23 insertions(+), 60 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 7e38b1a65..7b1b2586d 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -116,32 +116,18 @@ module alu #(parameter WIDTH=32) ( assign LTU = ~Carry; // Select appropriate ALU Result - if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) begin - always_comb - if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) - else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect - 3'b000: FullResult = Sum; // add or sub - 3'b001: FullResult = Shift; // sll, sra, or srl - 3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt - 3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu - 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv - 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}};// bext - 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset - 3'b111: FullResult = A & CondMaskInvB; // and, bclr - endcase - end - else begin - always_comb - if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) - else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect - 3'b000: FullResult = Sum; // add or sub - 3'b?01: FullResult = Shift; // sll, sra, or srl - 3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt - 3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu - 3'b100: FullResult = A ^ B; // xor - 3'b110: FullResult = A | B; // or - 3'b111: FullResult = A & B; // and - endcase + always_comb begin + if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) + else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect + 3'b000: FullResult = Sum; // add or sub + 3'b001: FullResult = Shift; // sll, sra, or srl + 3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt + 3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu + 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv + 3'b101: FullResult = (`ZBS_SUPPORTED | `ZBB_SUPPORTED) ? {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}} : Shift;// bext + 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset + 3'b111: FullResult = A & CondMaskInvB; // and, bclr + endcase end if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index eea174d3e..eb4b92bc4 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" -module alu #(parameter WIDTH=32) ( +module bitmanipalu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform input logic [2:0] ALUSelect, // ALU mux select signal @@ -38,16 +38,17 @@ module alu #(parameter WIDTH=32) ( input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect input logic [1:0] CompFlags, // Comparator flags input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage + output logic [WIDTH-1:0] CondMaskB, + output logic [WIDTH-1:0] CondShiftA, + output logic [WIDTH-1:0] rotA, output logic [WIDTH-1:0] Result, // ALU result - output logic [WIDTH-1:0] Sum); // Sum of operands + output logic [WIDTH-1:0] ZBBResult, // ZBB result + output logic [WIDTH-1:0] ZBCResult); // ZBC result // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult,ALUResult; // Intermediate Signals - logic [WIDTH-1:0] ZBCResult, ZBBResult; // Result of ZBB, ZBC logic [WIDTH-1:0] MaskB; // BitMask of B - logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux - logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux logic [WIDTH-1:0] RevA; // Bit-reversed A logic Carry, Neg; // Flags: carry out, negative @@ -57,7 +58,6 @@ module alu #(parameter WIDTH=32) ( logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B logic shSignA; - logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter logic [1:0] shASelect; // select signal for shifter source generation mux logic Rotate; // Indicates if it is Rotate instruction logic Mask; // Indicates if it is ZBS instruction @@ -73,8 +73,6 @@ module alu #(parameter WIDTH=32) ( // Pack control signals into shifter select assign shASelect = {W64,SubArith}; - assign PreShiftAmt = Funct3[2:1] & {2{PreShift}}; - if (`ZBS_SUPPORTED) begin: zbsdec decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB); @@ -87,24 +85,12 @@ module alu #(parameter WIDTH=32) ( end else assign rotA = A; if (`ZBA_SUPPORTED) begin: zbapreshift + assign PreShiftAmt = Funct3[2:1] & {2{PreShift}}; // Pre-Shift assign CondShiftA = CondExtA << (PreShiftAmt); - end else assign CondShiftA = A; - - // Select appropriate ALU Result - if (`ZBS_SUPPORTED | `ZBB_SUPPORTED) begin - always_comb - if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) - else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect - 3'b000: FullResult = Sum; // add or sub - 3'b001: FullResult = Shift; // sll, sra, or srl - 3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt - 3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu - 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv - 3'b101: FullResult = {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}};// bext - 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset - 3'b111: FullResult = A & CondMaskInvB; // and, bclr - endcase + end else begin + assign PreShiftAmt = 2'b0; + assign CondShiftA = A; end if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse @@ -119,13 +105,4 @@ module alu #(parameter WIDTH=32) ( zbb #(WIDTH) ZBB(.A, .RevA, .B, .ALUResult, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult); end else assign ZBBResult = 0; - // Final Result B instruction select mux -always_comb - case (BSelect) - // 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC - 2'b00: Result = ALUResult; - 2'b01: Result = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word. - 2'b10: Result = ZBBResult; - 2'b11: Result = ZBCResult; - endcase -endmodule \ No newline at end of file +endmodule From 8e67c64e2c574d4ed33503a1ad43068471820f3d Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 23 Mar 2023 16:06:46 -0700 Subject: [PATCH 202/231] fixed rori rv32 bug --- src/ieu/bmu/bmuctrl.sv | 1 + 1 file changed, 1 insertion(+) diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 645e711cc..8a0a2b8a2 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -102,6 +102,7 @@ module bmuctrl( BMUControlsD = `BMUCTRLW'b000_10_000_1_1_0_1_0_0_0_0_0; // count instruction 17'b0110011_0000100_100: if (`XLEN == 32) BMUControlsD = `BMUCTRLW'b000_10_001_1_1_0_1_0_0_0_0_0; // zexth (rv32) + 17'b0010011_0110000_101: BMUControlsD = `BMUCTRLW'b001_00_111_1_1_0_1_0_1_0_0_0; // rori (rv32) 17'b0110011_0100000_111: BMUControlsD = `BMUCTRLW'b111_01_111_1_0_0_1_1_0_0_0_0; // andn 17'b0110011_0100000_110: BMUControlsD = `BMUCTRLW'b110_01_111_1_0_0_1_1_0_0_0_0; // orn 17'b0110011_0100000_100: BMUControlsD = `BMUCTRLW'b100_01_111_1_0_0_1_1_0_0_0_0; // xnor From e69d2e2b96120c69f75d9703ad3b62491c91dfb9 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 17:24:58 -0700 Subject: [PATCH 203/231] Tool change docs --- bin/wally-tool-chain-install.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/bin/wally-tool-chain-install.sh b/bin/wally-tool-chain-install.sh index 798fe51bb..ef98aed76 100755 --- a/bin/wally-tool-chain-install.sh +++ b/bin/wally-tool-chain-install.sh @@ -35,8 +35,8 @@ set -e # break on error # Modify accordingly for your machine # Increasing NUM_THREADS will speed up parallel compilation of the tools -NUM_THREADS=2 # for low memory machines > 16GiB -#NUM_THREADS=8 # for >= 32GiB +#NUM_THREADS=2 # for low memory machines > 16GiB +NUM_THREADS=8 # for >= 32GiB #NUM_THREADS=16 # for >= 64GiB sudo mkdir -p $RISCV From b674ebf7f4e74fcc2f5abb328a4bdd3ab5bf05fd Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 17:25:27 -0700 Subject: [PATCH 204/231] 100% IEU coverage --- sim/coverage-exclusions-rv64gc.do | 19 +++++++++++++++---- tests/coverage/ieu.S | 2 ++ 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index 8f79b7d5d..9905c897b 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -24,11 +24,22 @@ #// and limitations under the License. #//////////////////////////////////////////////////////////////////////////////////////////////// +# LZA (i<64) statement confuses coverage tool +# This is ugly to exlcude the whole file - is there a better option +coverage exclude -srcfile lzc.sv + + +###################### +# Toggle exclusions +# Not used because toggle coverage isn't measured +###################### + # Exclude DivBusyE from all design units because rv64gc uses the fdivsqrt unit for integer division -coverage exclude -togglenode DivBusyE -du * +#coverage exclude -togglenode DivBusyE -du * # Exclude QuotM and RemM from MDU because rv64gc uses the fdivsqrt rather tha div unit for integer division -coverage exclude -togglenode /dut/core/mdu/mdu/QuotM -coverage exclude -togglenode /dut/core/mdu/mdu/RemM +#coverage exclude -togglenode /dut/core/mdu/mdu/QuotM +#coverage exclude -togglenode /dut/core/mdu/mdu/RemM # StallFCause is hardwired to 0 -coverage exclude -togglenode /dut/core/hzu/StallFCause +#coverage exclude -togglenode /dut/core/hzu/StallFCause + diff --git a/tests/coverage/ieu.S b/tests/coverage/ieu.S index 8467f2d4b..e1b239371 100644 --- a/tests/coverage/ieu.S +++ b/tests/coverage/ieu.S @@ -33,6 +33,8 @@ main: clz t1, t0 li t0, -1 clz t1, t0 + li t0, 1 + clz t1, t0 # Test forwarding from store conditional lr.w t0, 0(a0) From c8ea5afe25436a1f26c49782fa0352c6396c72c5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 23 Mar 2023 17:25:59 -0700 Subject: [PATCH 205/231] Removed unnecessary XZero from fdivsqrt --- src/fpu/fdivsqrt/fdivsqrtexpcalc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index b5b2ba335..482fed842 100644 --- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -69,6 +69,6 @@ module fdivsqrtexpcalc( assign SExp = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias}; // correct exponent for subnormal input's normalization shifts - assign DExp = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias}) & {`NE+2{~XZero}}; // *** why Xzero? Is this a hack for postprocessor? + assign DExp = ({2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - {2'b0, Ye} + {{(`NE+1-`DIVBLEN){1'b0}}, m} + {3'b0, Bias}); assign Qe = Sqrt ? SExp : DExp; endmodule From 443e64bef270c8bee2ecb015727eee46b01c88f1 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 23 Mar 2023 20:42:49 -0700 Subject: [PATCH 206/231] more progress. Failing regression --- src/ieu/alu.sv | 47 ++++++++------------------------------ src/ieu/bmu/bitmanipalu.sv | 21 +++++++++-------- 2 files changed, 21 insertions(+), 47 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 7b1b2586d..545e09a81 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -67,19 +67,11 @@ module alu #(parameter WIDTH=32) ( // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; - // Extract control signals from bitmanip ALUControl. assign {Rotate, Mask, PreShift} = BALUControl; // Pack control signals into shifter select assign shASelect = {W64,SubArith}; - assign PreShiftAmt = Funct3[2:1] & {2{PreShift}}; - - if (`ZBS_SUPPORTED) begin: zbsdec - decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); - mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB); - end else assign CondMaskB = B; - if (WIDTH == 64) begin mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, shSignA); mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A,{~W64, SubArith}, CondExtA); @@ -88,16 +80,7 @@ module alu #(parameter WIDTH=32) ( assign CondExtA = A; end - // shifter rotate source select mux - if (`ZBB_SUPPORTED & WIDTH == 64) begin - mux2 #(WIDTH) rotmux(A, {A[31:0], A[31:0]}, W64, rotA); - end else assign rotA = A; - if (`ZBA_SUPPORTED) begin: zbapreshift - // Pre-Shift - assign CondShiftA = CondExtA << (PreShiftAmt); - end else assign CondShiftA = A; - // Addition assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB; assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith}; @@ -130,31 +113,19 @@ module alu #(parameter WIDTH=32) ( endcase end - if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse - bitreverse #(WIDTH) brA(.A, .RevA); - end - - if (`ZBC_SUPPORTED) begin: zbc - zbc #(WIDTH) ZBC(.A, .RevA, .B, .Funct3, .ZBCResult); - end else assign ZBCResult = 0; - - if (`ZBB_SUPPORTED) begin: zbb - zbb #(WIDTH) ZBB(.A, .RevA, .B, .ALUResult, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult); - end else assign ZBBResult = 0; // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; else assign ALUResult = FullResult; // Final Result B instruction select mux - if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : zbdecoder - always_comb - case (BSelect) - // 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC - 2'b00: Result = ALUResult; - 2'b01: Result = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word. - 2'b10: Result = ZBBResult; - 2'b11: Result = ZBCResult; - endcase - end else assign Result = ALUResult; + if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu + bitmanipalu #(WIDTH) balu(.A, .B, .ALUControl, .ALUSelect, .BSelect, .ZBBSelect, .Funct3, .CompFlags, .BALUControl, + .CondMaskB, .CondShiftA, .rotA, .Result); + end else begin + assign Result = ALUResult; + assign CondMaskB = B; + assign CondShiftA = A; + assign rotA = A; + end endmodule \ No newline at end of file diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index eb4b92bc4..04e078e01 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -41,13 +41,11 @@ module bitmanipalu #(parameter WIDTH=32) ( output logic [WIDTH-1:0] CondMaskB, output logic [WIDTH-1:0] CondShiftA, output logic [WIDTH-1:0] rotA, - output logic [WIDTH-1:0] Result, // ALU result - output logic [WIDTH-1:0] ZBBResult, // ZBB result - output logic [WIDTH-1:0] ZBCResult); // ZBC result - + output logic [WIDTH-1:0] Result); // Result // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult,ALUResult; // Intermediate Signals + logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult,ALUResult; // Intermediate Signals + logic [WIDTH-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux logic [WIDTH-1:0] RevA; // Bit-reversed A @@ -70,14 +68,10 @@ module bitmanipalu #(parameter WIDTH=32) ( // Extract control signals from bitmanip ALUControl. assign {Rotate, Mask, PreShift} = BALUControl; - // Pack control signals into shifter select - assign shASelect = {W64,SubArith}; - if (`ZBS_SUPPORTED) begin: zbsdec decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB); end else assign CondMaskB = B; - // shifter rotate source select mux if (`ZBB_SUPPORTED & WIDTH == 64) begin @@ -105,4 +99,13 @@ module bitmanipalu #(parameter WIDTH=32) ( zbb #(WIDTH) ZBB(.A, .RevA, .B, .ALUResult, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult); end else assign ZBBResult = 0; + always_comb + case (BSelect) + // 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC + 2'b00: Result = ALUResult; + 2'b01: Result = FullResult; // NOTE: We don't use ALUResult because ZBA/ZBS instructions don't sign extend the MSB of the right-hand word. + 2'b10: Result = ZBBResult; + 2'b11: Result = ZBCResult; + endcase + endmodule From 9c457e3af4e3a0a0281b227a6f262a39371ec52e Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 23 Mar 2023 21:56:03 -0700 Subject: [PATCH 207/231] bitmanip alu submodule passes lint and regression --- src/ieu/alu.sv | 5 ++--- src/ieu/bmu/bitmanipalu.sv | 39 +++++++++++++++++++------------------- 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 545e09a81..a425de2d1 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -72,6 +72,7 @@ module alu #(parameter WIDTH=32) ( // Pack control signals into shifter select assign shASelect = {W64,SubArith}; + // A, A sign bit muxes if (WIDTH == 64) begin mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, shSignA); mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A,{~W64, SubArith}, CondExtA); @@ -80,7 +81,6 @@ module alu #(parameter WIDTH=32) ( assign CondExtA = A; end - // Addition assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB; assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith}; @@ -113,14 +113,13 @@ module alu #(parameter WIDTH=32) ( endcase end - // Support RV64I W-type addw/subw/addiw/shifts that discard upper 32 bits and sign-extend 32-bit result to 64 bits if (WIDTH == 64) assign ALUResult = W64 ? {{32{FullResult[31]}}, FullResult[31:0]} : FullResult; else assign ALUResult = FullResult; // Final Result B instruction select mux if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu - bitmanipalu #(WIDTH) balu(.A, .B, .ALUControl, .ALUSelect, .BSelect, .ZBBSelect, .Funct3, .CompFlags, .BALUControl, + bitmanipalu #(WIDTH) balu(.A, .B, .ALUControl, .ALUSelect, .BSelect, .ZBBSelect, .Funct3, .CompFlags, .BALUControl, .CondExtA, .ALUResult, .FullResult, .CondMaskB, .CondShiftA, .rotA, .Result); end else begin assign Result = ALUResult; diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 04e078e01..472c8a1fb 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -30,33 +30,30 @@ `include "wally-config.vh" module bitmanipalu #(parameter WIDTH=32) ( - input logic [WIDTH-1:0] A, B, // Operands - input logic [2:0] ALUControl, // With Funct3, indicates operation to perform - input logic [2:0] ALUSelect, // ALU mux select signal - input logic [1:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction - input logic [2:0] ZBBSelect, // ZBB mux select signal - input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect - input logic [1:0] CompFlags, // Comparator flags - input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage - output logic [WIDTH-1:0] CondMaskB, - output logic [WIDTH-1:0] CondShiftA, - output logic [WIDTH-1:0] rotA, - output logic [WIDTH-1:0] Result); // Result + input logic [WIDTH-1:0] A, B, // Operands + input logic [2:0] ALUControl, // With Funct3, indicates operation to perform + input logic [2:0] ALUSelect, // ALU mux select signal + input logic [1:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction + input logic [2:0] ZBBSelect, // ZBB mux select signal + input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect + input logic [1:0] CompFlags, // Comparator flags + input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage + input logic [WIDTH-1:0] CondExtA, // A Conditional Extend Intermediary Signal + input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals + output logic [WIDTH-1:0] CondMaskB, // B is a mask for ZBS instructions + output logic [WIDTH-1:0] CondShiftA, // A for ShAdd instructions + output logic [WIDTH-1:0] rotA, // A for rotate instructions + output logic [WIDTH-1:0] Result); // Result + // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult,ALUResult; // Intermediate Signals + logic [WIDTH-1:0] CondMaskInvB, Shift; // Intermediate Signals logic [WIDTH-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result logic [WIDTH-1:0] MaskB; // BitMask of B - logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux logic [WIDTH-1:0] RevA; // Bit-reversed A - logic Carry, Neg; // Flags: carry out, negative - logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction logic SubArith; // Performing subtraction or arithmetic right shift logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops - logic Asign, Bsign; // Sign bits of A, B - logic shSignA; - logic [1:0] shASelect; // select signal for shifter source generation mux logic Rotate; // Indicates if it is Rotate instruction logic Mask; // Indicates if it is ZBS instruction logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction @@ -68,6 +65,7 @@ module bitmanipalu #(parameter WIDTH=32) ( // Extract control signals from bitmanip ALUControl. assign {Rotate, Mask, PreShift} = BALUControl; + // Mask Generation Mux if (`ZBS_SUPPORTED) begin: zbsdec decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB); @@ -78,15 +76,16 @@ module bitmanipalu #(parameter WIDTH=32) ( mux2 #(WIDTH) rotmux(A, {A[31:0], A[31:0]}, W64, rotA); end else assign rotA = A; + // Pre-Shift Mux if (`ZBA_SUPPORTED) begin: zbapreshift assign PreShiftAmt = Funct3[2:1] & {2{PreShift}}; - // Pre-Shift assign CondShiftA = CondExtA << (PreShiftAmt); end else begin assign PreShiftAmt = 2'b0; assign CondShiftA = A; end + // Bit reverse needed for some ZBB, ZBC instructions if (`ZBC_SUPPORTED | `ZBB_SUPPORTED) begin: bitreverse bitreverse #(WIDTH) brA(.A, .RevA); end From ae162a26948c4f382f5b9b7a1c6c32994033f7b6 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 23 Mar 2023 22:20:37 -0700 Subject: [PATCH 208/231] removed redundant signals -fixed some comments too --- src/ieu/alu.sv | 12 +++--------- src/ieu/bmu/bitmanipalu.sv | 37 ++++++++++++++++++------------------- 2 files changed, 21 insertions(+), 28 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index a425de2d1..41f269e46 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -33,7 +33,7 @@ module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform input logic [2:0] ALUSelect, // ALU mux select signal - input logic [1:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction + input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect input logic [1:0] CompFlags, // Comparator flags @@ -43,13 +43,10 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult,ALUResult; // Intermediate Signals - logic [WIDTH-1:0] ZBCResult, ZBBResult; // Result of ZBB, ZBC - logic [WIDTH-1:0] MaskB; // BitMask of B + logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult, ALUResult; // Intermediate Signals logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux - logic [WIDTH-1:0] RevA; // Bit-reversed A logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic W64; // RV64 W-type instruction @@ -60,14 +57,11 @@ module alu #(parameter WIDTH=32) ( logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter logic [1:0] shASelect; // select signal for shifter source generation mux logic Rotate; // Indicates if it is Rotate instruction - logic Mask; // Indicates if it is ZBS instruction - logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction - logic [1:0] PreShiftAmt; // Amount to Pre-Shift A // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; - assign {Rotate, Mask, PreShift} = BALUControl; + assign Rotate = BALUControl[2]; // Pack control signals into shifter select assign shASelect = {W64,SubArith}; diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 472c8a1fb..83638ce26 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -33,37 +33,34 @@ module bitmanipalu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform input logic [2:0] ALUSelect, // ALU mux select signal - input logic [1:0] BSelect, // One-Hot encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction + input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect input logic [1:0] CompFlags, // Comparator flags input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage input logic [WIDTH-1:0] CondExtA, // A Conditional Extend Intermediary Signal input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals - output logic [WIDTH-1:0] CondMaskB, // B is a mask for ZBS instructions - output logic [WIDTH-1:0] CondShiftA, // A for ShAdd instructions - output logic [WIDTH-1:0] rotA, // A for rotate instructions + output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions + output logic [WIDTH-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions + output logic [WIDTH-1:0] rotA, // Rotate source signal output logic [WIDTH-1:0] Result); // Result - // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. - // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondMaskInvB, Shift; // Intermediate Signals - logic [WIDTH-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result - logic [WIDTH-1:0] MaskB; // BitMask of B - logic [WIDTH-1:0] RevA; // Bit-reversed A - logic W64; // RV64 W-type instruction - logic SubArith; // Performing subtraction or arithmetic right shift - logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops - logic Rotate; // Indicates if it is Rotate instruction - logic Mask; // Indicates if it is ZBS instruction - logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction - logic [1:0] PreShiftAmt; // Amount to Pre-Shift A + logic [WIDTH-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result + logic [WIDTH-1:0] MaskB; // BitMask of B + logic [WIDTH-1:0] RevA; // Bit-reversed A + logic W64; // RV64 W-type instruction + logic SubArith; // Performing subtraction or arithmetic right shift + logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops + logic Rotate; // Indicates if it is Rotate instruction + logic Mask; // Indicates if it is ZBS instruction + logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction + logic [1:0] PreShiftAmt; // Amount to Pre-Shift A // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; // Extract control signals from bitmanip ALUControl. - assign {Rotate, Mask, PreShift} = BALUControl; + assign {Mask, PreShift} = BALUControl[1:0]; // Mask Generation Mux if (`ZBS_SUPPORTED) begin: zbsdec @@ -90,14 +87,17 @@ module bitmanipalu #(parameter WIDTH=32) ( bitreverse #(WIDTH) brA(.A, .RevA); end + // ZBC Unit if (`ZBC_SUPPORTED) begin: zbc zbc #(WIDTH) ZBC(.A, .RevA, .B, .Funct3, .ZBCResult); end else assign ZBCResult = 0; + // ZBB Unit if (`ZBB_SUPPORTED) begin: zbb zbb #(WIDTH) ZBB(.A, .RevA, .B, .ALUResult, .W64, .lt(CompFlags[0]), .ZBBSelect, .ZBBResult); end else assign ZBBResult = 0; + // Result Select Mux always_comb case (BSelect) // 00: ALU, 01: ZBA/ZBS, 10: ZBB, 11: ZBC @@ -106,5 +106,4 @@ module bitmanipalu #(parameter WIDTH=32) ( 2'b10: Result = ZBBResult; 2'b11: Result = ZBCResult; endcase - endmodule From 5a1993451153ca494e89a4c4999a45809c8cbe04 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 23 Mar 2023 22:22:25 -0700 Subject: [PATCH 209/231] comments --- src/ieu/alu.sv | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 41f269e46..c1940f9d3 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -44,27 +44,28 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. logic [WIDTH-1:0] CondMaskInvB, Shift, FullResult, ALUResult; // Intermediate Signals - logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux - logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux - logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux - logic Carry, Neg; // Flags: carry out, negative - logic LT, LTU; // Less than, Less than unsigned - logic W64; // RV64 W-type instruction - logic SubArith; // Performing subtraction or arithmetic right shift - logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops - logic Asign, Bsign; // Sign bits of A, B + logic [WIDTH-1:0] CondMaskB; // Result of B mask select mux + logic [WIDTH-1:0] CondShiftA; // Result of A shifted select mux + logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux + logic Carry, Neg; // Flags: carry out, negative + logic LT, LTU; // Less than, Less than unsigned + logic W64; // RV64 W-type instruction + logic SubArith; // Performing subtraction or arithmetic right shift + logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops + logic Asign, Bsign; // Sign bits of A, B logic shSignA; - logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter - logic [1:0] shASelect; // select signal for shifter source generation mux - logic Rotate; // Indicates if it is Rotate instruction + logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter + logic [1:0] shASelect; // select signal for shifter source generation mux + logic Rotate; // Indicates if it is Rotate instruction // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; + // Extract rotate signal from BALUControl. assign Rotate = BALUControl[2]; - // Pack control signals into shifter select - assign shASelect = {W64,SubArith}; + // Pack control signals into shifter select signal. + assign shASelect = {W64, SubArith}; // A, A sign bit muxes if (WIDTH == 64) begin From 4c73f0fffd69b7dda608e02958773959230c93e7 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Thu, 23 Mar 2023 22:28:21 -0700 Subject: [PATCH 210/231] minor formatting --- src/ieu/alu.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index c1940f9d3..2f1bd9d80 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -114,7 +114,8 @@ module alu #(parameter WIDTH=32) ( // Final Result B instruction select mux if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu - bitmanipalu #(WIDTH) balu(.A, .B, .ALUControl, .ALUSelect, .BSelect, .ZBBSelect, .Funct3, .CompFlags, .BALUControl, .CondExtA, .ALUResult, .FullResult, + bitmanipalu #(WIDTH) balu(.A, .B, .ALUControl, .ALUSelect, .BSelect, .ZBBSelect, + .Funct3, .CompFlags, .BALUControl, .CondExtA, .ALUResult, .FullResult, .CondMaskB, .CondShiftA, .rotA, .Result); end else begin assign Result = ALUResult; From e8d6073eca2017ee55a8cfb9a9700499ef088686 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 24 Mar 2023 06:18:06 -0700 Subject: [PATCH 211/231] BMU simplifications --- src/ieu/alu.sv | 12 ++---------- src/ieu/bmu/bmuctrl.sv | 2 +- src/ieu/controller.sv | 4 +--- 3 files changed, 4 insertions(+), 14 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 2f1bd9d80..a0370f2b4 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -55,22 +55,14 @@ module alu #(parameter WIDTH=32) ( logic Asign, Bsign; // Sign bits of A, B logic shSignA; logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter - logic [1:0] shASelect; // select signal for shifter source generation mux - logic Rotate; // Indicates if it is Rotate instruction // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; - // Extract rotate signal from BALUControl. - assign Rotate = BALUControl[2]; - - // Pack control signals into shifter select signal. - assign shASelect = {W64, SubArith}; - // A, A sign bit muxes if (WIDTH == 64) begin mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, shSignA); - mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A,{~W64, SubArith}, CondExtA); + mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, CondExtA); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux end else begin mux2 #(1) signmux(1'b0, A[31], SubArith, shSignA); assign CondExtA = A; @@ -81,7 +73,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) - shifter sh(.shA(CondExtA), .Sign(shSignA), .rotA, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .Y(Shift), .Rotate); + shifter sh(.shA(CondExtA), .Sign(shSignA), .rotA, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .Y(Shift), .Rotate(BALUControl[2])); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 46222cf7a..4769c63dd 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -34,7 +34,6 @@ module bmuctrl( // Decode stage control signals input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage - output logic [2:0] ALUSelectD, // ALU Mux select signal in Decode Stage output logic [1:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage @@ -62,6 +61,7 @@ module bmuctrl( logic MaskD; // Indicates if zbs instruction in Decode Stage logic PreShiftD; // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage logic [2:0] BALUControlD; // ALU Control signals for B instructions + logic [2:0] ALUSelectD; // ALU Mux select signal in Decode Stage `define BMUCTRLW 17 `define BMUCTRLWSUB3 14 diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 5c397d157..2cb453110 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -98,7 +98,6 @@ module controller( logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu logic BaseALUSrcBD; // Base instruction ALU B source select signal logic [2:0] ALUControlD; // Determines ALU operation - logic [2:0] ALUSelectD; // ALU mux select signal logic ALUSrcAD, ALUSrcBD; // ALU inputs logic ALUResultSrcD, W64D, MDUD; // ALU result, is RV64 W-type, is multiply/divide instruction logic CSRZeroSrcD; // Ignore setting and clearing zeros to CSR @@ -260,7 +259,7 @@ module controller( // bit manipulation Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BALUSrcBD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); if (`ZBA_SUPPORTED) begin @@ -269,7 +268,6 @@ module controller( end else assign sltD = (Funct3D == 3'b010); end else begin: bitmanipi - assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; assign BSelectE = 2'b00; assign BSelectD = 2'b00; From 89479391ca8d4deef76e769b3d8cb08b84915994 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 24 Mar 2023 06:49:26 -0700 Subject: [PATCH 212/231] Simplified rotate source to shifter --- src/ieu/alu.sv | 8 +++----- src/ieu/bmu/bitmanipalu.sv | 10 ++-------- src/ieu/shifter.sv | 30 ++++++++++++++++-------------- 3 files changed, 21 insertions(+), 27 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index a0370f2b4..714535739 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -54,7 +54,6 @@ module alu #(parameter WIDTH=32) ( logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B logic shSignA; - logic [WIDTH-1:0] rotA; // XLEN bit input source to shifter // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; @@ -73,7 +72,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) - shifter sh(.shA(CondExtA), .Sign(shSignA), .rotA, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .Y(Shift), .Rotate(BALUControl[2])); + shifter sh(.A(CondExtA), .Sign(shSignA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .Y(Shift), .Rotate(BALUControl[2])); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign @@ -106,13 +105,12 @@ module alu #(parameter WIDTH=32) ( // Final Result B instruction select mux if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu - bitmanipalu #(WIDTH) balu(.A, .B, .ALUControl, .ALUSelect, .BSelect, .ZBBSelect, + bitmanipalu #(WIDTH) balu(.A, .B, .ALUControl, .BSelect, .ZBBSelect, .Funct3, .CompFlags, .BALUControl, .CondExtA, .ALUResult, .FullResult, - .CondMaskB, .CondShiftA, .rotA, .Result); + .CondMaskB, .CondShiftA, .Result); end else begin assign Result = ALUResult; assign CondMaskB = B; assign CondShiftA = A; - assign rotA = A; end endmodule \ No newline at end of file diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 83638ce26..a8439b762 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -32,17 +32,15 @@ module bitmanipalu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform - input logic [2:0] ALUSelect, // ALU mux select signal input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelect, // ZBB mux select signal - input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect + input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform input logic [1:0] CompFlags, // Comparator flags input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage input logic [WIDTH-1:0] CondExtA, // A Conditional Extend Intermediary Signal input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions output logic [WIDTH-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions - output logic [WIDTH-1:0] rotA, // Rotate source signal output logic [WIDTH-1:0] Result); // Result logic [WIDTH-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result @@ -68,12 +66,8 @@ module bitmanipalu #(parameter WIDTH=32) ( mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB); end else assign CondMaskB = B; - // shifter rotate source select mux - if (`ZBB_SUPPORTED & WIDTH == 64) begin - mux2 #(WIDTH) rotmux(A, {A[31:0], A[31:0]}, W64, rotA); - end else assign rotA = A; - // Pre-Shift Mux + // 0-3 bit Pre-Shift Mux if (`ZBA_SUPPORTED) begin: zbapreshift assign PreShiftAmt = Funct3[2:1] & {2{PreShift}}; assign CondShiftA = CondExtA << (PreShiftAmt); diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 594ef3dd5..d0a6471c8 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -30,8 +30,7 @@ `include "wally-config.vh" module shifter ( - input logic [`XLEN-1:0] shA, // shift Source - input logic [`XLEN-1:0] rotA, // rotate source + input logic [`XLEN-1:0] A, // shift Source input logic [`LOG_XLEN-1:0] Amt, // Shift amount input logic Right, Rotate, W64, Sign, // Shift right, rotate signals output logic [`XLEN-1:0] Y); // Shifted result @@ -43,32 +42,35 @@ module shifter ( if (`XLEN==32) begin // rv32 with rotates always_comb // funnel mux case({Right, Rotate}) - 2'b00: z = {shA[31:0], 31'b0}; - 2'b01: z = {rotA,rotA[31:1]}; - 2'b10: z = {{31{Sign}}, shA[31:0]}; - 2'b11: z = {rotA[30:0],rotA}; + 2'b00: z = {A[31:0], 31'b0}; + 2'b01: z = {A[31:0], A[31:1]}; + 2'b10: z = {{31{Sign}}, A[31:0]}; + 2'b11: z = {A[30:0], A}; endcase assign amttrunc = Amt; // shift amount end else begin // rv64 with rotates + // shifter rotate source select mux + logic [`XLEN-1:0] RotA; // rotate source + mux2 #(`XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons always_comb // funnel mux case ({Right, Rotate}) - 2'b00: z = {shA[63:0],{63'b0}}; - 2'b01: z = {rotA, rotA[63:1]}; - 2'b10: z = {{63{Sign}},shA[63:0]}; - 2'b11: z = {rotA[62:0],rotA[63:0]}; + 2'b00: z = {A[63:0],{63'b0}}; + 2'b01: z = {RotA, RotA[63:1]}; + 2'b10: z = {{63{Sign}}, A[63:0]}; + 2'b11: z = {RotA[62:0], RotA}; endcase assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end end else begin: norotfunnel if (`XLEN==32) begin:shifter // RV32 always_comb // funnel mux - if (Right) z = {{31{Sign}}, shA[31:0]}; - else z = {shA[31:0], 31'b0}; + if (Right) z = {{31{Sign}}, A[31:0]}; + else z = {A[31:0], 31'b0}; assign amttrunc = Amt; // shift amount end else begin:shifter // RV64 always_comb // funnel mux - if (Right) z = {{63{Sign}},shA[63:0]}; - else z = {shA[63:0],{63'b0}}; + if (Right) z = {{63{Sign}}, A[63:0]}; + else z = {A[63:0], {63'b0}}; assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end end From f648be8ee2dbb4f52eb522aa5592305b0a61b190 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 24 Mar 2023 07:28:42 -0700 Subject: [PATCH 213/231] Merged ALUOp into ALUControl to simplify ALU mux --- src/ieu/alu.sv | 5 ++--- src/ieu/bmu/bitmanipalu.sv | 3 +-- src/ieu/bmu/bmuctrl.sv | 17 ++++++++++------- src/ieu/controller.sv | 9 +++------ 4 files changed, 16 insertions(+), 18 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 714535739..82e3c097c 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -86,9 +86,8 @@ module alu #(parameter WIDTH=32) ( // Select appropriate ALU Result always_comb begin - if (~ALUOp) FullResult = Sum; // Always add for ALUOp = 0 (address generation) - else casez (ALUSelect) // Otherwise check Funct3 NOTE: change signal name to ALUSelect - 3'b000: FullResult = Sum; // add or sub + case (ALUSelect) + 3'b000: FullResult = Sum; // add or sub (including address generation) 3'b001: FullResult = Shift; // sll, sra, or srl 3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt 3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index a8439b762..6a63d20a6 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -62,11 +62,10 @@ module bitmanipalu #(parameter WIDTH=32) ( // Mask Generation Mux if (`ZBS_SUPPORTED) begin: zbsdec - decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], MaskB); + decoder #($clog2(WIDTH)) maskgen(B[$clog2(WIDTH)-1:0], MaskB); mux2 #(WIDTH) maskmux(B, MaskB, Mask, CondMaskB); end else assign CondMaskB = B; - // 0-3 bit Pre-Shift Mux if (`ZBA_SUPPORTED) begin: zbapreshift assign PreShiftAmt = Funct3[2:1] & {2{PreShift}}; diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 4769c63dd..ad599c8fe 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -34,12 +34,12 @@ module bmuctrl( // Decode stage control signals input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage + input logic ALUOpD, // Regular ALU Operation output logic [1:0] BSelectD, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding in Decode stage output logic [2:0] ZBBSelectD, // ZBB mux select signal in Decode stage NOTE: do we need this in decode? output logic BRegWriteD, // Indicates if it is a R type B instruction in Decode Stage output logic BALUSrcBD, // Indicates if it is an I/IW (non auipc) type B instruction in Decode Stage output logic BW64D, // Indiciates if it is a W type B instruction in Decode Stage - output logic BALUOpD, // Indicates if it is an ALU B instruction in Decode Stage output logic BSubArithD, // TRUE if ext, clr, andn, orn, xnor instruction in Decode Stage output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction in Decode Stage // Execute stage control signals @@ -61,10 +61,10 @@ module bmuctrl( logic MaskD; // Indicates if zbs instruction in Decode Stage logic PreShiftD; // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage logic [2:0] BALUControlD; // ALU Control signals for B instructions - logic [2:0] ALUSelectD; // ALU Mux select signal in Decode Stage + logic [2:0] BALUSelectD, ALUSelectD; // ALU Mux select signal in Decode Stage + logic BALUOpD; // Indicates if it is an ALU B instruction in Decode Stage `define BMUCTRLW 17 - `define BMUCTRLWSUB3 14 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -76,8 +76,8 @@ module bmuctrl( // Main Instruction Decoder always_comb begin - // ALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD - BMUControlsD = {Funct3D, `BMUCTRLWSUB3'b00_000_0_0_0_0_0_0_0_0_1}; // default: Illegal instruction + // BALUSelect_BSelect_ZBBSelect_BRegWrite_BALUSrcB_BW64_BALUOp_BSubArithD_RotateD_MaskD_PreShiftD_IllegalBitmanipInstrD + BMUControlsD = `BMUCTRLW'b000_00_000_0_0_0_0_0_0_0_0_1; // default: Illegal bmu instruction; if (`ZBA_SUPPORTED) begin casez({OpD, Funct7D, Funct3D}) 17'b0110011_0010000_010: BMUControlsD = `BMUCTRLW'b000_01_000_1_0_0_1_0_0_0_1_0; // sh1add @@ -157,7 +157,7 @@ module bmuctrl( 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_01_000_1_1_0_1_0_0_1_0_0; // bseti (rv64) endcase end - if (`ZBB_SUPPORTED | `ZBS_SUPPORTED) // rv32i/64i shift instructions need certain BMU shifter control when BMU shifter is used + if (`ZBB_SUPPORTED | `ZBS_SUPPORTED) // rv32i/64i shift instructions need BMU ALUSelect when BMU shifter is used casez({OpD, Funct7D, Funct3D}) 17'b0110011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_0_0_1_0_0_0_0_0; // sra, srl, sll 17'b0010011_0?0000?_?01: BMUControlsD = `BMUCTRLW'b001_00_000_1_1_0_1_0_0_0_0_0; // srai, srli, slli @@ -167,7 +167,7 @@ module bmuctrl( end // Unpack Control Signals - assign {ALUSelectD,BSelectD,ZBBSelectD, BRegWriteD,BALUSrcBD, BW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD; + assign {BALUSelectD, BSelectD, ZBBSelectD, BRegWriteD,BALUSrcBD, BW64D, BALUOpD, BSubArithD, RotateD, MaskD, PreShiftD, IllegalBitmanipInstrD} = BMUControlsD; // Pack BALUControl Signals assign BALUControlD = {RotateD, MaskD, PreShiftD}; @@ -175,6 +175,9 @@ module bmuctrl( // Comparator should perform signed comparison when min/max instruction. We have overlap in funct3 with some branch instructions so we use opcode to differentiate betwen min/max and branches assign BComparatorSignedD = (Funct3D[2]^Funct3D[0]) & ~OpD[6]; + // Choose ALUSelect brom BMU for BMU operations, Funct3 for IEU operations, or 0 for addition + assign ALUSelectD = BALUOpD ? BALUSelectD : (ALUOpD ? Funct3D : 3'b000); + // BMU Execute stage pipieline control register flopenrc#(13) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, BALUControlD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE}); endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 2cb453110..8bc68353f 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -127,7 +127,6 @@ module controller( logic [2:0] ZBBSelectD; // ZBB Mux Select Signal logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage logic BW64D; // Indicates if it is a W type B instruction in decode stage - logic BALUOpD; // Indicates if it is an ALU B instruction in decode stage logic BSubArithD; // TRUE for B-type ext, clr, andn, orn, xnor logic BALUSrcBD; // B-type alu src select signal logic BComparatorSignedE; // Indicates if max, min (signed comarison) instruction in Execute Stage @@ -235,11 +234,10 @@ module controller( assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ; //NOTE: Do we want to segregate the IllegalBitmanipInstrD into its own output signal //assign IllegalBaseInstrD = 1'b0; assign {BaseRegWriteD, ImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD, - ResultSrcD, BranchD, BaseALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, + ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD; // If either bitmanip signal or base instruction signal - assign ALUOpD = BaseALUOpD | BALUOpD; assign RegWriteD = BaseRegWriteD | BRegWriteD; assign W64D = BaseW64D | BW64D; assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD; @@ -259,8 +257,8 @@ module controller( // bit manipulation Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .BSelectD, .ZBBSelectD, - .BRegWriteD, .BALUSrcBD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUOpD, .BSelectD, .ZBBSelectD, + .BRegWriteD, .BALUSrcBD, .BW64D, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); if (`ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw @@ -274,7 +272,6 @@ module controller( assign ZBBSelectE = 3'b000; assign BRegWriteD = 1'b0; assign BW64D = 1'b0; - assign BALUOpD = 1'b0; assign BRegWriteE = 1'b0; assign BSubArithD = 1'b0; assign BComparatorSignedE = 1'b0; From 576545e32892094846211563d35d5652d3074ca6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 24 Mar 2023 08:10:48 -0700 Subject: [PATCH 214/231] ALUControl Elimination --- src/ieu/alu.sv | 25 +++++++--------- src/ieu/bmu/bitmanipalu.sv | 8 +----- src/ieu/bmu/bmuctrl.sv | 6 ++-- src/ieu/controller.sv | 59 +++++++++++++++++++------------------- src/ieu/datapath.sv | 5 ++-- src/ieu/ieu.sv | 10 +++---- 6 files changed, 52 insertions(+), 61 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 82e3c097c..11759b1d6 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -31,11 +31,12 @@ module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands - input logic [2:0] ALUControl, // With Funct3, indicates operation to perform + input logic W64, // W64-type instruction + input logic SubArith, // Subtraction or arithmetic shift input logic [2:0] ALUSelect, // ALU mux select signal input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelect, // ZBB mux select signal - input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect + input logic [2:0] Funct3, // For BMU decoding input logic [1:0] CompFlags, // Comparator flags input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage output logic [WIDTH-1:0] Result, // ALU result @@ -49,21 +50,15 @@ module alu #(parameter WIDTH=32) ( logic [WIDTH-1:0] CondExtA; // Result of Zero Extend A select mux logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned - logic W64; // RV64 W-type instruction - logic SubArith; // Performing subtraction or arithmetic right shift - logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Asign, Bsign; // Sign bits of A, B - logic shSignA; - - // Extract control signals from ALUControl. - assign {W64, SubArith, ALUOp} = ALUControl; + logic ShiftSignA; // A, A sign bit muxes if (WIDTH == 64) begin - mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, shSignA); + mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, ShiftSignA); mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, CondExtA); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux end else begin - mux2 #(1) signmux(1'b0, A[31], SubArith, shSignA); + mux2 #(1) signmux(1'b0, A[31], SubArith, ShiftSignA); assign CondExtA = A; end @@ -72,7 +67,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) - shifter sh(.A(CondExtA), .Sign(shSignA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .Y(Shift), .Rotate(BALUControl[2])); + shifter sh(.A(CondExtA), .Sign(ShiftSignA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .Y(Shift), .Rotate(BALUControl[2])); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign @@ -92,7 +87,7 @@ module alu #(parameter WIDTH=32) ( 3'b010: FullResult = {{(WIDTH-1){1'b0}}, LT}; // slt 3'b011: FullResult = {{(WIDTH-1){1'b0}}, LTU}; // sltu 3'b100: FullResult = A ^ CondMaskInvB; // xor, xnor, binv - 3'b101: FullResult = (`ZBS_SUPPORTED | `ZBB_SUPPORTED) ? {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}} : Shift;// bext + 3'b101: FullResult = (`ZBS_SUPPORTED | `ZBB_SUPPORTED) ? {{(WIDTH-1){1'b0}},{|(A & CondMaskB)}} : Shift; // bext (or IEU shift when BMU not supported) 3'b110: FullResult = A | CondMaskInvB; // or, orn, bset 3'b111: FullResult = A & CondMaskInvB; // and, bclr endcase @@ -104,8 +99,8 @@ module alu #(parameter WIDTH=32) ( // Final Result B instruction select mux if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu - bitmanipalu #(WIDTH) balu(.A, .B, .ALUControl, .BSelect, .ZBBSelect, - .Funct3, .CompFlags, .BALUControl, .CondExtA, .ALUResult, .FullResult, + bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, + .Funct3, .CompFlags, .BALUControl, .CondExtA, .ALUResult, .FullResult, .CondMaskB, .CondShiftA, .Result); end else begin assign Result = ALUResult; diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 6a63d20a6..1cf1cd084 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -31,7 +31,7 @@ module bitmanipalu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands - input logic [2:0] ALUControl, // With Funct3, indicates operation to perform + input logic W64, // W64-type instruction input logic [1:0] BSelect, // Binary encoding of if it's a ZBA_ZBB_ZBC_ZBS instruction input logic [2:0] ZBBSelect, // ZBB mux select signal input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform @@ -46,17 +46,11 @@ module bitmanipalu #(parameter WIDTH=32) ( logic [WIDTH-1:0] ZBBResult, ZBCResult; // ZBB, ZBC Result logic [WIDTH-1:0] MaskB; // BitMask of B logic [WIDTH-1:0] RevA; // Bit-reversed A - logic W64; // RV64 W-type instruction - logic SubArith; // Performing subtraction or arithmetic right shift - logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops logic Rotate; // Indicates if it is Rotate instruction logic Mask; // Indicates if it is ZBS instruction logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction logic [1:0] PreShiftAmt; // Amount to Pre-Shift A - // Extract control signals from ALUControl. - assign {W64, SubArith, ALUOp} = ALUControl; - // Extract control signals from bitmanip ALUControl. assign {Mask, PreShift} = BALUControl[1:0]; diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index ad599c8fe..b436fda46 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -44,7 +44,7 @@ module bmuctrl( output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction in Decode Stage // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage - output logic [2:0] ALUSelectE, + output logic [2:0] ALUSelectD, // ALU select output logic [1:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding output logic [2:0] ZBBSelectE, // ZBB mux select signal output logic BRegWriteE, // Indicates if it is a R type B instruction in Execute @@ -61,7 +61,7 @@ module bmuctrl( logic MaskD; // Indicates if zbs instruction in Decode Stage logic PreShiftD; // Indicates if sh1add, sh2add, sh3add instruction in Decode Stage logic [2:0] BALUControlD; // ALU Control signals for B instructions - logic [2:0] BALUSelectD, ALUSelectD; // ALU Mux select signal in Decode Stage + logic [2:0] BALUSelectD; // ALU Mux select signal in Decode Stage for BMU operations logic BALUOpD; // Indicates if it is an ALU B instruction in Decode Stage `define BMUCTRLW 17 @@ -179,5 +179,5 @@ module bmuctrl( assign ALUSelectD = BALUOpD ? BALUSelectD : (ALUOpD ? Funct3D : 3'b000); // BMU Execute stage pipieline control register - flopenrc#(13) controlregBMU(clk, reset, FlushE, ~StallE, {ALUSelectD, BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, BALUControlD}, {ALUSelectE, BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE}); + flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, BALUControlD}, {BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE}); endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 8bc68353f..21811b49a 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -45,7 +45,6 @@ module controller( input logic [1:0] FlagsE, // Comparison flags ({eq, lt}) input logic FWriteIntE, // Write integer register, coming from FPU controller output logic PCSrcE, // Select signal to choose next PC (for datapath and Hazard unit) - output logic [2:0] ALUControlE, // ALU operation to perform output logic ALUSrcAE, ALUSrcBE, // ALU operands output logic ALUResultSrcE, // Selects result to pass on to Memory stage output logic [2:0] ALUSelectE, // ALU mux select signal @@ -54,6 +53,7 @@ module controller( output logic IntDivE, // Integer divide output logic MDUE, // MDU (multiply/divide) operatio output logic W64E, // RV64 W-type operation + output logic SubArithE, // Subtraction or arithmetic shift output logic JumpE, // jump instruction output logic BranchE, // Branch instruction output logic SCE, // Store Conditional instruction @@ -93,7 +93,7 @@ module controller( logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file logic [1:0] MemRWD, MemRWE; // Store (write to memory) logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) - logic BaseALUOpD, BaseW64D; // ALU operation and W64 for Base instructions specifically + logic BaseW64D; // W64 for Base instructions specifically logic BaseRegWriteD; // Indicates if Base instruction register write instruction logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu logic BaseALUSrcBD; // Base instruction ALU B source select signal @@ -111,6 +111,7 @@ module controller( logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions + logic ALUOpE; // 0 for address generationm 1 for ALU operations logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; @@ -118,22 +119,18 @@ module controller( logic IEURegWriteE; // Register write logic BRegWriteE; // Register write from BMU controller in Execute Stage logic IllegalERegAdrD; // RV32E attempts to write upper 16 registers - logic IllegalBitmanipInstrD; // Unrecognized B instruction logic [1:0] AtomicE; // Atomic instruction logic FenceD, FenceE; // Fence instruction logic SFenceVmaD; // sfence.vma instruction logic IntDivM; // Integer divide instruction logic [1:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage logic [2:0] ZBBSelectD; // ZBB Mux Select Signal - logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage - logic BW64D; // Indicates if it is a W type B instruction in decode stage - logic BSubArithD; // TRUE for B-type ext, clr, andn, orn, xnor - logic BALUSrcBD; // B-type alu src select signal logic BComparatorSignedE; // Indicates if max, min (signed comarison) instruction in Execute Stage logic IFunctD, RFunctD, MFunctD; // Detect I, R, and M-type RV32IM/Rv64IM instructions logic LFunctD, SFunctD, BFunctD; // Detect load, store, branch instructions logic JFunctD; // detect jalr instruction logic FenceM; // Fence.I or sfence.VMA instruction in memory stage + logic [2:0] ALUSelectD; // ALU Output selection mux control // Extract fields assign OpD = InstrD[6:0]; @@ -231,17 +228,10 @@ module controller( // Squash control signals if coming from an illegal compressed instruction // On RV32E, can't write to upper 16 registers. Checking reads to upper 16 is more costly so disregard them. assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11]; - assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ; //NOTE: Do we want to segregate the IllegalBitmanipInstrD into its own output signal //assign IllegalBaseInstrD = 1'b0; assign {BaseRegWriteD, ImmSrcD, ALUSrcAD, BaseALUSrcBD, MemRWD, ResultSrcD, BranchD, ALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD, PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD; - - // If either bitmanip signal or base instruction signal - assign RegWriteD = BaseRegWriteD | BRegWriteD; - assign W64D = BaseW64D | BW64D; - assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD; - assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source? assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros @@ -253,34 +243,45 @@ module controller( assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); assign BaseSubArithD = ALUOpD & (subD | sraD | sltD | sltuD); - assign ALUControlD = {W64D, SubArithD, ALUOpD}; // bit manipulation Configuration Block if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags + logic IllegalBitmanipInstrD; // Unrecognized B instruction + logic BRegWriteD; // Indicates if it is a R type BMU instruction in decode stage + logic BW64D; // Indicates if it is a W type BMU instruction in decode stage + logic BSubArithD; // TRUE for BMU ext, clr, andn, orn, xnor + logic BALUSrcBD; // BMU alu src select signal + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUOpD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BALUSrcBD, .BW64D, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, - .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); + .ALUSelectD, .BSelectE, .ZBBSelectE, .BRegWriteE, .BComparatorSignedE, .BALUControlE); if (`ZBA_SUPPORTED) begin // ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ; end else assign sltD = (Funct3D == 3'b010); + // Combine base and bit manipulation signals + assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ; + assign RegWriteD = BaseRegWriteD | BRegWriteD; + assign W64D = BaseW64D | BW64D; + assign ALUSrcBD = BaseALUSrcBD | BALUSrcBD; + assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If BMU or R-type instruction involves inverted operand + end else begin: bitmanipi - assign ALUSelectE = Funct3E; + assign ALUSelectD = ALUOpD ? Funct3D : 3'b000; // add for address generation when not doing ALU operation + assign sltD = (Funct3D == 3'b010); + assign IllegalBaseInstrD = ControlsD[0] | IllegalERegAdrD ; + assign RegWriteD = BaseRegWriteD; + assign W64D = BaseW64D; + assign ALUSrcBD = BaseALUSrcBD; + assign SubArithD = BaseSubArithD; // TRUE If B-type or R-type instruction involves inverted operand + + // tie off unused bit manipulation signals assign BSelectE = 2'b00; assign BSelectD = 2'b00; assign ZBBSelectE = 3'b000; - assign BRegWriteD = 1'b0; - assign BW64D = 1'b0; - assign BRegWriteE = 1'b0; - assign BSubArithD = 1'b0; assign BComparatorSignedE = 1'b0; assign BALUControlE = 3'b0; - assign BALUSrcBD = 1'b0; - - assign sltD = (Funct3D == 3'b010); - - assign IllegalBitmanipInstrD = 1'b1; end // Fences @@ -300,9 +301,9 @@ module controller( flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(28) controlregE(clk, reset, FlushE, ~StallE, - {RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, - {IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); + flopenrc #(29) controlregE(clk, reset, FlushE, ~StallE, + {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD}, + {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE}); // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index dc9a02894..a6fb1fdcd 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -40,7 +40,8 @@ module datapath ( input logic [2:0] Funct3E, // Funct3 field of instruction in Execute stage input logic StallE, FlushE, // Stall, flush Execute stage input logic [1:0] ForwardAE, ForwardBE, // Forward ALU operands from later stages - input logic [2:0] ALUControlE, // Indicate operation ALU performs + input logic W64E, // W64-type instruction + input logic SubArithE, // Subtraction or arithmetic shift input logic ALUSrcAE, ALUSrcBE, // ALU operands input logic ALUResultSrcE, // Selects result to pass on to Memory stage input logic [2:0] ALUSelectE, // ALU mux select signal @@ -113,7 +114,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, BALUControlE, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, W64E, SubArithE, ALUSelectE, BSelectE, ZBBSelectE, Funct3E, FlagsE, BALUControlE, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index c436a96db..0fdba9e8a 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -76,7 +76,6 @@ module ieu ( logic [2:0] ImmSrcD; // Select type of immediate extension logic [1:0] FlagsE; // Comparison flags ({eq, lt}) - logic [2:0] ALUControlE; // ALU control indicates function to perform logic ALUSrcAE, ALUSrcBE; // ALU source operands logic [2:0] ResultSrcW; // Selects result in Writeback stage logic ALUResultSrcE; // Selects ALU result to pass on to Memory stage @@ -87,6 +86,7 @@ module ieu ( logic [1:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding logic [2:0] ZBBSelectE; // ZBB Result Select Signal in Execute Stage logic [2:0] BALUControlE; // ALU Control signals for B instructions in Execute Stage + logic SubArithE; // Subtraction or arithmetic shift // Forwarding signals logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers @@ -99,15 +99,15 @@ module ieu ( controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE, - .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, - .Funct3E, .IntDivE, .MDUE, .W64E, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .StallM, .FlushM, .MemRWM, + .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, + .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD); datapath dp( - .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, - .ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, + .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .W64E, .SubArithE, + .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .ZBBSelectE, .BALUControlE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, From 2dda311df8f97ca0a094f838c60fa995b65e35f8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 24 Mar 2023 08:11:15 -0700 Subject: [PATCH 215/231] Avoid printing junk when running regression --- sim/regression-wally | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sim/regression-wally b/sim/regression-wally index 122b04b51..7a509c890 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -162,7 +162,7 @@ def run_test_case(config): """Run the given test case, and return 0 if the test suceeds and 1 if it fails""" logname = "logs/"+config.variant+"_"+config.name+".log" cmd = config.cmd.format(logname) - print(cmd) +# print(cmd) os.chdir(regressionDir) os.system(cmd) if search_log_for_text(config.grepstr, logname): From f1e87c5e69e345c8d532b4ab4a11f2f79fdc83d5 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 24 Mar 2023 08:12:02 -0700 Subject: [PATCH 216/231] Start of EBU coverage tests --- src/ebu/ebufsmarb.sv | 27 +++++++++++++++----------- testbench/tests.vh | 1 + tests/coverage/ebu.S | 45 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 62 insertions(+), 11 deletions(-) create mode 100644 tests/coverage/ebu.S diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index bd5cfb892..11d3eb2b6 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -56,7 +56,7 @@ module ebufsmarb ( logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst logic BeatCntEn; - logic [4-1:0] NextBeatCount, BeatCount; // Position within a burst transfer + logic [3:0] BeatCount; // Position within a burst transfer logic CntReset; logic [3:0] Threshold; // Number of beats derived from HBURST @@ -91,31 +91,36 @@ module ebufsmarb ( // This is necessary because the pipeline is stalled for the entire duration of both transactions, // and the LSU memory request will stil be active. flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD); - assign LSUDisable = CurrState == ARBITRATE ? 1'b0 : (IFUReqD & ~(HREADY & FinalBeatD)); - assign LSUSelect = NextState == ARBITRATE ? 1'b1: LSUReq; + assign LSUDisable = (CurrState == ARBITRATE) ? 1'b0 : (IFUReqD & ~(HREADY & FinalBeatD)); + assign LSUSelect = (NextState == ARBITRATE) ? 1'b1: LSUReq; //////////////////////////////////////////////////////////////////////////////////////////////////// // Burst mode logic //////////////////////////////////////////////////////////////////////////////////////////////////// - flopenr #(4) BeatCountReg(HCLK, ~HRESETn | CntReset | FinalBeat, BeatCntEn, NextBeatCount, BeatCount); - assign NextBeatCount = BeatCount + 1'b1; - assign CntReset = NextState == IDLE; assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access. - assign BeatCntEn = (NextState == ARBITRATE & HREADY); - + assign BeatCntEn = (NextState == ARBITRATE) & HREADY; + counter #(4) BeatCounter(HCLK, ~HRESETn | CntReset | FinalBeat, BeatCntEn, BeatCount); + // Used to store data from data phase of AHB. flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | CntReset, BeatCntEn, FinalBeat, FinalBeatD); // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST. - always_comb begin - case(HBURST) + // HBURST[2:1] Beats + // 00 1 + // 01 4 + // 10 8 + // 11 16 + always_comb + if (HBURST[2:1] == 2'b00) Threshold = 4'b0000; + else Threshold = (2 << HBURST[2:1]) - 1; +/* case(HBURST) 0: Threshold = 4'b0000; 3: Threshold = 4'b0011; // INCR4 5: Threshold = 4'b0111; // INCR8 7: Threshold = 4'b1111; // INCR16 default: Threshold = 4'b0000; // INCR without end. endcase - end + end */ endmodule diff --git a/testbench/tests.vh b/testbench/tests.vh index f5e02290b..64b5ca59a 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -45,6 +45,7 @@ string tvpaths[] = '{ string coverage64gc[] = '{ `COVERAGE, "ieu", + "ebu", "csrwrites" }; diff --git a/tests/coverage/ebu.S b/tests/coverage/ebu.S new file mode 100644 index 000000000..8c69f9d11 --- /dev/null +++ b/tests/coverage/ebu.S @@ -0,0 +1,45 @@ +/////////////////////////////////////////// +// ebu.S +// +// Written: David_Harris@hmc.edu 23 March 2023 +// +// Purpose: Test coverage for EBU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate +#include "WALLY-init-lib.h" + +main: + + # Test clz with all bits being 0 + li t0, 0 + clz t1, t0 + li t0, -1 + clz t1, t0 + li t0, 1 + clz t1, t0 + + # Test forwarding from store conditional + lr.w t0, 0(a0) + sc.w t0, a1, 0(a0) + addi t0, t0, 1 + + j done + From cb261731f24d2ece99dd7f8843de15ea27e892e8 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 24 Mar 2023 08:12:32 -0700 Subject: [PATCH 217/231] FPU detect illegal instructions --- src/fpu/fctrl.sv | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index e787d10b4..5700e1b6a 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -123,7 +123,7 @@ module fctrl ( 7'b00001??: ControlsD = `FCTRLW'b1_0_01_10_111_0_0_0; // fsub 7'b00010??: ControlsD = `FCTRLW'b1_0_01_10_100_0_0_0; // fmul 7'b00011??: ControlsD = `FCTRLW'b1_0_01_01_xx0_1_0_0; // fdiv - 7'b01011??: ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0_0; // fsqrt + 7'b01011??: if (Rs2D == 5'b0000) ControlsD = `FCTRLW'b1_0_01_01_xx1_1_0_0; // fsqrt 7'b00100??: case(Funct3D) 3'b000: ControlsD = `FCTRLW'b1_0_00_xx_000_0_0_0; // fsgnj 3'b001: ControlsD = `FCTRLW'b1_0_00_xx_001_0_0_0; // fsgnjn @@ -141,7 +141,8 @@ module fctrl ( 3'b000: ControlsD = `FCTRLW'b0_1_00_xx_011_0_0_0; // fle default: ControlsD = `FCTRLW'b0_0_00_xx_000__0_1_0; // non-implemented instruction endcase - 7'b11100??: if (Funct3D == 3'b001) ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass + 7'b11100??: if (Funct3D == 3'b001 & Rs2D == 5'b00000) + ControlsD = `FCTRLW'b0_1_10_xx_000_0_0_0; // fclass else if (Funct3D[1:0] == 2'b00) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.w to int reg else if (Funct3D[1:0] == 2'b01) ControlsD = `FCTRLW'b0_1_11_xx_000_0_0_0; // fmv.x.d to int reg else ControlsD = `FCTRLW'b0_0_00_xx_000_0_1_0; // non-implemented instruction From 21424d0f8648ff70753c4826867a68b78846eabb Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 24 Mar 2023 08:27:30 -0700 Subject: [PATCH 218/231] Shifter sign simplification and capitalization --- src/ieu/alu.sv | 5 +---- src/ieu/shifter.sv | 19 +++++++++++-------- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 11759b1d6..47af5f4d5 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -51,14 +51,11 @@ module alu #(parameter WIDTH=32) ( logic Carry, Neg; // Flags: carry out, negative logic LT, LTU; // Less than, Less than unsigned logic Asign, Bsign; // Sign bits of A, B - logic ShiftSignA; // A, A sign bit muxes if (WIDTH == 64) begin - mux3 #(1) signmux(A[63], A[31], 1'b0, {~SubArith, W64}, ShiftSignA); mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, CondExtA); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux end else begin - mux2 #(1) signmux(1'b0, A[31], SubArith, ShiftSignA); assign CondExtA = A; end @@ -67,7 +64,7 @@ module alu #(parameter WIDTH=32) ( assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) - shifter sh(.A(CondExtA), .Sign(ShiftSignA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .Y(Shift), .Rotate(BALUControl[2])); + shifter sh(.A(CondExtA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2])); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index d0a6471c8..8dbdf88e4 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -30,13 +30,16 @@ `include "wally-config.vh" module shifter ( - input logic [`XLEN-1:0] A, // shift Source - input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Rotate, W64, Sign, // Shift right, rotate signals - output logic [`XLEN-1:0] Y); // Shifted result + input logic [`XLEN-1:0] A, // shift Source + input logic [`LOG_XLEN-1:0] Amt, // Shift amount + input logic Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift + output logic [`XLEN-1:0] Y); // Shifted result - logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] amttrunc, offset; // Shift amount adjusted for RV64, right-shift amount + logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits + logic [`LOG_XLEN-1:0] amttrunc, Offset; // Shift amount adjusted for RV64, right-shift amount + logic Sign; // Sign bit for sign extension + + assign Sign = A[`XLEN-1] & SubArith; // sign bit for sign extension if (`ZBB_SUPPORTED) begin: rotfunnel if (`XLEN==32) begin // rv32 with rotates @@ -76,10 +79,10 @@ module shifter ( end // Opposite offset for right shifts - assign offset = Right ? amttrunc : ~amttrunc; + assign Offset = Right ? amttrunc : ~amttrunc; // Funnel operation - assign zshift = z >> offset; + assign zshift = z >> Offset; assign Y = zshift[`XLEN-1:0]; endmodule From 89954df49b1503406af8ca589bbfe5f7d31126ef Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 24 Mar 2023 08:35:33 -0700 Subject: [PATCH 219/231] Query about CondExtA --- src/ieu/alu.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 47af5f4d5..15328bb2f 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -52,9 +52,9 @@ module alu #(parameter WIDTH=32) ( logic LT, LTU; // Less than, Less than unsigned logic Asign, Bsign; // Sign bits of A, B - // A, A sign bit muxes + // *** explain this part better; possibly move into shifter and BMU? if (WIDTH == 64) begin - mux3 #(64) extendmux({{32{1'b0}}, A[31:0]},{{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, CondExtA); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux + mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, CondExtA); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux end else begin assign CondExtA = A; end From 47f8e847f09e7a08d9684962c6b13f55cab61304 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 10:51:04 -0500 Subject: [PATCH 220/231] Renamed ebu signal. --- src/ebu/ebufsmarb.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 11d3eb2b6..1990e8f5d 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -57,7 +57,7 @@ module ebufsmarb ( logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst logic BeatCntEn; logic [3:0] BeatCount; // Position within a burst transfer - logic CntReset; + logic BeatCntReset; logic [3:0] Threshold; // Number of beats derived from HBURST //////////////////////////////////////////////////////////////////////////////////////////////////// @@ -98,13 +98,13 @@ module ebufsmarb ( // Burst mode logic //////////////////////////////////////////////////////////////////////////////////////////////////// - assign CntReset = NextState == IDLE; + assign BeatCntReset = NextState == IDLE; assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access. assign BeatCntEn = (NextState == ARBITRATE) & HREADY; - counter #(4) BeatCounter(HCLK, ~HRESETn | CntReset | FinalBeat, BeatCntEn, BeatCount); + counter #(4) BeatCounter(HCLK, ~HRESETn | BeatCntReset | FinalBeat, BeatCntEn, BeatCount); // Used to store data from data phase of AHB. - flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | CntReset, BeatCntEn, FinalBeat, FinalBeatD); + flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, FinalBeat, FinalBeatD); // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST. // HBURST[2:1] Beats From 4b9b20bce09f2d880c5c4bd4ffdb8a796fb50d56 Mon Sep 17 00:00:00 2001 From: David Harris Date: Fri, 24 Mar 2023 09:01:07 -0700 Subject: [PATCH 221/231] Shifter capitalization --- src/ieu/shifter.sv | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 8dbdf88e4..bdb40022a 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -35,8 +35,8 @@ module shifter ( input logic Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift output logic [`XLEN-1:0] Y); // Shifted result - logic [2*`XLEN-2:0] z, zshift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] amttrunc, Offset; // Shift amount adjusted for RV64, right-shift amount + logic [2*`XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits + logic [`LOG_XLEN-1:0] TruncAmt, Offset; // Shift amount adjusted for RV64, right-shift amount logic Sign; // Sign bit for sign extension assign Sign = A[`XLEN-1] & SubArith; // sign bit for sign extension @@ -45,45 +45,45 @@ module shifter ( if (`XLEN==32) begin // rv32 with rotates always_comb // funnel mux case({Right, Rotate}) - 2'b00: z = {A[31:0], 31'b0}; - 2'b01: z = {A[31:0], A[31:1]}; - 2'b10: z = {{31{Sign}}, A[31:0]}; - 2'b11: z = {A[30:0], A}; + 2'b00: Z = {A[31:0], 31'b0}; + 2'b01: Z = {A[31:0], A[31:1]}; + 2'b10: Z = {{31{Sign}}, A[31:0]}; + 2'b11: Z = {A[30:0], A}; endcase - assign amttrunc = Amt; // shift amount + assign TruncAmt = Amt; // shift amount end else begin // rv64 with rotates // shifter rotate source select mux logic [`XLEN-1:0] RotA; // rotate source mux2 #(`XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons always_comb // funnel mux case ({Right, Rotate}) - 2'b00: z = {A[63:0],{63'b0}}; - 2'b01: z = {RotA, RotA[63:1]}; - 2'b10: z = {{63{Sign}}, A[63:0]}; - 2'b11: z = {RotA[62:0], RotA}; + 2'b00: Z = {A[63:0],{63'b0}}; + 2'b01: Z = {RotA, RotA[63:1]}; + 2'b10: Z = {{63{Sign}}, A[63:0]}; + 2'b11: Z = {RotA[62:0], RotA}; endcase - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + assign TruncAmt = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end end else begin: norotfunnel if (`XLEN==32) begin:shifter // RV32 always_comb // funnel mux - if (Right) z = {{31{Sign}}, A[31:0]}; - else z = {A[31:0], 31'b0}; - assign amttrunc = Amt; // shift amount + if (Right) Z = {{31{Sign}}, A[31:0]}; + else Z = {A[31:0], 31'b0}; + assign TruncAmt = Amt; // shift amount end else begin:shifter // RV64 always_comb // funnel mux - if (Right) z = {{63{Sign}}, A[63:0]}; - else z = {A[63:0], {63'b0}}; - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + if (Right) Z = {{63{Sign}}, A[63:0]}; + else Z = {A[63:0], {63'b0}}; + assign TruncAmt = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end end // Opposite offset for right shifts - assign Offset = Right ? amttrunc : ~amttrunc; + assign Offset = Right ? TruncAmt : ~TruncAmt; // Funnel operation - assign zshift = z >> Offset; - assign Y = zshift[`XLEN-1:0]; + assign ZShift = Z >> Offset; + assign Y = ZShift[`XLEN-1:0]; endmodule From 78701488146e47cee7aee20c35e00ddc9f01d33f Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 22:12:04 -0700 Subject: [PATCH 222/231] added premilinary boundary ccrossing cases --- .../references/WALLY-pmp-01.reference_output | 8 +++++- .../rv64i_m/privilege/src/WALLY-pmp-01.S | 26 ++++++++++++------- 2 files changed, 24 insertions(+), 10 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output index ea5a0cb18..031d87970 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output @@ -1,6 +1,6 @@ 0fffffff # Test 12.3.2.2.1: writeback of value written to PMPADDR0 00000000 -20040000 # writeback of value written to PMPADDR1 +20040001 # writeback of value written to PMPADDR1 00000000 2004003f # writeback of value written to PMPADDR2 00000000 @@ -26,6 +26,12 @@ 00000000 00000bad 00000000 +00000005 # read test with access fault when access begins in allowed region and ends in protected NA region +00000000 +00000bad +00000000 +00000007 # write test with access fault when access begins in allowed region and ends in protected TOR region +00000000 00600dbb # read test success from region with L=X=W=R=0 00000000 0000000b # Test 12.3.2.2.3: ecall from going to S mode from M mode diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S index fc3864d38..dcc2a2dc6 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S @@ -60,18 +60,19 @@ test_cases: # write pmpaddr regs. Each of these should output the value of the pmpaddr after being written. # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments | -.8byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1F | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | -.8byte 0x1, 0x20040000, write_pmpaddr_1 # | 1 | 0x20040000 | 00 | 0 | OFF | 0 | 0 | 0 | | -.8byte 0x2, 0x2004003F, write_pmpaddr_2 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100000-801000FF R | -.8byte 0x3, 0x20040080, write_pmpaddr_3 # | 3 | 0x20040080 | 00 | 0 | OFF | 0 | 0 | 0 | | -.8byte 0x4, 0x20040084, write_pmpaddr_4 # | 4 | 0x20040084 | 0C | 0 | TOR | 1 | 0 | 0 | 80100200-80100210 X | -.8byte 0x5, 0x200400C0, write_pmpaddr_5 # | 5 | 0x200400C0 | 90 | 1 | NA4 | 0 | 0 | 0 | 80100300-80100303 locked out | -.8byte 0x6, 0x2004013F, write_pmpaddr_6 # | 6 | 0x2004013F | 18 | 0 | NAPOT | 0 | 0 | 0 | 80100400-801004FF no access | +.8byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1B | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | +.8byte 0x1, 0x20040001, write_pmpaddr_1 # | 1 | 0x20040001 | 00 | 0 | OFF | 0 | 0 | 0 | | +.8byte 0x2, 0x2004003F, write_pmpaddr_2 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100004-801000FF R | +.8byte 0x3, 0x20040080, write_pmpaddr_3 # | 3 | 0x20040080 | 16 | 0 | NA4 | 1 | 1 | 0 | 80100200-80100203 XW | +.8byte 0x4, 0x20040081, write_pmpaddr_4 # | 4 | 0x20040081 | 00 | 0 | OFF | 0 | 0 | 0 | | +.8byte 0x5, 0x20040084, write_pmpaddr_5 # | 5 | 0x20040084 | 0C | 0 | TOR | 1 | 0 | 0 | 80100204-80100210 X | +.8byte 0x5, 0x200400C1, write_pmpaddr_6 # | 6 | 0x200400C1 | 90 | 1 | NA4 | 0 | 0 | 0 | 80100304-80100307 locked out | +.8byte 0x6, 0x2004013F, write_pmpaddr_7 # | 7 | 0x2004013F | 18 | 0 | NAPOT | 0 | 0 | 0 | 80100400-801004FF no access | # Pmpaddr 7-14 are all zeroed out in this test, so they don't need writes. .8byte 0xF, 0x2FFFFFFF, write_pmpaddr_15 # | 15 | 0x2FFFFFFF | 1F | 0 | NAPOT | 1 | 1 | 1 | Main mem 80000000-FFFFFFFF RWX| # write pmpcfg regs with the information in the table above. this should also write the value of these registers to the output. -.8byte 0x0, 0x0018900C0009001F, write_pmpcfg_0 # write pmpcfg0, output 0x0018900C0009001F +.8byte 0x0, 0x0018900C0009001F, write_pmpcfg_0 # write pmpcfg0, output 0x0018900C0009001B .8byte 0x2, 0x1F00000000000000, write_pmpcfg_2 # write pmpcfg2, output 0x1F00000000000000 # write known values to memory where W=0. This should be possible since we're in machine mode. @@ -90,7 +91,14 @@ test_cases: # Test 12.3.2.2.2 Machine mode access -.8byte 0x80100300, 0x0, read64_test # access fault to region with L=1, R=0 +.8byte 0x80100304, 0x0, read32_test # access fault to region with L=1, R=0 + +# accesses across PMP region boundaries +.8byte 0x80100300, 0x0, read64_test # access fault when access begins in allowed NA region and goes into protected region. + +.8byte 0x80100000, 0xbad, write64_test # access fault when access begins in allowed TOR region and goes into protected region. +.8byte 0x80100000, 0xbad, write64_test # access fault when access begins in allowed TOR region and goes into protected region. + .8byte 0x80100400, 0x0, read64_test # successful access to region with L=X=W=R=0 # Test 12.3.2.2.3 System mode access From 6f15ae1225b2faa83611397f64743bac23ac6800 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 23:08:39 -0700 Subject: [PATCH 223/231] Added cause_s_soft_from_m_interrupt --- .../rv64i_m/privilege/src/WALLY-TEST-LIB-64.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h index 00e235f35..85b5ab8c4 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h @@ -162,6 +162,11 @@ cause_s_soft_interrupt: csrs sip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. ret +cause_s_soft_from_m_interrupt: + li t3, 0x2 + csrs mip, t3 // set supervisor software interrupt pending. SIP is a subset of MIP, so writing this should also change MIP. + ret + cause_m_ext_interrupt: // ========== Configure PLIC ========== li a3, 0x40 From ff59fefcc9a82c10cb587c3647a6db2ca0f50cbd Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 23:09:43 -0700 Subject: [PATCH 224/231] replaced inerrupt tests with allowed versions --- .../privilege/references/WALLY-trap-s-01.reference_output | 8 -------- .../rv64i_m/privilege/src/WALLY-stvec-01.S | 2 +- .../rv64i_m/privilege/src/WALLY-trap-01.S | 4 ++-- .../rv64i_m/privilege/src/WALLY-trap-s-01.S | 6 +++--- 4 files changed, 6 insertions(+), 14 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output index fe559dfb7..cdc883697 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -60,14 +60,6 @@ 00000000 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0 00000000 -0007ec01 # value to indicate successful vectoring on s soft interrupt -00000000 -00000001 # scause value from s soft interrupt -80000000 -00000000 # stval for ssoft interrupt (0x0) -00000000 -00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 -00000000 0007ec03 # value to indicate successful vectoring on m soft interrupt 00000000 00000003 # scause value from m soft interrupt diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S index 4a4bdb768..05ecf515a 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S @@ -49,7 +49,7 @@ jal cause_s_soft_interrupt // only cause one interrupt since we just want to tes GOTO_M_MODE -jal cause_s_soft_interrupt // set software interrupt pending without it firing so we can make it fire in U mode +jal cause_s_soft_from_m_interrupt // set software interrupt pending without it firing so we can make it fire in U mode GOTO_U_MODE // Should cause software interrupt to fire off. diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S index 41d9cd072..b44b6440d 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S @@ -50,7 +50,7 @@ GOTO_S_MODE // Causes U mode ecall GOTO_M_MODE // Causes S mode ecall -jal cause_s_soft_interrupt +jal cause_s_soft_from_m_interrupt jal cause_m_soft_interrupt jal cause_s_time_interrupt jal cause_m_time_interrupt @@ -72,7 +72,7 @@ jal cause_store_addr_misaligned jal cause_store_acc jal cause_ecall // M mode ecall -jal cause_s_soft_interrupt // The delegated S mode interrupts should not fire since we're running in M mode. +jal cause_s_soft_interrupt // S Mode Interrupts Ignored in M mode. sip writeable when mideleg = 1 jal cause_m_soft_interrupt jal cause_s_time_interrupt jal cause_m_time_interrupt diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S index cfe02f3a6..525e79276 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-s-01.S @@ -56,12 +56,12 @@ GOTO_U_MODE // Causes S mode ecall GOTO_S_MODE // Causes U mode ecall -// some interrupts excluded becaus writing MIP is illegal from S mode -jal cause_s_soft_interrupt +// some interrupts excluded because writing MIP is illegal from S mode and writing SIP is only possible when delegated, which is tested below (priv spec 3.1.9) +//jal cause_s_soft_interrupt jal cause_m_soft_interrupt jal cause_m_time_interrupt li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. -// since interrupts are not always enabled, +// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 jal cause_s_ext_interrupt_GPIO li a3, 0x40 jal cause_m_ext_interrupt From 758da62a9f0e8141e6545e1a2df9e4d9b6206c2b Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 23:16:57 -0700 Subject: [PATCH 225/231] ported fixes to 32 bit tests --- .../privilege/references/WALLY-trap-s-01.reference_output | 4 ---- .../rv32i_m/privilege/src/WALLY-trap-s-01.S | 6 +++--- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output index 089aeba9d..5ee52bee5 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/references/WALLY-trap-s-01.reference_output @@ -29,10 +29,6 @@ 00000008 # scause from U mode ecall 00000000 # stval of ecall (*** defined to be zero for now) 00000000 # masked out mstatus.mpp = 0 (from U mode), mstatus.MPIE = 0, and mstatus.MIE = 0 -0007ec01 # value to indicate successful vectoring on s soft interrupt -80000001 # scause value from s soft interrupt -00000000 # stval for ssoft interrupt (0x0) -00000800 # masked out mstatus.mpp = 1, mstatus.MPIE = 0, and mstatus.MIE = 0 0007ec03 # value to indicate successful vectoring on m soft interrupt 80000003 # scause value from m soft interrupt 00000000 # stval for msoft interrupt (0x0) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S index 4b1e2afa4..85758b101 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/WALLY-trap-s-01.S @@ -57,12 +57,12 @@ GOTO_U_MODE // Causes S mode ecall GOTO_S_MODE // Causes U mode ecall -// some interrupts excluded becaus writing MIP is illegal from S mode -jal cause_s_soft_interrupt +// some interrupts excluded because writing MIP is illegal from S mode and writing SIP is only possible when delegated, which is tested below (priv spec 3.1.9) +//jal cause_s_soft_interrupt jal cause_m_soft_interrupt jal cause_m_time_interrupt li a3, 0x40 // this interrupt involves a time loop waiting for the interrupt to go off. -// since interrupts are not always enabled, +// since interrupts are not always enabled, we need to make it stop after a certain number of loops, which is the number in a3 jal cause_s_ext_interrupt_GPIO li a3, 0x40 jal cause_m_ext_interrupt From 74e0ece8918bf4b541930af87be6414be68c9208 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Wed, 22 Mar 2023 23:18:31 -0700 Subject: [PATCH 226/231] added working tests back into regression --- testbench/tests.vh | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 64b5ca59a..93c1d7ea1 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1852,7 +1852,6 @@ string arch64zbs[] = '{ string wally64priv[] = '{ `WALLYTEST, -// "rv64i_m/privilege/src/BUG66", "rv64i_m/privilege/src/WALLY-csr-permission-s-01.S", "rv64i_m/privilege/src/WALLY-csr-permission-u-01.S", "rv64i_m/privilege/src/WALLY-mie-01.S", @@ -1863,15 +1862,15 @@ string arch64zbs[] = '{ "rv64i_m/privilege/src/WALLY-mtvec-01.S", "rv64i_m/privilege/src/WALLY-pma-01.S", "rv64i_m/privilege/src/WALLY-pmp-01.S", -// "rv64i_m/privilege/src/WALLY-sie-01.S", + "rv64i_m/privilege/src/WALLY-sie-01.S", "rv64i_m/privilege/src/WALLY-status-mie-01.S", -// "rv64i_m/privilege/src/WALLY-status-sie-01.S", + "rv64i_m/privilege/src/WALLY-status-sie-01.S", "rv64i_m/privilege/src/WALLY-status-tw-01.S", "rv64i_m/privilege/src/WALLY-status-tvm-01.S", "rv64i_m/privilege/src/WALLY-status-fp-enabled-01.S", -// "rv64i_m/privilege/src/WALLY-stvec-01.S", -// "rv64i_m/privilege/src/WALLY-trap-01.S", -// "rv64i_m/privilege/src/WALLY-trap-s-01.S", + "rv64i_m/privilege/src/WALLY-stvec-01.S", + "rv64i_m/privilege/src/WALLY-trap-01.S", + "rv64i_m/privilege/src/WALLY-trap-s-01.S", "rv64i_m/privilege/src/WALLY-trap-sret-01.S", "rv64i_m/privilege/src/WALLY-trap-u-01.S", "rv64i_m/privilege/src/WALLY-wfi-01.S", @@ -1951,15 +1950,15 @@ string arch64zbs[] = '{ "rv32i_m/privilege/src/WALLY-mtvec-01.S", "rv32i_m/privilege/src/WALLY-pma-01.S", "rv32i_m/privilege/src/WALLY-pmp-01.S", -// "rv32i_m/privilege/src/WALLY-sie-01.S", + "rv32i_m/privilege/src/WALLY-sie-01.S", "rv32i_m/privilege/src/WALLY-status-mie-01.S", -// "rv32i_m/privilege/src/WALLY-status-sie-01.S", + "rv32i_m/privilege/src/WALLY-status-sie-01.S", "rv32i_m/privilege/src/WALLY-status-tw-01.S", "rv32i_m/privilege/src/WALLY-status-tvm-01.S", "rv32i_m/privilege/src/WALLY-status-fp-enabled-01.S", -// "rv32i_m/privilege/src/WALLY-stvec-01.S", -// "rv32i_m/privilege/src/WALLY-trap-01.S", -// "rv32i_m/privilege/src/WALLY-trap-s-01.S", + "rv32i_m/privilege/src/WALLY-stvec-01.S", + "rv32i_m/privilege/src/WALLY-trap-01.S", + "rv32i_m/privilege/src/WALLY-trap-s-01.S", "rv32i_m/privilege/src/WALLY-trap-sret-01.S", "rv32i_m/privilege/src/WALLY-trap-u-01.S", "rv32i_m/privilege/src/WALLY-wfi-01.S", From 106ed02a7e9749251eba4e19b64742d4a926da70 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Fri, 24 Mar 2023 11:27:41 -0700 Subject: [PATCH 227/231] Revert "added premilinary boundary ccrossing cases" This reverts commit 78701488146e47cee7aee20c35e00ddc9f01d33f. --- .../references/WALLY-pmp-01.reference_output | 8 +----- .../rv64i_m/privilege/src/WALLY-pmp-01.S | 26 +++++++------------ 2 files changed, 10 insertions(+), 24 deletions(-) diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output index 031d87970..ea5a0cb18 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/references/WALLY-pmp-01.reference_output @@ -1,6 +1,6 @@ 0fffffff # Test 12.3.2.2.1: writeback of value written to PMPADDR0 00000000 -20040001 # writeback of value written to PMPADDR1 +20040000 # writeback of value written to PMPADDR1 00000000 2004003f # writeback of value written to PMPADDR2 00000000 @@ -26,12 +26,6 @@ 00000000 00000bad 00000000 -00000005 # read test with access fault when access begins in allowed region and ends in protected NA region -00000000 -00000bad -00000000 -00000007 # write test with access fault when access begins in allowed region and ends in protected TOR region -00000000 00600dbb # read test success from region with L=X=W=R=0 00000000 0000000b # Test 12.3.2.2.3: ecall from going to S mode from M mode diff --git a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S index dcc2a2dc6..fc3864d38 100644 --- a/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S +++ b/tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-pmp-01.S @@ -60,19 +60,18 @@ test_cases: # write pmpaddr regs. Each of these should output the value of the pmpaddr after being written. # | Reg | pmpaddr | pmpcfg | L | A | X | W | R | Comments | -.8byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1B | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | -.8byte 0x1, 0x20040001, write_pmpaddr_1 # | 1 | 0x20040001 | 00 | 0 | OFF | 0 | 0 | 0 | | -.8byte 0x2, 0x2004003F, write_pmpaddr_2 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100004-801000FF R | -.8byte 0x3, 0x20040080, write_pmpaddr_3 # | 3 | 0x20040080 | 16 | 0 | NA4 | 1 | 1 | 0 | 80100200-80100203 XW | -.8byte 0x4, 0x20040081, write_pmpaddr_4 # | 4 | 0x20040081 | 00 | 0 | OFF | 0 | 0 | 0 | | -.8byte 0x5, 0x20040084, write_pmpaddr_5 # | 5 | 0x20040084 | 0C | 0 | TOR | 1 | 0 | 0 | 80100204-80100210 X | -.8byte 0x5, 0x200400C1, write_pmpaddr_6 # | 6 | 0x200400C1 | 90 | 1 | NA4 | 0 | 0 | 0 | 80100304-80100307 locked out | -.8byte 0x6, 0x2004013F, write_pmpaddr_7 # | 7 | 0x2004013F | 18 | 0 | NAPOT | 0 | 0 | 0 | 80100400-801004FF no access | +.8byte 0x0, 0x0FFFFFFF, write_pmpaddr_0 # | 0 | 0x0FFFFFFF | 1F | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW | +.8byte 0x1, 0x20040000, write_pmpaddr_1 # | 1 | 0x20040000 | 00 | 0 | OFF | 0 | 0 | 0 | | +.8byte 0x2, 0x2004003F, write_pmpaddr_2 # | 2 | 0x2004003F | 09 | 0 | TOR | 0 | 0 | 1 | 80100000-801000FF R | +.8byte 0x3, 0x20040080, write_pmpaddr_3 # | 3 | 0x20040080 | 00 | 0 | OFF | 0 | 0 | 0 | | +.8byte 0x4, 0x20040084, write_pmpaddr_4 # | 4 | 0x20040084 | 0C | 0 | TOR | 1 | 0 | 0 | 80100200-80100210 X | +.8byte 0x5, 0x200400C0, write_pmpaddr_5 # | 5 | 0x200400C0 | 90 | 1 | NA4 | 0 | 0 | 0 | 80100300-80100303 locked out | +.8byte 0x6, 0x2004013F, write_pmpaddr_6 # | 6 | 0x2004013F | 18 | 0 | NAPOT | 0 | 0 | 0 | 80100400-801004FF no access | # Pmpaddr 7-14 are all zeroed out in this test, so they don't need writes. .8byte 0xF, 0x2FFFFFFF, write_pmpaddr_15 # | 15 | 0x2FFFFFFF | 1F | 0 | NAPOT | 1 | 1 | 1 | Main mem 80000000-FFFFFFFF RWX| # write pmpcfg regs with the information in the table above. this should also write the value of these registers to the output. -.8byte 0x0, 0x0018900C0009001F, write_pmpcfg_0 # write pmpcfg0, output 0x0018900C0009001B +.8byte 0x0, 0x0018900C0009001F, write_pmpcfg_0 # write pmpcfg0, output 0x0018900C0009001F .8byte 0x2, 0x1F00000000000000, write_pmpcfg_2 # write pmpcfg2, output 0x1F00000000000000 # write known values to memory where W=0. This should be possible since we're in machine mode. @@ -91,14 +90,7 @@ test_cases: # Test 12.3.2.2.2 Machine mode access -.8byte 0x80100304, 0x0, read32_test # access fault to region with L=1, R=0 - -# accesses across PMP region boundaries -.8byte 0x80100300, 0x0, read64_test # access fault when access begins in allowed NA region and goes into protected region. - -.8byte 0x80100000, 0xbad, write64_test # access fault when access begins in allowed TOR region and goes into protected region. -.8byte 0x80100000, 0xbad, write64_test # access fault when access begins in allowed TOR region and goes into protected region. - +.8byte 0x80100300, 0x0, read64_test # access fault to region with L=1, R=0 .8byte 0x80100400, 0x0, read64_test # successful access to region with L=X=W=R=0 # Test 12.3.2.2.3 System mode access From b70ab0fa5aa5ef95df3475db3ad8e623e7e965c5 Mon Sep 17 00:00:00 2001 From: Kevin Kim Date: Fri, 24 Mar 2023 11:52:51 -0700 Subject: [PATCH 228/231] Zero/Sign extend mux in Shifter, Zero extend mux in Bitmanip alu --- src/ieu/alu.sv | 11 ++-------- src/ieu/bmu/bitmanipalu.sv | 7 +++++-- src/ieu/shifter.sv | 43 +++++++++++++++++++------------------- 3 files changed, 28 insertions(+), 33 deletions(-) diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 15328bb2f..c4e0f3906 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -52,19 +52,12 @@ module alu #(parameter WIDTH=32) ( logic LT, LTU; // Less than, Less than unsigned logic Asign, Bsign; // Sign bits of A, B - // *** explain this part better; possibly move into shifter and BMU? - if (WIDTH == 64) begin - mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, CondExtA); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux - end else begin - assign CondExtA = A; - end - // Addition assign CondMaskInvB = SubArith ? ~CondMaskB : CondMaskB; assign {Carry, Sum} = CondShiftA + CondMaskInvB + {{(WIDTH-1){1'b0}}, SubArith}; // Shifts (configurable for rotation) - shifter sh(.A(CondExtA), .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2])); + shifter sh(.A, .Amt(B[`LOG_XLEN-1:0]), .Right(Funct3[2]), .W64, .SubArith, .Y(Shift), .Rotate(BALUControl[2])); // Condition code flags are based on subtraction output Sum = A-B. // Overflow occurs when the numbers being subtracted have the opposite sign @@ -97,7 +90,7 @@ module alu #(parameter WIDTH=32) ( // Final Result B instruction select mux if (`ZBC_SUPPORTED | `ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED) begin : bitmanipalu bitmanipalu #(WIDTH) balu(.A, .B, .W64, .BSelect, .ZBBSelect, - .Funct3, .CompFlags, .BALUControl, .CondExtA, .ALUResult, .FullResult, + .Funct3, .CompFlags, .BALUControl, .ALUResult, .FullResult, .CondMaskB, .CondShiftA, .Result); end else begin assign Result = ALUResult; diff --git a/src/ieu/bmu/bitmanipalu.sv b/src/ieu/bmu/bitmanipalu.sv index 1cf1cd084..07c7e5343 100644 --- a/src/ieu/bmu/bitmanipalu.sv +++ b/src/ieu/bmu/bitmanipalu.sv @@ -37,7 +37,6 @@ module bitmanipalu #(parameter WIDTH=32) ( input logic [2:0] Funct3, // Funct3 field of opcode indicates operation to perform input logic [1:0] CompFlags, // Comparator flags input logic [2:0] BALUControl, // ALU Control signals for B instructions in Execute Stage - input logic [WIDTH-1:0] CondExtA, // A Conditional Extend Intermediary Signal input logic [WIDTH-1:0] ALUResult, FullResult, // ALUResult, FullResult signals output logic [WIDTH-1:0] CondMaskB, // B is conditionally masked for ZBS instructions output logic [WIDTH-1:0] CondShiftA, // A is conditionally shifted for ShAdd instructions @@ -50,6 +49,7 @@ module bitmanipalu #(parameter WIDTH=32) ( logic Mask; // Indicates if it is ZBS instruction logic PreShift; // Inidicates if it is sh1add, sh2add, sh3add instruction logic [1:0] PreShiftAmt; // Amount to Pre-Shift A + logic [WIDTH-1:0] CondZextA; // A Conditional Extend Intermediary Signal // Extract control signals from bitmanip ALUControl. assign {Mask, PreShift} = BALUControl[1:0]; @@ -62,8 +62,11 @@ module bitmanipalu #(parameter WIDTH=32) ( // 0-3 bit Pre-Shift Mux if (`ZBA_SUPPORTED) begin: zbapreshift + if (WIDTH == 64) begin + mux2 #(64) zextmux(A, {{32{1'b0}}, A[31:0]}, W64, CondZextA); + end else assign CondZextA = A; assign PreShiftAmt = Funct3[2:1] & {2{PreShift}}; - assign CondShiftA = CondExtA << (PreShiftAmt); + assign CondShiftA = CondZextA << (PreShiftAmt); end else begin assign PreShiftAmt = 2'b0; assign CondShiftA = A; diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 8dbdf88e4..1c5128be4 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -40,42 +40,41 @@ module shifter ( logic Sign; // Sign bit for sign extension assign Sign = A[`XLEN-1] & SubArith; // sign bit for sign extension - - if (`ZBB_SUPPORTED) begin: rotfunnel - if (`XLEN==32) begin // rv32 with rotates + if (`XLEN==32) begin // rv32 + if (`ZBB_SUPPORTED) begin: rotfunnel32 //rv32 shifter with rotates always_comb // funnel mux case({Right, Rotate}) 2'b00: z = {A[31:0], 31'b0}; 2'b01: z = {A[31:0], A[31:1]}; 2'b10: z = {{31{Sign}}, A[31:0]}; - 2'b11: z = {A[30:0], A}; + 2'b11: z = {A[30:0], A[31:0]}; endcase - assign amttrunc = Amt; // shift amount - end else begin // rv64 with rotates + end else begin: norotfunnel32 //rv32 shifter without rotates + always_comb // funnel mux + if (Right) z = {{31{Sign}}, A[31:0]}; + else z = {A[31:0], 31'b0}; + end + assign amttrunc = Amt; // shift amount + end else begin // rv64 + logic [`XLEN-1:0] A64; + mux3 #(64) extendmux({{32{1'b0}}, A[31:0]}, {{32{A[31]}}, A[31:0]}, A, {~W64, SubArith}, A64); // bottom 32 bits are always A[31:0], so effectively a 32-bit upper mux + if (`ZBB_SUPPORTED) begin: rotfunnel64 // rv64 shifter with rotates // shifter rotate source select mux logic [`XLEN-1:0] RotA; // rotate source mux2 #(`XLEN) rotmux(A, {A[31:0], A[31:0]}, W64, RotA); // W64 rotatons always_comb // funnel mux case ({Right, Rotate}) - 2'b00: z = {A[63:0],{63'b0}}; - 2'b01: z = {RotA, RotA[63:1]}; - 2'b10: z = {{63{Sign}}, A[63:0]}; - 2'b11: z = {RotA[62:0], RotA}; + 2'b00: z = {A64[63:0],{63'b0}}; + 2'b01: z = {RotA[63:0], RotA[63:1]}; + 2'b10: z = {{63{Sign}}, A64[63:0]}; + 2'b11: z = {RotA[62:0], RotA[63:0]}; endcase - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift - end - end else begin: norotfunnel - if (`XLEN==32) begin:shifter // RV32 + end else begin: norotfunnel64 // rv64 shifter without rotates always_comb // funnel mux - if (Right) z = {{31{Sign}}, A[31:0]}; - else z = {A[31:0], 31'b0}; - assign amttrunc = Amt; // shift amount - end else begin:shifter // RV64 - always_comb // funnel mux - if (Right) z = {{63{Sign}}, A[63:0]}; - else z = {A[63:0], {63'b0}}; - assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift + if (Right) z = {{63{Sign}}, A64[63:0]}; + else z = {A64[63:0], {63'b0}}; end + assign amttrunc = W64 ? {1'b0, Amt[4:0]} : Amt; // 32- or 64-bit shift end // Opposite offset for right shifts From b518177a45061492f51dbdc1a57b896dacef77ac Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 15:01:38 -0500 Subject: [PATCH 229/231] Updated EBU to replace tabs with spaces. --- src/ebu/ahbcacheinterface.sv | 12 +++--- src/ebu/ahbinterface.sv | 34 ++++++++-------- src/ebu/buscachefsm.sv | 26 ++++++------ src/ebu/busfsm.sv | 22 +++++------ src/ebu/controllerinputstage.sv | 32 +++++++-------- src/ebu/ebu.sv | 2 - src/ebu/ebufsmarb.sv | 70 ++++++++++++++++----------------- 7 files changed, 96 insertions(+), 102 deletions(-) diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index 7278f4f93..b30a15096 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -35,7 +35,7 @@ module ahbcacheinterface #( parameter LINELEN, // Number of bits in cacheline parameter LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation) )( - input logic HCLK, HRESETn, + input logic HCLK, HRESETn, // bus interface controls input logic HREADY, // AHB peripheral ready output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ @@ -56,7 +56,7 @@ module ahbcacheinterface #( input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch output logic CacheBusAck, // Handshack to $ indicating bus transaction completed output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus - output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase + output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // uncached interface @@ -76,10 +76,10 @@ module ahbcacheinterface #( logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA - logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s + logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data - genvar index; + genvar index; // fetch buffer is made of BEATSPERLINE flip-flops for (index = 0; index < BEATSPERLINE; index++) begin:fetchbuffer @@ -100,7 +100,7 @@ module ahbcacheinterface #( logic [`AHBW-1:0] AHBWordSets [(LLENPOVERAHBW)-1:0]; genvar index; for (index = 0; index < LLENPOVERAHBW; index++) begin:readdatalinesetsmux - assign AHBWordSets[index] = CacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)]; + assign AHBWordSets[index] = CacheReadDataWordM[(index*`AHBW)+`AHBW-1: (index*`AHBW)]; end assign CacheReadDataWordAHB = AHBWordSets[BeatCount[$clog2(LLENPOVERAHBW)-1:0]]; end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0]; @@ -118,5 +118,5 @@ module ahbcacheinterface #( buscachefsm #(BeatCountThreshold, AHBWLOGBWPL) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed, - .HREADY, .HTRANS, .HWRITE, .HBURST); + .HREADY, .HTRANS, .HWRITE, .HBURST); endmodule diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index ff50f54f5..579791032 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -32,29 +32,28 @@ module ahbinterface #( parameter LSU = 0 // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits )( - input logic HCLK, HRESETn, + input logic HCLK, HRESETn, // bus interface - input logic HREADY, // AHB peripheral ready - output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - output logic HWRITE, // AHB 0: Read operation 1: Write operation - input logic [`XLEN-1:0] HRDATA, // AHB read data - output logic [`XLEN-1:0] HWDATA, // AHB write data - output logic [`XLEN/8-1:0] HWSTRB, // AHB byte mask + input logic HREADY, // AHB peripheral ready + output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + output logic HWRITE, // AHB 0: Read operation 1: Write operation + input logic [`XLEN-1:0] HRDATA, // AHB read data + output logic [`XLEN-1:0] HWDATA, // AHB write data + output logic [`XLEN/8-1:0] HWSTRB, // AHB byte mask // lsu/ifu interface - input logic Stall, // Core pipeline is stalled - input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting - input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write - input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word - input logic [`XLEN-1:0] WriteData, // IEU write data for a store - output logic BusStall, // Bus is busy with an in flight memory operation - output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt + input logic Stall, // Core pipeline is stalled + input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting + input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write + input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word + input logic [`XLEN-1:0] WriteData, // IEU write data for a store + output logic BusStall, // Bus is busy with an in flight memory operation + output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer // Register to hold HRDATA after arriving from the bus ); - logic CaptureEn; - - localparam LEN = (LSU ? `XLEN : 32); // 32 bits for IFU, XLEN for LSU + logic CaptureEn; + localparam LEN = (LSU ? `XLEN : 32); // 32 bits for IFU, XLEN for LSU flopen #(LEN) fb(.clk(HCLK), .en(CaptureEn), .d(HRDATA[LEN-1:0]), .q(FetchBuffer)); @@ -70,4 +69,5 @@ module ahbinterface #( busfsm busfsm(.HCLK, .HRESETn, .Flush, .BusRW, .BusCommitted, .Stall, .BusStall, .CaptureEn, .HREADY, .HTRANS, .HWRITE); + endmodule diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index 2f3e99228..508a49ff2 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -81,15 +81,15 @@ module buscachefsm #( else CurrState <= #1 NextState; always_comb begin - case(CurrState) - ADR_PHASE: if (HREADY & |BusRW) NextState = DATA_PHASE; - else if (HREADY & CacheBusRW[0]) NextState = CACHE_WRITEBACK; - else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH; - else NextState = ADR_PHASE; - DATA_PHASE: if(HREADY) NextState = MEM3; - else NextState = DATA_PHASE; - MEM3: if(Stall) NextState = MEM3; - else NextState = ADR_PHASE; + case(CurrState) + ADR_PHASE: if (HREADY & |BusRW) NextState = DATA_PHASE; + else if (HREADY & CacheBusRW[0]) NextState = CACHE_WRITEBACK; + else if (HREADY & CacheBusRW[1]) NextState = CACHE_FETCH; + else NextState = ADR_PHASE; + DATA_PHASE: if(HREADY) NextState = MEM3; + else NextState = DATA_PHASE; + MEM3: if(Stall) NextState = MEM3; + else NextState = ADR_PHASE; CACHE_FETCH: if(HREADY & FinalBeatCount & CacheBusRW[0]) NextState = CACHE_WRITEBACK; else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE; @@ -98,8 +98,8 @@ module buscachefsm #( else if(HREADY & FinalBeatCount & CacheBusRW[1]) NextState = CACHE_FETCH; else if(HREADY & FinalBeatCount & ~|CacheBusRW) NextState = ADR_PHASE; else NextState = CACHE_WRITEBACK; - default: NextState = ADR_PHASE; - endcase + default: NextState = ADR_PHASE; + endcase end // IEU, LSU, and IFU controls @@ -117,8 +117,8 @@ module buscachefsm #( assign CacheAccess = CurrState == CACHE_FETCH | CurrState == CACHE_WRITEBACK; assign BusStall = (CurrState == ADR_PHASE & ((|BusRW) | (|CacheBusRW))) | - //(CurrState == DATA_PHASE & ~BusRW[0]) | // *** replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem. - (CurrState == DATA_PHASE) | + //(CurrState == DATA_PHASE & ~BusRW[0]) | // *** replace the next line with this. Fails uart test but i think it's a test problem not a hardware problem. + (CurrState == DATA_PHASE) | (CurrState == CACHE_FETCH & ~HREADY) | (CurrState == CACHE_WRITEBACK & ~HREADY); assign BusCommitted = CurrState != ADR_PHASE; diff --git a/src/ebu/busfsm.sv b/src/ebu/busfsm.sv index 019708a3d..de1dd7583 100644 --- a/src/ebu/busfsm.sv +++ b/src/ebu/busfsm.sv @@ -57,20 +57,20 @@ module busfsm ( else CurrState <= #1 NextState; always_comb begin - case(CurrState) - ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE; - else NextState = ADR_PHASE; - DATA_PHASE: if(HREADY) NextState = MEM3; - else NextState = DATA_PHASE; - MEM3: if(Stall) NextState = MEM3; - else NextState = ADR_PHASE; - default: NextState = ADR_PHASE; - endcase + case(CurrState) + ADR_PHASE: if(HREADY & |BusRW) NextState = DATA_PHASE; + else NextState = ADR_PHASE; + DATA_PHASE: if(HREADY) NextState = MEM3; + else NextState = DATA_PHASE; + MEM3: if(Stall) NextState = MEM3; + else NextState = ADR_PHASE; + default: NextState = ADR_PHASE; + endcase end assign BusStall = (CurrState == ADR_PHASE & |BusRW) | -// (CurrState == DATA_PHASE & ~BusRW[0]); // possible optimization here. fails uart test, but i'm not sure the failure is valid. - (CurrState == DATA_PHASE); +// (CurrState == DATA_PHASE & ~BusRW[0]); // possible optimization here. fails uart test, but i'm not sure the failure is valid. + (CurrState == DATA_PHASE); assign BusCommitted = CurrState != ADR_PHASE; diff --git a/src/ebu/controllerinputstage.sv b/src/ebu/controllerinputstage.sv index 681f12bc9..7a6c76bb9 100644 --- a/src/ebu/controllerinputstage.sv +++ b/src/ebu/controllerinputstage.sv @@ -36,26 +36,26 @@ module controllerinputstage #( parameter SAVE_ENABLED = 1 // 1: Save manager inputs if Save = 1, 0: Don't save inputs )( - input logic HCLK, - input logic HRESETn, - input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs - input logic Restore, // Restore a saved manager inputs when it is finally granted - input logic Disable, // Supress HREADY to the non-granted manager - output logic Request, // This manager is making a request + input logic HCLK, + input logic HRESETn, + input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs + input logic Restore, // Restore a saved manager inputs when it is finally granted + input logic Disable, // Supress HREADY to the non-granted manager + output logic Request, // This manager is making a request // controller input - input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation - input logic [2:0] HSIZEIn, // Manager input. AHB transaction width - input logic [2:0] HBURSTIn, // Manager input. AHB burst length + input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation + input logic [2:0] HSIZEIn, // Manager input. AHB transaction width + input logic [2:0] HBURSTIn, // Manager input. AHB burst length input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address - output logic HREADYOut, // Indicate to manager the peripherial is not busy and another manager does not have priority + output logic HREADYOut, // Indicate to manager the peripherial is not busy and another manager does not have priority // controller output - output logic [1:0] HTRANSOut, // Aribrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - output logic HWRITEOut, // Aribrated manager transaction. AHB 0: Read operation 1: Write operation - output logic [2:0] HSIZEOut, // Aribrated manager transaction. AHB transaction width - output logic [2:0] HBURSTOut, // Aribrated manager transaction. AHB burst length + output logic [1:0] HTRANSOut, // Aribrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + output logic HWRITEOut, // Aribrated manager transaction. AHB 0: Read operation 1: Write operation + output logic [2:0] HSIZEOut, // Aribrated manager transaction. AHB transaction width + output logic [2:0] HBURSTOut, // Aribrated manager transaction. AHB burst length output logic [`PA_BITS-1:0] HADDROut, // Aribrated manager transaction. AHB address - input logic HREADYIn // Peripherial ready + input logic HREADYIn // Peripherial ready ); logic HWRITESave; diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index d4e87de2a..17ba080fb 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -89,8 +89,6 @@ module ebu ( logic IFUReq; logic LSUReq; - - assign HCLK = clk; assign HRESETn = ~reset; diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index 1990e8f5d..ec1a3d674 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -31,34 +31,33 @@ `include "wally-config.vh" module ebufsmarb ( - input logic HCLK, - input logic HRESETn, + input logic HCLK, + input logic HRESETn, input logic [2:0] HBURST, // AHB burst length - input logic HREADY, + input logic HREADY, - input logic LSUReq, - input logic IFUReq, + input logic LSUReq, + input logic IFUReq, + output logic IFUSave, + output logic IFURestore, + output logic IFUDisable, + output logic IFUSelect, + output logic LSUDisable, + output logic LSUSelect); - output logic IFUSave, - output logic IFURestore, - output logic IFUDisable, - output logic IFUSelect, - output logic LSUDisable, - output logic LSUSelect); - - typedef enum logic [1:0] {IDLE, ARBITRATE} statetype; + typedef enum logic [1:0] {IDLE, ARBITRATE} statetype; statetype CurrState, NextState; - logic both; // Both the LSU and IFU request at the same time - logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration - logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst - logic BeatCntEn; - logic [3:0] BeatCount; // Position within a burst transfer - logic BeatCntReset; - logic [3:0] Threshold; // Number of beats derived from HBURST + logic both; // Both the LSU and IFU request at the same time + logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration + logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst + logic BeatCntEn; + logic [3:0] BeatCount; // Position within a burst transfer + logic BeatCntReset; + logic [3:0] Threshold; // Number of beats derived from HBURST //////////////////////////////////////////////////////////////////////////////////////////////////// // Aribtration scheme @@ -70,8 +69,8 @@ module ebufsmarb ( flopenl #(.TYPE(statetype)) busreg(HCLK, ~HRESETn, 1'b1, NextState, IDLE, CurrState); always_comb case (CurrState) - IDLE: if (both) NextState = ARBITRATE; - else NextState = IDLE; + IDLE: if (both) NextState = ARBITRATE; + else NextState = IDLE; ARBITRATE: if (HREADY & FinalBeatD & ~(LSUReq & IFUReq)) NextState = IDLE; else NextState = ARBITRATE; default: NextState = IDLE; @@ -100,27 +99,24 @@ module ebufsmarb ( assign BeatCntReset = NextState == IDLE; assign FinalBeat = (BeatCount == Threshold); // Detect when we are waiting on the final access. - assign BeatCntEn = (NextState == ARBITRATE) & HREADY; + // Counting the beats in the EBU is only necessary when both the LSU and IFU request concurrently. + // LSU has priority. HREADY serves double duty during a burst transaction. It indicates when the + // beat completes and when the transaction finishes. However there is nothing external to + // differentiate them. The EBU counts the HREADY beats so it knows when to switch to the IFU's + // request. + assign BeatCntEn = (NextState == ARBITRATE) & HREADY; counter #(4) BeatCounter(HCLK, ~HRESETn | BeatCntReset | FinalBeat, BeatCntEn, BeatCount); // Used to store data from data phase of AHB. flopenr #(1) FinalBeatReg(HCLK, ~HRESETn | BeatCntReset, BeatCntEn, FinalBeat, FinalBeatD); - // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST. - // HBURST[2:1] Beats - // 00 1 - // 01 4 - // 10 8 - // 11 16 + // unlike the bus fsm in lsu/ifu, we need to derive the number of beats from HBURST, Threshold = num beats - 1. + // HBURST[2:1] Beats threshold + // 00 1 0 + // 01 4 3 + // 10 8 7 + // 11 16 15 always_comb if (HBURST[2:1] == 2'b00) Threshold = 4'b0000; else Threshold = (2 << HBURST[2:1]) - 1; -/* case(HBURST) - 0: Threshold = 4'b0000; - 3: Threshold = 4'b0011; // INCR4 - 5: Threshold = 4'b0111; // INCR8 - 7: Threshold = 4'b1111; // INCR16 - default: Threshold = 4'b0000; // INCR without end. - endcase - end */ endmodule From b5a58502d06c6cba4b3fb7a43bf74d441b67e101 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 15:15:38 -0500 Subject: [PATCH 230/231] Replaced tabs -> spaces cache. --- src/cache/cache.sv | 22 +++++----- src/cache/cachefsm.sv | 76 +++++++++++++++++------------------ src/cache/cacheway.sv | 14 ++----- src/cache/subcachelineread.sv | 6 +-- src/ebu/buscachefsm.sv | 50 +++++++++++------------ src/ebu/ebu.sv | 37 +++++++++-------- 6 files changed, 98 insertions(+), 107 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 5d4fca7d5..da7f83276 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -98,9 +98,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE logic CacheEn; logic [CACHEWORDSPERLINE-1:0] MemPAdrDecoded; logic [LINELEN/8-1:0] LineByteMask, DemuxedByteMask, FetchBufferByteSel; - logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr; + logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0] WordOffsetAddr; - genvar index; + genvar index; ///////////////////////////////////////////////////////////////////////////////////////////// // Read Path @@ -154,9 +154,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // Bus address for fetch, writeback, or flush writeback mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), - .d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), - .d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}), - .s({SelFlush, SelWriteback}), .y(CacheBusAdr)); + .d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), + .d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}), + .s({SelFlush, SelWriteback}), .y(CacheBusAdr)); ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path @@ -198,11 +198,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE ///////////////////////////////////////////////////////////////////////////////////////////// cachefsm #(READ_ONLY_CACHE) cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, - .FlushStage, .CacheRW, .CacheAtomic, .Stall, - .CacheHit, .LineDirty, .CacheStall, .CacheCommitted, - .CacheMiss, .CacheAccess, .SelAdr, - .ClearValid, .ClearDirty, .SetDirty, .SetValid, .SelWriteback, .SelFlush, - .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst, - .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer, + .FlushStage, .CacheRW, .CacheAtomic, .Stall, + .CacheHit, .LineDirty, .CacheStall, .CacheCommitted, + .CacheMiss, .CacheAccess, .SelAdr, + .ClearValid, .ClearDirty, .SetDirty, .SetValid, .SelWriteback, .SelFlush, + .FlushAdrCntEn, .FlushWayCntEn, .FlushCntRst, + .FlushAdrFlag, .FlushWayFlag, .FlushCache, .SelFetchBuffer, .InvalidateCache, .CacheEn, .LRUWriteEn); endmodule diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 1edb0b65a..c51257be7 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -47,7 +47,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( output logic [1:0] CacheBusRW, // [1] Read (cache line fetch) or [0] write bus (cache line writeback) // performance counter outputs output logic CacheMiss, // Cache miss - output logic CacheAccess, // Cache access + output logic CacheAccess, // Cache access // cache internals input logic CacheHit, // Exactly 1 way hits @@ -69,21 +69,21 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( output logic CacheEn // Enable the cache memory arrays. Disable hold read data constant ); - logic resetDelay; - logic AMO, StoreAMO; - logic AnyUpdateHit, AnyHit; - logic AnyMiss; - logic FlushFlag; + logic resetDelay; + logic AMO, StoreAMO; + logic AnyUpdateHit, AnyHit; + logic AnyMiss; + logic FlushFlag; typedef enum logic [3:0]{STATE_READY, // hit states - // miss states - STATE_FETCH, - STATE_WRITEBACK, - STATE_WRITE_LINE, - STATE_READ_HOLD, // required for back to back reads. structural hazard on writting SRAM - // flush cache - STATE_FLUSH, - STATE_FLUSH_WRITEBACK} statetype; + // miss states + STATE_FETCH, + STATE_WRITEBACK, + STATE_WRITE_LINE, + STATE_READ_HOLD, // required for back to back reads. structural hazard on writting SRAM + // flush cache + STATE_FLUSH, + STATE_FLUSH_WRITEBACK} statetype; statetype CurrState, NextState; @@ -111,26 +111,26 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( always_comb begin NextState = STATE_READY; case (CurrState) - STATE_READY: if(InvalidateCache) NextState = STATE_READY; - else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; - else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; - else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK; - else NextState = STATE_READY; - STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; - else NextState = STATE_FETCH; - STATE_WRITE_LINE: NextState = STATE_READ_HOLD; - STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; - else NextState = STATE_READY; - STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH; - else NextState = STATE_WRITEBACK; + STATE_READY: if(InvalidateCache) NextState = STATE_READY; + else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; + else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; + else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK; + else NextState = STATE_READY; + STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; + else NextState = STATE_FETCH; + STATE_WRITE_LINE: NextState = STATE_READ_HOLD; + STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; + else NextState = STATE_READY; + STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH; + else NextState = STATE_WRITEBACK; // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. - STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK; - else if (FlushFlag) NextState = STATE_READ_HOLD; - else NextState = STATE_FLUSH; - STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH; - else if(CacheBusAck) NextState = STATE_READ_HOLD; - else NextState = STATE_FLUSH_WRITEBACK; - default: NextState = STATE_READY; + STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK; + else if (FlushFlag) NextState = STATE_READ_HOLD; + else NextState = STATE_FLUSH; + STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH; + else if(CacheBusAck) NextState = STATE_READ_HOLD; + else NextState = STATE_FLUSH_WRITEBACK; + default: NextState = STATE_READY; endcase end @@ -156,14 +156,14 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( (CurrState == STATE_READY & AnyMiss & LineDirty); assign SelFlush = (CurrState == STATE_READY & FlushCache) | - (CurrState == STATE_FLUSH) | - (CurrState == STATE_FLUSH_WRITEBACK); + (CurrState == STATE_FLUSH) | + (CurrState == STATE_FLUSH_WRITEBACK); assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) | - (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty); + (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty); assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) | - (CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck); + (CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck); assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) | - (CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck); + (CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck); // Bus interface controls assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | (CurrState == STATE_FETCH & ~CacheBusAck) | diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index da40ab705..d7cc0792d 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -30,7 +30,7 @@ `include "wally-config.vh" module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, - OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) ( + OFFSETLEN = 5, INDEXLEN = 9, READ_ONLY_CACHE = 0) ( input logic clk, input logic reset, input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations) @@ -86,8 +86,6 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, assign SelNonHit = FlushWayEn | SetValid | SelWriteback; mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag); - //assign SelTag = VictimWay | FlushWay; - //assign SelData = HitWay | FlushWayEn | VictimWayEn; mux2 #(1) selectedwaymux(HitWay, SelTag, SelNonHit , SelData); @@ -95,10 +93,6 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, // Write Enable demux ///////////////////////////////////////////////////////////////////////////////////////////// - // RT: Can we merge these two muxes? This is also shared in cacheLRU. - //mux3 #(1) selectwaymux(HitWay, VictimWay, FlushWay, {SelFlush, SetValid}, SelData); - //mux3 #(1) selecteddatamux(HitWay, VictimWay, FlushWay, {SelFlush, SelNonHit}, SelData); - assign SetValidWay = SetValid & SelData; assign ClearValidWay = ClearValid & SelData; assign SetDirtyWay = SetDirty & SelData; @@ -117,8 +111,6 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, .addr(CacheSet), .dout(ReadTag), .bwe('1), .din(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .we(SetValidEN)); - - // AND portion of distributed tag multiplexer assign TagWay = SelTag ? ReadTag : '0; // AND part of AOMux assign DirtyWay = SelTag & Dirty & ValidWay; @@ -152,8 +144,8 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, always_ff @(posedge clk) begin // Valid bit array, if (reset) ValidBits <= #1 '0; if(CacheEn) begin - ValidWay <= #1 ValidBits[CacheSet]; - if(InvalidateCache) ValidBits <= #1 '0; + ValidWay <= #1 ValidBits[CacheSet]; + if(InvalidateCache) ValidBits <= #1 '0; else if (SetValidEN | (ClearValidWay & ~FlushStage)) ValidBits[CacheSet] <= #1 SetValidWay; end end diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index 490618070..58d022a71 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -33,8 +33,8 @@ module subcachelineread #(parameter LINELEN, WORDLEN, parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$ input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address - input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline - output logic [WORDLEN-1:0] ReadDataWord // read data of selected word. + input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline + output logic [WORDLEN-1:0] ReadDataWord // read data of selected word. ); localparam WORDSPERLINE = LINELEN/MUXINTERVAL; @@ -50,7 +50,7 @@ module subcachelineread #(parameter LINELEN, WORDLEN, genvar index; for (index = 0; index < WORDSPERLINE; index++) begin:readdatalinesetsmux - assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1 : (index*MUXINTERVAL)]; + assign ReadDataLineSets[index] = ReadDataLinePad[(index*MUXINTERVAL)+WORDLEN-1 : (index*MUXINTERVAL)]; end // variable input mux diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index 508a49ff2..c619c9135 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -35,33 +35,33 @@ module buscachefsm #( parameter BeatCountThreshold, // Largest beat index parameter AHBWLOGBWPL // Log2 of BEATSPERLINE )( - input logic HCLK, - input logic HRESETn, + input logic HCLK, + input logic HRESETn, // IEU interface - input logic Stall, // Core pipeline is stalled - input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting - input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write - output logic BusStall, // Bus is busy with an in flight memory operation - output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt - - // ahb cache interface locals. - output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA - - // cache interface - input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch - output logic CacheBusAck, // Handshack to $ indicating bus transaction completed + input logic Stall, // Core pipeline is stalled + input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting + input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write + output logic BusStall, // Bus is busy with an in flight memory operation + output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt + + // ahb cache interface locals. + output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA + + // cache interface + input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch + output logic CacheBusAck, // Handshack to $ indicating bus transaction completed // lsu interface output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase output logic [AHBWLOGBWPL-1:0] BeatCountDelayed, // Beat within the cache line in the second (Data) cache stage - output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr + output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // BUS interface - input logic HREADY, // AHB peripheral ready - output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - output logic HWRITE, // AHB 0: Read operation 1: Write operation - output logic [2:0] HBURST // AHB burst length + input logic HREADY, // AHB peripheral ready + output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + output logic HWRITE, // AHB 0: Read operation 1: Write operation + output logic [2:0] HBURST // AHB burst length ); typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype; @@ -70,11 +70,11 @@ module buscachefsm #( busstatetype CurrState, NextState; logic [AHBWLOGBWPL-1:0] NextBeatCount; - logic FinalBeatCount; - logic [2:0] LocalBurstType; - logic BeatCntEn; - logic BeatCntReset; - logic CacheAccess; + logic FinalBeatCount; + logic [2:0] LocalBurstType; + logic BeatCntEn; + logic BeatCntReset; + logic CacheAccess; always_ff @(posedge HCLK) if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; @@ -144,7 +144,7 @@ module buscachefsm #( // communication to cache assign CacheBusAck = (CacheAccess & HREADY & FinalBeatCount); assign SelBusBeat = (CurrState == ADR_PHASE & (BusRW[0] | CacheBusRW[0])) | - (CurrState == DATA_PHASE & BusRW[0]) | + (CurrState == DATA_PHASE & BusRW[0]) | (CurrState == CACHE_WRITEBACK) | (CurrState == CACHE_FETCH); diff --git a/src/ebu/ebu.sv b/src/ebu/ebu.sv index 17ba080fb..b045c6aaa 100644 --- a/src/ebu/ebu.sv +++ b/src/ebu/ebu.sv @@ -52,27 +52,26 @@ module ebu ( output logic LSUHREADY, // AHB peripheral. Never gated as LSU always has priority // AHB-Lite external signals - output logic HCLK, HRESETn, - input logic HREADY, // AHB peripheral ready - input logic HRESP, // AHB peripheral response. 0: OK 1: Error - output logic [`PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration - output logic [`AHBW-1:0] HWDATA, // AHB Write data after arbitration - output logic [`XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration - output logic HWRITE, // AHB transaction direction after arbitration - output logic [2:0] HSIZE, // AHB transaction size after arbitration - output logic [2:0] HBURST, // AHB burst length after arbitration - output logic [3:0] HPROT, // AHB protection. Wally does not use - output logic [1:0] HTRANS, // AHB transaction request after arbitration - output logic HMASTLOCK // AHB master lock. Wally does not use + output logic HCLK, HRESETn, + input logic HREADY, // AHB peripheral ready + input logic HRESP, // AHB peripheral response. 0: OK 1: Error + output logic [`PA_BITS-1:0] HADDR, // AHB address to peripheral after arbitration + output logic [`AHBW-1:0] HWDATA, // AHB Write data after arbitration + output logic [`XLEN/8-1:0] HWSTRB, // AHB byte write enables after arbitration + output logic HWRITE, // AHB transaction direction after arbitration + output logic [2:0] HSIZE, // AHB transaction size after arbitration + output logic [2:0] HBURST, // AHB burst length after arbitration + output logic [3:0] HPROT, // AHB protection. Wally does not use + output logic [1:0] HTRANS, // AHB transaction request after arbitration + output logic HMASTLOCK // AHB master lock. Wally does not use ); - logic LSUDisable; - logic LSUSelect; + logic LSUSelect; logic IFUSave; - logic IFURestore; - logic IFUDisable; - logic IFUSelect; + logic IFURestore; + logic IFUDisable; + logic IFUSelect; logic [`PA_BITS-1:0] IFUHADDROut; logic [1:0] IFUHTRANSOut; @@ -87,7 +86,7 @@ module ebu ( logic LSUHWRITEOut; logic IFUReq; - logic LSUReq; + logic LSUReq; assign HCLK = clk; assign HRESETn = ~reset; @@ -127,7 +126,7 @@ module ebu ( // HRDATA is sent to all controllers at the core level. ebufsmarb ebufsmarb(.HCLK, .HRESETn, .HBURST, .HREADY, .LSUReq, .IFUReq, .IFUSave, - .IFURestore, .IFUDisable, .IFUSelect, .LSUDisable, .LSUSelect); + .IFURestore, .IFUDisable, .IFUSelect, .LSUDisable, .LSUSelect); endmodule From 46b1bca4fc892329ea0d9bbe0e278e0415b61037 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Fri, 24 Mar 2023 17:32:25 -0500 Subject: [PATCH 231/231] Fixed all tap/space issue in RTL. --- src/fpu/fctrl.sv | 80 +++--- src/fpu/fcvt.sv | 28 +- src/fpu/fdivsqrt/fdivsqrt.sv | 76 +++--- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 14 +- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 50 ++-- src/fpu/fdivsqrt/fdivsqrtqsel2.sv | 6 +- src/fpu/fdivsqrt/fdivsqrtqsel4.sv | 22 +- src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv | 20 +- src/fpu/fdivsqrt/fdivsqrtstage2.sv | 34 +-- src/fpu/fdivsqrt/fdivsqrtstage4.sv | 42 +-- src/fpu/fma/fmalza.sv | 4 +- src/fpu/fpu.sv | 222 ++++++++-------- src/fpu/fregfile.sv | 6 +- src/fpu/fsgninj.sv | 54 ++-- src/generic/arrs.sv | 8 +- src/generic/clockgater.sv | 10 +- src/generic/mem/ram1p1rwbe.sv | 63 +++-- src/generic/mem/ram1p1rwbe_64x128.sv | 2 +- src/generic/mem/ram1p1rwbe_64x22.sv | 2 +- src/generic/mem/ram1p1rwbe_64x44.sv | 2 +- src/generic/mem/ram2p1r1wbe.sv | 152 ++++++----- src/generic/mem/ram2p1r1wbe_1024x36.sv | 10 +- src/generic/mem/ram2p1r1wbe_1024x68.sv | 8 +- src/generic/mem/ram2p1r1wbe_128x64.sv | 8 +- src/generic/mem/ram2p1r1wbe_512x64.sv | 8 +- src/generic/mem/ram2p1r1wbe_64x32.sv | 8 +- src/generic/mem/rom1p1r.sv | 94 +++---- src/generic/mem/rom1p1r_128x32.sv | 2 +- src/generic/mem/rom1p1r_128x64.sv | 6 +- src/ieu/bmu/bmuctrl.sv | 8 +- src/ieu/controller.sv | 66 ++--- src/ieu/datapath.sv | 4 +- src/ieu/forward.sv | 2 +- src/ieu/ieu.sv | 34 +-- src/ieu/regfile.sv | 2 +- src/ifu/bpred/RASPredictor.sv | 24 +- src/ifu/bpred/bpred.sv | 88 +++--- src/ifu/bpred/btb.sv | 33 ++- src/ifu/bpred/gshare.sv | 38 +-- src/ifu/bpred/gsharebasic.sv | 20 +- src/ifu/bpred/icpred.sv | 12 +- src/ifu/ifu.sv | 196 +++++++------- src/ifu/irom.sv | 14 +- src/ifu/spill.sv | 37 +-- src/lsu/dtim.sv | 12 +- src/lsu/lrsc.sv | 12 +- src/lsu/lsu.sv | 108 ++++---- src/lsu/subwordread.sv | 34 +-- src/mdu/div.sv | 4 +- src/mdu/mdu.sv | 100 +++---- src/mmu/hptw.sv | 354 ++++++++++++------------- src/mmu/tlb/tlb.sv | 6 +- src/privileged/csr.sv | 14 +- src/privileged/csrc.sv | 90 +++---- src/privileged/csri.sv | 10 +- src/privileged/csrm.sv | 42 +-- src/privileged/csrs.sv | 38 +-- src/privileged/csrsr.sv | 2 +- src/privileged/csru.sv | 2 +- src/privileged/privileged.sv | 160 +++++------ src/privileged/trap.sv | 50 ++-- src/uncore/clint_apb.sv | 2 +- src/uncore/plic_apb.sv | 50 ++-- src/uncore/ram_ahb.sv | 45 ++-- src/uncore/uartPC16550D.sv | 146 +++++----- src/uncore/uncore.sv | 106 ++++---- src/wally/wallypipelinedcore.sv | 76 +++--- src/wally/wallypipelinedsoc.sv | 56 ++-- 68 files changed, 1561 insertions(+), 1577 deletions(-) diff --git a/src/fpu/fctrl.sv b/src/fpu/fctrl.sv index 5700e1b6a..be10e8007 100755 --- a/src/fpu/fctrl.sv +++ b/src/fpu/fctrl.sv @@ -31,53 +31,53 @@ module fctrl ( input logic clk, input logic reset, // input control signals - input logic StallE, StallM, StallW, // stall signals - input logic FlushE, FlushM, FlushW, // flush signals - input logic IntDivE, // is inteteger division - input logic [2:0] FRM_REGW, // rounding mode from CSR - input logic [1:0] STATUS_FS, // is FPU enabled? - input logic FDivBusyE, // is the divider busy - // intruction - input logic [31:0] InstrD, // the full instruction - input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision - input logic [6:0] OpD, // bits 6:0 of instruction - input logic [4:0] Rs2D, // bits 24:20 of instruction - input logic [2:0] Funct3D, Funct3E, // bits 14:12 of instruction - may contain rounding mode - // input mux selections - output logic XEnD, YEnD, ZEnD, // enable inputs - output logic XEnE, YEnE, ZEnE, // enable inputs - // opperation mux selections - output logic FCvtIntE, FCvtIntW, // convert to integer opperation - output logic [2:0] FrmM, // FP rounding mode - output logic [`FMTBITS-1:0] FmtE, FmtM, // FP format - output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component - output logic FpLoadStoreM, // FP load or store instruction - output logic [1:0] PostProcSelE, PostProcSelM, // select result in the post processing unit - output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage + input logic StallE, StallM, StallW, // stall signals + input logic FlushE, FlushM, FlushW, // flush signals + input logic IntDivE, // is inteteger division + input logic [2:0] FRM_REGW, // rounding mode from CSR + input logic [1:0] STATUS_FS, // is FPU enabled? + input logic FDivBusyE, // is the divider busy + // intruction + input logic [31:0] InstrD, // the full instruction + input logic [6:0] Funct7D, // bits 31:25 of instruction - may contain percision + input logic [6:0] OpD, // bits 6:0 of instruction + input logic [4:0] Rs2D, // bits 24:20 of instruction + input logic [2:0] Funct3D, Funct3E, // bits 14:12 of instruction - may contain rounding mode + // input mux selections + output logic XEnD, YEnD, ZEnD, // enable inputs + output logic XEnE, YEnE, ZEnE, // enable inputs + // opperation mux selections + output logic FCvtIntE, FCvtIntW, // convert to integer opperation + output logic [2:0] FrmM, // FP rounding mode + output logic [`FMTBITS-1:0] FmtE, FmtM, // FP format + output logic [2:0] OpCtrlE, OpCtrlM, // Select which opperation to do in each component + output logic FpLoadStoreM, // FP load or store instruction + output logic [1:0] PostProcSelE, PostProcSelM, // select result in the post processing unit + output logic [1:0] FResSelE, FResSelM, FResSelW, // Select one of the results that finish in the memory stage // register control signals - output logic FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable - output logic FWriteIntE, FWriteIntM, // Write to integer register - output logic [4:0] Adr1D, Adr2D, Adr3D, // adresses of each input - output logic [4:0] Adr1E, Adr2E, Adr3E, // adresses of each input + output logic FRegWriteE, FRegWriteM, FRegWriteW, // FP register write enable + output logic FWriteIntE, FWriteIntM, // Write to integer register + output logic [4:0] Adr1D, Adr2D, Adr3D, // adresses of each input + output logic [4:0] Adr1E, Adr2E, Adr3E, // adresses of each input // other control signals output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction - output logic FDivStartE, IDivStartE // Start division or squareroot + output logic FDivStartE, IDivStartE // Start division or squareroot ); `define FCTRLW 12 - logic [`FCTRLW-1:0] ControlsD; // control signals - logic FRegWriteD; // FP register write enable - logic FDivStartD; // start division/sqrt - logic FWriteIntD; // integer register write enable - logic [2:0] OpCtrlD; // Select which opperation to do in each component - logic [1:0] PostProcSelD; // select result in the post processing unit - logic [1:0] FResSelD; // Select one of the results that finish in the memory stage - logic [2:0] FrmD, FrmE; // FP rounding mode - logic [`FMTBITS-1:0] FmtD; // FP format - logic [1:0] Fmt; // format - before possible reduction - logic SupportedFmt; // is the format supported - logic FCvtIntD, FCvtIntM; // convert to integer opperation + logic [`FCTRLW-1:0] ControlsD; // control signals + logic FRegWriteD; // FP register write enable + logic FDivStartD; // start division/sqrt + logic FWriteIntD; // integer register write enable + logic [2:0] OpCtrlD; // Select which opperation to do in each component + logic [1:0] PostProcSelD; // select result in the post processing unit + logic [1:0] FResSelD; // Select one of the results that finish in the memory stage + logic [2:0] FrmD, FrmE; // FP rounding mode + logic [`FMTBITS-1:0] FmtD; // FP format + logic [1:0] Fmt; // format - before possible reduction + logic SupportedFmt; // is the format supported + logic FCvtIntD, FCvtIntM; // convert to integer opperation // FPU Instruction Decoder assign Fmt = Funct7D[1:0]; diff --git a/src/fpu/fcvt.sv b/src/fpu/fcvt.sv index 2f121a75a..32ca7542f 100644 --- a/src/fpu/fcvt.sv +++ b/src/fpu/fcvt.sv @@ -30,20 +30,20 @@ `include "wally-config.vh" module fcvt ( - input logic Xs, // input's sign - input logic [`NE-1:0] Xe, // input's exponent - input logic [`NF:0] Xm, // input's fraction - input logic [`XLEN-1:0] Int, // integer input - from IEU - input logic [2:0] OpCtrl, // choose which opperation (look below for values) - input logic ToInt, // is fp->int (since it's writting to the integer register) - input logic XZero, // is the input zero - input logic [`FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half) - output logic [`NE:0] Ce, // the calculated expoent - output logic [`LOGCVTLEN-1:0] ShiftAmt, // how much to shift by + input logic Xs, // input's sign + input logic [`NE-1:0] Xe, // input's exponent + input logic [`NF:0] Xm, // input's fraction + input logic [`XLEN-1:0] Int, // integer input - from IEU + input logic [2:0] OpCtrl, // choose which opperation (look below for values) + input logic ToInt, // is fp->int (since it's writting to the integer register) + input logic XZero, // is the input zero + input logic [`FMTBITS-1:0] Fmt, // the input's precision (11=quad 01=double 00=single 10=half) + output logic [`NE:0] Ce, // the calculated expoent + output logic [`LOGCVTLEN-1:0] ShiftAmt, // how much to shift by output logic ResSubnormUf,// does the result underflow or is subnormal - output logic Cs, // the result's sign - output logic IntZero, // is the integer zero? - output logic [`CVTLEN-1:0] LzcIn // input to the Leading Zero Counter (priority encoder) + output logic Cs, // the result's sign + output logic IntZero, // is the integer zero? + output logic [`CVTLEN-1:0] LzcIn // input to the Leading Zero Counter (priority encoder) ); // OpCtrls: @@ -60,7 +60,7 @@ module fcvt ( logic [`XLEN-1:0] PosInt; // the positive integer input logic [`XLEN-1:0] TrimInt; // integer trimmed to the correct size logic [`NE-2:0] NewBias; // the bias of the final result - logic [`NE-1:0] OldExp; // the old exponent + logic [`NE-1:0] OldExp; // the old exponent logic Signed; // is the opperation with a signed integer? logic Int64; // is the integer 64 bits? logic IntToFp; // is the opperation an int->fp conversion? diff --git a/src/fpu/fdivsqrt/fdivsqrt.sv b/src/fpu/fdivsqrt/fdivsqrt.sv index c69618f43..92f64cbdc 100644 --- a/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/src/fpu/fdivsqrt/fdivsqrt.sv @@ -29,49 +29,49 @@ `include "wally-config.vh" module fdivsqrt( - input logic clk, - input logic reset, + input logic clk, + input logic reset, input logic [`FMTBITS-1:0] FmtE, - input logic XsE, - input logic [`NF:0] XmE, YmE, - input logic [`NE-1:0] XeE, YeE, - input logic XInfE, YInfE, - input logic XZeroE, YZeroE, - input logic XNaNE, YNaNE, - input logic FDivStartE, IDivStartE, - input logic StallM, - input logic FlushE, - input logic SqrtE, SqrtM, - input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B - input logic [2:0] Funct3E, Funct3M, - input logic IntDivE, W64E, - output logic DivStickyM, - output logic FDivBusyE, IFDivStartE, FDivDoneE, - output logic [`NE+1:0] QeM, - output logic [`DIVb:0] QmM, - output logic [`XLEN-1:0] FIntDivResultM + input logic XsE, + input logic [`NF:0] XmE, YmE, + input logic [`NE-1:0] XeE, YeE, + input logic XInfE, YInfE, + input logic XZeroE, YZeroE, + input logic XNaNE, YNaNE, + input logic FDivStartE, IDivStartE, + input logic StallM, + input logic FlushE, + input logic SqrtE, SqrtM, + input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B + input logic [2:0] Funct3E, Funct3M, + input logic IntDivE, W64E, + output logic DivStickyM, + output logic FDivBusyE, IFDivStartE, FDivDoneE, + output logic [`NE+1:0] QeM, + output logic [`DIVb:0] QmM, + output logic [`XLEN-1:0] FIntDivResultM ); // Floating-point division and square root module, with optional integer division and remainder // Computes X/Y, sqrt(X), A/B, or A%B - logic [`DIVb+3:0] WS, WC; // Partial remainder components - logic [`DIVb+3:0] X; // Iterator Initial Value (from dividend) - logic [`DIVb-1:0] DPreproc, D; // Iterator Divisor - logic [`DIVb:0] FirstU, FirstUM; // Intermediate result values - logic [`DIVb+1:0] FirstC; // Step tracker - logic Firstun; // Quotient selection - logic WZeroE; // Early termination flag - logic SpecialCaseM; // Divide by zero, square root of negative, etc. - logic DivStartE; // Enable signal for flops during stall - - // Integer div/rem signals - logic BZeroM; // Denominator is zero - logic IntDivM; // Integer operation - logic [`DIVBLEN:0] nE, nM, mM; // Shift amounts - logic NegQuotM, ALTBM, AsM, W64M; // Special handling for postprocessor - logic [`XLEN-1:0] AM; // Original Numerator for postprocessor - logic ISpecialCaseE; // Integer div/remainder special cases + logic [`DIVb+3:0] WS, WC; // Partial remainder components + logic [`DIVb+3:0] X; // Iterator Initial Value (from dividend) + logic [`DIVb-1:0] DPreproc, D; // Iterator Divisor + logic [`DIVb:0] FirstU, FirstUM; // Intermediate result values + logic [`DIVb+1:0] FirstC; // Step tracker + logic Firstun; // Quotient selection + logic WZeroE; // Early termination flag + logic SpecialCaseM; // Divide by zero, square root of negative, etc. + logic DivStartE; // Enable signal for flops during stall + + // Integer div/rem signals + logic BZeroM; // Denominator is zero + logic IntDivM; // Integer operation + logic [`DIVBLEN:0] nE, nM, mM; // Shift amounts + logic NegQuotM, ALTBM, AsM, W64M; // Special handling for postprocessor + logic [`XLEN-1:0] AM; // Original Numerator for postprocessor + logic ISpecialCaseE; // Integer div/remainder special cases fdivsqrtpreproc fdivsqrtpreproc( // Preprocessor .clk, .IFDivStartE, .Xm(XmE), .Ym(YmE), .Xe(XeE), .Ye(YeE), @@ -100,4 +100,4 @@ module fdivsqrt( // Int-specific .nM, .mM, .ALTBM, .AsM, .BZeroM, .NegQuotM, .W64M, .RemOpM(Funct3M[1]), .AM, .FIntDivResultM); -endmodule \ No newline at end of file +endmodule diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index b09e9f385..7b92f8c83 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -37,7 +37,7 @@ module fdivsqrtpostproc( input logic [`DIVb+1:0] FirstC, input logic SqrtE, input logic Firstun, SqrtM, SpecialCaseM, NegQuotM, - input logic [`XLEN-1:0] AM, + input logic [`XLEN-1:0] AM, input logic RemOpM, ALTBM, BZeroM, AsM, W64M, input logic [`DIVBLEN:0] nM, mM, output logic [`DIVb:0] QmM, @@ -46,11 +46,11 @@ module fdivsqrtpostproc( output logic [`XLEN-1:0] FIntDivResultM ); - logic [`DIVb+3:0] W, Sum, DM; - logic [`DIVb:0] PreQmM; - logic NegStickyM; - logic weq0E, WZeroM; - logic [`XLEN-1:0] IntDivResultM; + logic [`DIVb+3:0] W, Sum, DM; + logic [`DIVb:0] PreQmM; + logic NegStickyM; + logic weq0E, WZeroM; + logic [`XLEN-1:0] IntDivResultM; ////////////////////////// // Execute Stage: Detect early termination for an exact result @@ -134,4 +134,4 @@ module fdivsqrtpostproc( end else assign FIntDivResultM = IntDivResultM[`XLEN-1:0]; end -endmodule \ No newline at end of file +endmodule diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index c5485c26f..9a69085fd 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -29,35 +29,35 @@ `include "wally-config.vh" module fdivsqrtpreproc ( - input logic clk, - input logic IFDivStartE, - input logic [`NF:0] Xm, Ym, - input logic [`NE-1:0] Xe, Ye, + input logic clk, + input logic IFDivStartE, + input logic [`NF:0] Xm, Ym, + input logic [`NE-1:0] Xe, Ye, input logic [`FMTBITS-1:0] Fmt, - input logic Sqrt, - input logic XZeroE, - input logic [2:0] Funct3E, - output logic [`NE+1:0] QeM, - output logic [`DIVb+3:0] X, - output logic [`DIVb-1:0] DPreproc, + input logic Sqrt, + input logic XZeroE, + input logic [2:0] Funct3E, + output logic [`NE+1:0] QeM, + output logic [`DIVb+3:0] X, + output logic [`DIVb-1:0] DPreproc, // Int-specific - input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B - input logic IntDivE, W64E, - output logic ISpecialCaseE, - output logic [`DIVBLEN:0] nE, nM, mM, - output logic NegQuotM, ALTBM, IntDivM, W64M, - output logic AsM, BZeroM, - output logic [`XLEN-1:0] AM + input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B + input logic IntDivE, W64E, + output logic ISpecialCaseE, + output logic [`DIVBLEN:0] nE, nM, mM, + output logic NegQuotM, ALTBM, IntDivM, W64M, + output logic AsM, BZeroM, + output logic [`XLEN-1:0] AM ); - logic [`DIVb-1:0] XPreproc; - logic [`DIVb:0] PreSqrtX; - logic [`DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed - logic [`NE+1:0] QeE; // Quotient Exponent (FP only) - logic [`DIVb-1:0] IFNormLenX, IFNormLenD; // Correctly-sized inputs for iterator - logic [`DIVBLEN:0] mE, ell; // Leading zeros of inputs - logic NumerZeroE; // Numerator is zero (X or A) - logic AZeroE, BZeroE; // A or B is Zero for integer division + logic [`DIVb-1:0] XPreproc; + logic [`DIVb:0] PreSqrtX; + logic [`DIVb+3:0] DivX, DivXShifted, SqrtX, PreShiftX; // Variations of dividend, to be muxed + logic [`NE+1:0] QeE; // Quotient Exponent (FP only) + logic [`DIVb-1:0] IFNormLenX, IFNormLenD; // Correctly-sized inputs for iterator + logic [`DIVBLEN:0] mE, ell; // Leading zeros of inputs + logic NumerZeroE; // Numerator is zero (X or A) + logic AZeroE, BZeroE; // A or B is Zero for integer division if (`IDIV_ON_FPU) begin:intpreproc // Int Supported logic signedDiv, NegQuotE; diff --git a/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv index f18b31f1b..fd0a2a469 100644 --- a/src/fpu/fdivsqrt/fdivsqrtqsel2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv @@ -45,11 +45,11 @@ module fdivsqrtqsel2 ( assign g = ps & pc; assign magnitude = ~((ps[2]^pc[2]) & (ps[1]^pc[1]) & - (ps[0]^pc[0])); + (ps[0]^pc[0])); assign sign = (ps[3]^pc[3])^ (ps[2] & pc[2] | ((ps[2]^pc[2]) & - (ps[1]&pc[1] | ((ps[1]^pc[1]) & - (ps[0]&pc[0]))))); + (ps[1]&pc[1] | ((ps[1]^pc[1]) & + (ps[0]&pc[0]))))); // Produce digit = +1, 0, or -1 assign up = magnitude & ~sign; diff --git a/src/fpu/fdivsqrt/fdivsqrtqsel4.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4.sv index 3a8a110f0..7a0db24d8 100644 --- a/src/fpu/fdivsqrt/fdivsqrtqsel4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtqsel4.sv @@ -32,21 +32,21 @@ module fdivsqrtqsel4 ( input logic [2:0] Dmsbs, input logic [4:0] Smsbs, input logic [7:0] WSmsbs, WCmsbs, - input logic Sqrt, j1, + input logic Sqrt, j1, output logic [3:0] udigit ); - logic [6:0] Wmsbs; - logic [7:0] PreWmsbs; - logic [2:0] A; + logic [6:0] Wmsbs; + logic [7:0] PreWmsbs; + logic [2:0] A; - assign PreWmsbs = WCmsbs + WSmsbs; - assign Wmsbs = PreWmsbs[7:1]; - // D = 0001.xxx... - // Dmsbs = | | + assign PreWmsbs = WCmsbs + WSmsbs; + assign Wmsbs = PreWmsbs[7:1]; + // D = 0001.xxx... + // Dmsbs = | | // W = xxxx.xxx... - // Wmsbs = | | + // Wmsbs = | | - logic [3:0] USel4[1023:0]; + logic [3:0] USel4[1023:0]; // Prepopulate selection table; this is constant at compile time always_comb begin @@ -109,5 +109,5 @@ module fdivsqrtqsel4 ( end else A = Dmsbs; // Select quotient digit from lookup table based on A and W - assign udigit = USel4[{A,Wmsbs}]; + assign udigit = USel4[{A,Wmsbs}]; endmodule diff --git a/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv b/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv index 882458106..e508a6d7c 100644 --- a/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv +++ b/src/fpu/fdivsqrt/fdivsqrtqsel4cmp.sv @@ -32,19 +32,19 @@ module fdivsqrtqsel4cmp ( input logic [2:0] Dmsbs, input logic [4:0] Smsbs, input logic [7:0] WSmsbs, WCmsbs, - input logic SqrtE, j1, + input logic SqrtE, j1, output logic [3:0] udigit ); - logic [6:0] Wmsbs; - logic [7:0] PreWmsbs; - logic [2:0] A; + logic [6:0] Wmsbs; + logic [7:0] PreWmsbs; + logic [2:0] A; - assign PreWmsbs = WCmsbs + WSmsbs; - assign Wmsbs = PreWmsbs[7:1]; - // D = 0001.xxx... - // Dmsbs = | | + assign PreWmsbs = WCmsbs + WSmsbs; + assign Wmsbs = PreWmsbs[7:1]; + // D = 0001.xxx... + // Dmsbs = | | // W = xxxx.xxx... - // Wmsbs = | | + // Wmsbs = | | logic [6:0] mk2, mk1, mk0, mkm1; logic [6:0] mks2[7:0], mks1[7:0]; @@ -87,5 +87,5 @@ module fdivsqrtqsel4cmp ( else if ($signed(Wmsbs) >= $signed(mk1)) udigit = 4'b0100; // choose 1 else if ($signed(Wmsbs) >= $signed(mk0)) udigit = 4'b0000; // choose 0 else if ($signed(Wmsbs) >= $signed(mkm1)) udigit = 4'b0010; // choose -1 - else udigit = 4'b0001; // choose -2 + else udigit = 4'b0001; // choose -2 endmodule diff --git a/src/fpu/fdivsqrt/fdivsqrtstage2.sv b/src/fpu/fdivsqrt/fdivsqrtstage2.sv index 63ab6c059..53c1711cb 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage2.sv @@ -31,32 +31,32 @@ /* verilator lint_off UNOPTFLAT */ module fdivsqrtstage2 ( input logic [`DIVb-1:0] D, - input logic [`DIVb+3:0] DBar, - input logic [`DIVb:0] U, UM, - input logic [`DIVb+3:0] WS, WC, + input logic [`DIVb+3:0] DBar, + input logic [`DIVb:0] U, UM, + input logic [`DIVb+3:0] WS, WC, input logic [`DIVb+1:0] C, - input logic SqrtE, - output logic un, + input logic SqrtE, + output logic un, output logic [`DIVb+1:0] CNext, - output logic [`DIVb:0] UNext, UMNext, - output logic [`DIVb+3:0] WSNext, WCNext + output logic [`DIVb:0] UNext, UMNext, + output logic [`DIVb+3:0] WSNext, WCNext ); /* verilator lint_on UNOPTFLAT */ - logic [`DIVb+3:0] Dsel; - logic up, uz; - logic [`DIVb+3:0] F; - logic [`DIVb+3:0] AddIn; - logic [`DIVb+3:0] WSA, WCA; + logic [`DIVb+3:0] Dsel; + logic up, uz; + logic [`DIVb+3:0] F; + logic [`DIVb+3:0] AddIn; + logic [`DIVb+3:0] WSA, WCA; // Qmient Selection logic // Given partial remainder, select digit of +1, 0, or -1 (up, uz, un) // q encoding: - // 1000 = +2 - // 0100 = +1 - // 0000 = 0 - // 0010 = -1 - // 0001 = -2 + // 1000 = +2 + // 0100 = +1 + // 0000 = 0 + // 0010 = -1 + // 0001 = -2 fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], up, uz, un); // Sqrt F generation. Extend C, U, UM to Q4.k diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv index 007dd18bb..ee92d263b 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -30,34 +30,34 @@ module fdivsqrtstage4 ( input logic [`DIVb-1:0] D, - input logic [`DIVb+3:0] DBar, D2, DBar2, - input logic [`DIVb:0] U, UM, - input logic [`DIVb+3:0] WS, WC, + input logic [`DIVb+3:0] DBar, D2, DBar2, + input logic [`DIVb:0] U,UM, + input logic [`DIVb+3:0] WS, WC, input logic [`DIVb+1:0] C, - input logic SqrtE, j1, + input logic SqrtE, j1, output logic [`DIVb+1:0] CNext, - output logic un, - output logic [`DIVb:0] UNext, UMNext, - output logic [`DIVb+3:0] WSNext, WCNext + output logic un, + output logic [`DIVb:0] UNext, UMNext, + output logic [`DIVb+3:0] WSNext, WCNext ); - logic [`DIVb+3:0] Dsel; - logic [3:0] udigit; - logic [`DIVb+3:0] F; - logic [`DIVb+3:0] AddIn; - logic [4:0] Smsbs; - logic [2:0] Dmsbs; - logic [7:0] WCmsbs, WSmsbs; - logic CarryIn; - logic [`DIVb+3:0] WSA, WCA; + logic [`DIVb+3:0] Dsel; + logic [3:0] udigit; + logic [`DIVb+3:0] F; + logic [`DIVb+3:0] AddIn; + logic [4:0] Smsbs; + logic [2:0] Dmsbs; + logic [7:0] WCmsbs, WSmsbs; + logic CarryIn; + logic [`DIVb+3:0] WSA, WCA; // Digit Selection logic // u encoding: - // 1000 = +2 - // 0100 = +1 - // 0000 = 0 - // 0010 = -1 - // 0001 = -2 + // 1000 = +2 + // 0100 = +1 + // 0000 = 0 + // 0010 = -1 + // 0001 = -2 assign Smsbs = U[`DIVb:`DIVb-4]; assign Dmsbs = D[`DIVb-1:`DIVb-3]; assign WCmsbs = WC[`DIVb+3:`DIVb-4]; diff --git a/src/fpu/fma/fmalza.sv b/src/fpu/fma/fmalza.sv index 640e4ed80..59fb3fc3e 100644 --- a/src/fpu/fma/fmalza.sv +++ b/src/fpu/fma/fmalza.sv @@ -32,12 +32,12 @@ module fmalza #(WIDTH) ( input logic [WIDTH-1:0] A, // addend input logic [2*`NF+1:0] Pm, // product - input logic Cin, // carry in + input logic Cin, // carry in input logic sub, // subtraction output logic [$clog2(WIDTH+1)-1:0] SCnt // normalization shift count for the positive result ); - logic [WIDTH:0] F; // most significant bit of F indicates leading digit + logic [WIDTH:0] F; // most significant bit of F indicates leading digit logic [WIDTH-1:0] B; // zero-extended product with same size as aligned A logic [WIDTH-1:0] P, G, K; // propagate, generate, kill for each column logic [WIDTH-1:0] Pp1, Gm1, Km1; // propagate shifted right by 1, generate/kill shifted left 1 diff --git a/src/fpu/fpu.sv b/src/fpu/fpu.sv index 8ff36fbfc..32bdfc1ca 100755 --- a/src/fpu/fpu.sv +++ b/src/fpu/fpu.sv @@ -29,40 +29,40 @@ `include "wally-config.vh" module fpu ( - input logic clk, - input logic reset, + input logic clk, + input logic reset, // Hazards - input logic StallE, StallM, StallW, // stall signals (from HZU) - input logic FlushE, FlushM, FlushW, // flush signals (from HZU) - output logic FPUStallD, // Stall the decode stage (To HZU) - output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) (to HZU) - // CSRs - input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit) - input logic [2:0] FRM_REGW, // Rounding mode (from CSR) - // Decode stage - input logic [31:0] InstrD, // instruction (from IFU) - // Execute stage - input logic [2:0] Funct3E, // Funct fields of instruction specify type of operations - input logic IntDivE, W64E, // Integer division on FPU - input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input for convert, move, and int div (from IEU) - input logic [4:0] RdE, // which FP register to write to (from IEU) - output logic FWriteIntE, // integer register write enable (to IEU) - output logic FCvtIntE, // Convert to int (to IEU) - // Memory stage - input logic [2:0] Funct3M, // Funct fields of instruction specify type of operations - input logic [4:0] RdM, // which FP register to write to (from IEU) - output logic FRegWriteM, // FP register write enable (to privileged unit) - output logic FpLoadStoreM, // Fp load instruction? (to LSU) - output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU) - output logic [`XLEN-1:0] FIntResM, // data to be written to integer register (to IEU) - output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction (to IFU) - output logic [4:0] SetFflagsM, // FPU flags (to privileged unit) - // Writeback stage - input logic [4:0] RdW, // which FP register to write to (from IEU) - input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU) - output logic [`XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU) - output logic FCvtIntW, // select FCvtIntRes (to IEU) - output logic [`XLEN-1:0] FIntDivResultW // Result from integer division (to IEU) + input logic StallE, StallM, StallW, // stall signals (from HZU) + input logic FlushE, FlushM, FlushW, // flush signals (from HZU) + output logic FPUStallD, // Stall the decode stage (To HZU) + output logic FDivBusyE, // Is the divide/sqrt unit busy (stall execute stage) (to HZU) + // CSRs + input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit) + input logic [2:0] FRM_REGW, // Rounding mode (from CSR) + // Decode stage + input logic [31:0] InstrD, // instruction (from IFU) + // Execute stage + input logic [2:0] Funct3E, // Funct fields of instruction specify type of operations + input logic IntDivE, W64E, // Integer division on FPU + input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input for convert, move, and int div (from IEU) + input logic [4:0] RdE, // which FP register to write to (from IEU) + output logic FWriteIntE, // integer register write enable (to IEU) + output logic FCvtIntE, // Convert to int (to IEU) + // Memory stage + input logic [2:0] Funct3M, // Funct fields of instruction specify type of operations + input logic [4:0] RdM, // which FP register to write to (from IEU) + output logic FRegWriteM, // FP register write enable (to privileged unit) + output logic FpLoadStoreM, // Fp load instruction? (to LSU) + output logic [`FLEN-1:0] FWriteDataM, // Data to be written to memory (to LSU) + output logic [`XLEN-1:0] FIntResM, // data to be written to integer register (to IEU) + output logic IllegalFPUInstrD, // Is the instruction an illegal fpu instruction (to IFU) + output logic [4:0] SetFflagsM, // FPU flags (to privileged unit) + // Writeback stage + input logic [4:0] RdW, // which FP register to write to (from IEU) + input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU) + output logic [`XLEN-1:0] FCvtIntResW, // convert result to to be written to integer register (to IEU) + output logic FCvtIntW, // select FCvtIntRes (to IEU) + output logic [`XLEN-1:0] FIntDivResultW // Result from integer division (to IEU) ); // RISC-V FPU specifics: @@ -70,97 +70,97 @@ module fpu ( // - RISC-V detects underflow after rounding // control signals - logic FRegWriteW; // FP register write enable - logic [2:0] FrmM; // FP rounding mode - logic [`FMTBITS-1:0] FmtE, FmtM; // FP precision 0-single 1-double - logic FDivStartE, IDivStartE; // Start division or squareroot - logic FWriteIntM; // Write to integer register - logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals - logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component - logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage - logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit - logic [4:0] Adr1D, Adr2D, Adr3D; // register adresses of each input - logic [4:0] Adr1E, Adr2E, Adr3E; // register adresses of each input - logic XEnD, YEnD, ZEnD; // X, Y, Z inputs used for current operation - logic XEnE, YEnE, ZEnE; // X, Y, Z inputs used for current operation - logic FRegWriteE; // Write floating-point register + logic FRegWriteW; // FP register write enable + logic [2:0] FrmM; // FP rounding mode + logic [`FMTBITS-1:0] FmtE, FmtM; // FP precision 0-single 1-double + logic FDivStartE, IDivStartE; // Start division or squareroot + logic FWriteIntM; // Write to integer register + logic [1:0] ForwardXE, ForwardYE, ForwardZE; // forwarding mux control signals + logic [2:0] OpCtrlE, OpCtrlM; // Select which opperation to do in each component + logic [1:0] FResSelE, FResSelM, FResSelW; // Select one of the results that finish in the memory stage + logic [1:0] PostProcSelE, PostProcSelM; // select result in the post processing unit + logic [4:0] Adr1D, Adr2D, Adr3D; // register adresses of each input + logic [4:0] Adr1E, Adr2E, Adr3E; // register adresses of each input + logic XEnD, YEnD, ZEnD; // X, Y, Z inputs used for current operation + logic XEnE, YEnE, ZEnE; // X, Y, Z inputs used for current operation + logic FRegWriteE; // Write floating-point register // regfile signals - logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage - logic [`FLEN-1:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage - logic [`FLEN-1:0] XE; // Input 1 to the various units (after forwarding) - logic [`XLEN-1:0] IntSrcXE; // Input 1 to the various units (after forwarding) - logic [`FLEN-1:0] PreYE, YE; // Input 2 to the various units (after forwarding) - logic [`FLEN-1:0] PreZE, ZE; // Input 3 to the various units (after forwarding) + logic [`FLEN-1:0] FRD1D, FRD2D, FRD3D; // Read Data from FP register - decode stage + logic [`FLEN-1:0] FRD1E, FRD2E, FRD3E; // Read Data from FP register - execute stage + logic [`FLEN-1:0] XE; // Input 1 to the various units (after forwarding) + logic [`XLEN-1:0] IntSrcXE; // Input 1 to the various units (after forwarding) + logic [`FLEN-1:0] PreYE, YE; // Input 2 to the various units (after forwarding) + logic [`FLEN-1:0] PreZE, ZE; // Input 3 to the various units (after forwarding) // unpacking signals - logic XsE, YsE, ZsE; // input's sign - execute stage - logic XsM, YsM; // input's sign - memory stage - logic [`NE-1:0] XeE, YeE, ZeE; // input's exponent - execute stage - logic [`NE-1:0] ZeM; // input's exponent - memory stage - logic [`NF:0] XmE, YmE, ZmE; // input's significand - execute stage - logic [`NF:0] XmM, YmM, ZmM; // input's significand - memory stage - logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage - logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage - logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage - logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage - logic XSubnormE; // is the input subnormal - logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage - logic XZeroM, YZeroM; // is the input zero - memory stage - logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage - logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage - logic XExpMaxE; // is the exponent all ones (max value) - logic [`FLEN-1:0] XPostBoxE; // X after fixing bad NaN box. Needed for 1-input operations + logic XsE, YsE, ZsE; // input's sign - execute stage + logic XsM, YsM; // input's sign - memory stage + logic [`NE-1:0] XeE, YeE, ZeE; // input's exponent - execute stage + logic [`NE-1:0] ZeM; // input's exponent - memory stage + logic [`NF:0] XmE, YmE, ZmE; // input's significand - execute stage + logic [`NF:0] XmM, YmM, ZmM; // input's significand - memory stage + logic XNaNE, YNaNE, ZNaNE; // is the input a NaN - execute stage + logic XNaNM, YNaNM, ZNaNM; // is the input a NaN - memory stage + logic XSNaNE, YSNaNE, ZSNaNE; // is the input a signaling NaN - execute stage + logic XSNaNM, YSNaNM, ZSNaNM; // is the input a signaling NaN - memory stage + logic XSubnormE; // is the input subnormal + logic XZeroE, YZeroE, ZZeroE; // is the input zero - execute stage + logic XZeroM, YZeroM; // is the input zero - memory stage + logic XInfE, YInfE, ZInfE; // is the input infinity - execute stage + logic XInfM, YInfM, ZInfM; // is the input infinity - memory stage + logic XExpMaxE; // is the exponent all ones (max value) + logic [`FLEN-1:0] XPostBoxE; // X after fixing bad NaN box. Needed for 1-input operations // Fma Signals - logic FmaAddSubE; // Multiply by 1.0 when adding or subtracting - logic [1:0] FmaZSelE; // Select Z = Y when adding or subtracting, 0 when multiplying - logic [3*`NF+3:0] SmE, SmM; // Sum significand - logic FmaAStickyE, FmaAStickyM; // FMA addend sticky bit output - logic [`NE+1:0] SeE,SeM; // Sum exponent - logic InvAE, InvAM; // Invert addend - logic AsE, AsM; // Addend sign - logic PsE, PsM; // Product sign - logic SsE, SsM; // Sum sign - logic [$clog2(3*`NF+5)-1:0] SCntE, SCntM; // LZA sum leading zero count + logic FmaAddSubE; // Multiply by 1.0 when adding or subtracting + logic [1:0] FmaZSelE; // Select Z = Y when adding or subtracting, 0 when multiplying + logic [3*`NF+3:0] SmE, SmM; // Sum significand + logic FmaAStickyE, FmaAStickyM; // FMA addend sticky bit output + logic [`NE+1:0] SeE,SeM; // Sum exponent + logic InvAE, InvAM; // Invert addend + logic AsE, AsM; // Addend sign + logic PsE, PsM; // Product sign + logic SsE, SsM; // Sum sign + logic [$clog2(3*`NF+5)-1:0] SCntE, SCntM; // LZA sum leading zero count // Cvt Signals - logic [`NE:0] CeE, CeM; // convert intermediate expoent - logic [`LOGCVTLEN-1:0] CvtShiftAmtE, CvtShiftAmtM; // how much to shift by - logic CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is subnormal - logic CsE, CsM; // convert result sign - logic IntZeroE, IntZeroM; // is the integer zero? - logic [`CVTLEN-1:0] CvtLzcInE, CvtLzcInM; // input to the Leading Zero Counter (priority encoder) - logic [`XLEN-1:0] FCvtIntResM; // fcvt integer result (for IEU) + logic [`NE:0] CeE, CeM; // convert intermediate expoent + logic [`LOGCVTLEN-1:0] CvtShiftAmtE, CvtShiftAmtM; // how much to shift by + logic CvtResSubnormUfE, CvtResSubnormUfM; // does the result underflow or is subnormal + logic CsE, CsM; // convert result sign + logic IntZeroE, IntZeroM; // is the integer zero? + logic [`CVTLEN-1:0] CvtLzcInE, CvtLzcInM; // input to the Leading Zero Counter (priority encoder) + logic [`XLEN-1:0] FCvtIntResM; // fcvt integer result (for IEU) // divide signals - logic [`DIVb:0] QmM; // fdivsqrt signifcand - logic [`NE+1:0] QeM; // fdivsqrt exponent - logic DivStickyM; // fdivsqrt sticky bit - logic FDivDoneE, IFDivStartE; // fdivsqrt control signals - logic [`XLEN-1:0] FIntDivResultM; // fdivsqrt integer division result (for IEU) + logic [`DIVb:0] QmM; // fdivsqrt signifcand + logic [`NE+1:0] QeM; // fdivsqrt exponent + logic DivStickyM; // fdivsqrt sticky bit + logic FDivDoneE, IFDivStartE; // fdivsqrt control signals + logic [`XLEN-1:0] FIntDivResultM; // fdivsqrt integer division result (for IEU) // result and flag signals - logic [`XLEN-1:0] ClassResE; // classify result - logic [`FLEN-1:0] CmpFpResE; // compare result to FPU (min/max) - logic [`XLEN-1:0] CmpIntResE; // compare result to IEU (eq/lt/le) - logic CmpNVE; // compare invalid flag (Not Valid) - logic [`FLEN-1:0] SgnResE; // sign injection result - logic [`XLEN-1:0] FIntResE; // FPU to IEU E-stage result (classify, compare, move) - logic [`FLEN-1:0] PostProcResM; // Postprocessor output - logic [4:0] PostProcFlgM; // Postprocessor flags - logic PreNVE, PreNVM; // selected flag that is ready in the memory stage - logic [`FLEN-1:0] FpResM, FpResW; // FPU preliminary result - logic [`FLEN-1:0] PreFpResE, PreFpResM; // selected result that is ready in the memory stage - logic [`FLEN-1:0] FResultW; // final FP result being written to the FP register + logic [`XLEN-1:0] ClassResE; // classify result + logic [`FLEN-1:0] CmpFpResE; // compare result to FPU (min/max) + logic [`XLEN-1:0] CmpIntResE; // compare result to IEU (eq/lt/le) + logic CmpNVE; // compare invalid flag (Not Valid) + logic [`FLEN-1:0] SgnResE; // sign injection result + logic [`XLEN-1:0] FIntResE; // FPU to IEU E-stage result (classify, compare, move) + logic [`FLEN-1:0] PostProcResM; // Postprocessor output + logic [4:0] PostProcFlgM; // Postprocessor flags + logic PreNVE, PreNVM; // selected flag that is ready in the memory stage + logic [`FLEN-1:0] FpResM, FpResW; // FPU preliminary result + logic [`FLEN-1:0] PreFpResE, PreFpResM; // selected result that is ready in the memory stage + logic [`FLEN-1:0] FResultW; // final FP result being written to the FP register // other signals - logic [`FLEN-1:0] AlignedSrcAE; // align SrcA from IEU to the floating point format for fmv - logic [`FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed - logic [`FLEN-1:0] BoxedOneE; // One value for Z for multiplication, with NaN boxing if needed - logic StallUnpackedM; // Stall unpacker outputs during multicycle fdivsqrt - logic [`FLEN-1:0] SgnExtXE; // Sign-extended X input for move to integer - logic mvsgn; // sign bit for extending move + logic [`FLEN-1:0] AlignedSrcAE; // align SrcA from IEU to the floating point format for fmv + logic [`FLEN-1:0] BoxedZeroE; // Zero value for Z for multiplication, with NaN boxing if needed + logic [`FLEN-1:0] BoxedOneE; // One value for Z for multiplication, with NaN boxing if needed + logic StallUnpackedM; // Stall unpacker outputs during multicycle fdivsqrt + logic [`FLEN-1:0] SgnExtXE; // Sign-extended X input for move to integer + logic mvsgn; // sign bit for extending move ////////////////////////////////////////////////////////////////////////////////////////// // Decode Stage: fctrl decoder, read register file @@ -180,7 +180,7 @@ module fpu ( fregfile fregfile (.clk, .reset, .we4(FRegWriteW), .a1(InstrD[19:15]), .a2(InstrD[24:20]), .a3(InstrD[31:27]), .a4(RdW), .wd4(FResultW), - .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D)); + .rd1(FRD1D), .rd2(FRD2D), .rd3(FRD3D)); // D/E pipeline registers flopenrc #(`FLEN) DEReg1(clk, reset, FlushE, ~StallE, FRD1D, FRD1E); diff --git a/src/fpu/fregfile.sv b/src/fpu/fregfile.sv index 1a5a2eecf..69961a847 100644 --- a/src/fpu/fregfile.sv +++ b/src/fpu/fregfile.sv @@ -29,8 +29,8 @@ `include "wally-config.vh" module fregfile ( - input logic clk, reset, - input logic we4, // write enable + input logic clk, reset, + input logic we4, // write enable input logic [4:0] a1, a2, a3, a4, // adresses input logic [`FLEN-1:0] wd4, // write data output logic [`FLEN-1:0] rd1, rd2, rd3 // read data @@ -46,7 +46,7 @@ module fregfile ( always_ff @(negedge clk) // or posedge reset) if (reset) for(i=0; i<32; i++) rf[i] <= 0; - else if (we4) rf[a4] <= wd4; + else if (we4) rf[a4] <= wd4; assign #2 rd1 = rf[a1]; assign #2 rd2 = rf[a2]; diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv index 0db7dc2f3..9ce938709 100755 --- a/src/fpu/fsgninj.sv +++ b/src/fpu/fsgninj.sv @@ -29,43 +29,43 @@ `include "wally-config.vh" module fsgninj ( - input logic Xs, Ys, // X and Y sign bits - input logic [`FLEN-1:0] X, // X - input logic [`FMTBITS-1:0] Fmt, // format - input logic [1:0] OpCtrl, // operation control - output logic [`FLEN-1:0] SgnRes // result + input logic Xs, Ys, // X and Y sign bits + input logic [`FLEN-1:0] X, // X + input logic [`FMTBITS-1:0] Fmt, // format + input logic [1:0] OpCtrl, // operation control + output logic [`FLEN-1:0] SgnRes // result ); - logic ResSgn; // result sign + logic ResSgn; // result sign - // OpCtrl: - // 00 - fsgnj - directly copy over sign value of Y - // 01 - fsgnjn - negate sign value of Y - // 10 - fsgnjx - XOR sign values of X and Y - - // calculate the result's sign - assign ResSgn = (OpCtrl[1] ? Xs : OpCtrl[0]) ^ Ys; - - // format final result based on precision - // - uses NaN-blocking format - // - if there are any unsused bits the most significant bits are filled with 1s - + // OpCtrl: + // 00 - fsgnj - directly copy over sign value of Y + // 01 - fsgnjn - negate sign value of Y + // 10 - fsgnjx - XOR sign values of X and Y + + // calculate the result's sign + assign ResSgn = (OpCtrl[1] ? Xs : OpCtrl[0]) ^ Ys; + + // format final result based on precision + // - uses NaN-blocking format + // - if there are any unsused bits the most significant bits are filled with 1s + if (`FPSIZES == 1) - assign SgnRes = {ResSgn, X[`FLEN-2:0]}; + assign SgnRes = {ResSgn, X[`FLEN-2:0]}; else if (`FPSIZES == 2) - assign SgnRes = {~Fmt|ResSgn, X[`FLEN-2:`LEN1], Fmt ? X[`LEN1-1] : ResSgn, X[`LEN1-2:0]}; + assign SgnRes = {~Fmt|ResSgn, X[`FLEN-2:`LEN1], Fmt ? X[`LEN1-1] : ResSgn, X[`LEN1-2:0]}; else if (`FPSIZES == 3) begin - logic [2:0] SgnBits; + logic [2:0] SgnBits; always_comb case (Fmt) `FMT: SgnBits = {ResSgn, X[`LEN1-1], X[`LEN2-1]}; - `FMT1: SgnBits = {1'b1, ResSgn, X[`LEN2-1]}; + `FMT1: SgnBits = {1'b1, ResSgn, X[`LEN2-1]}; `FMT2: SgnBits = {2'b11, ResSgn}; default: SgnBits = {3{1'bx}}; endcase - assign SgnRes = {SgnBits[2], X[`FLEN-2:`LEN1], SgnBits[1], X[`LEN1-2:`LEN2], SgnBits[0], X[`LEN2-2:0]}; - end else if (`FPSIZES == 4) begin - logic [3:0] SgnBits; + assign SgnRes = {SgnBits[2], X[`FLEN-2:`LEN1], SgnBits[1], X[`LEN1-2:`LEN2], SgnBits[0], X[`LEN2-2:0]}; + end else if (`FPSIZES == 4) begin + logic [3:0] SgnBits; always_comb case (Fmt) `Q_FMT: SgnBits = {ResSgn, X[`D_LEN-1], X[`S_LEN-1], X[`H_LEN-1]}; @@ -73,7 +73,7 @@ module fsgninj ( `S_FMT: SgnBits = {2'b11, ResSgn, X[`H_LEN-1]}; `H_FMT: SgnBits = {3'b111, ResSgn}; endcase - assign SgnRes = {SgnBits[3], X[`Q_LEN-2:`D_LEN], SgnBits[2], X[`D_LEN-2:`S_LEN], SgnBits[1], X[`S_LEN-2:`H_LEN], SgnBits[0], X[`H_LEN-2:0]}; - end + assign SgnRes = {SgnBits[3], X[`Q_LEN-2:`D_LEN], SgnBits[2], X[`D_LEN-2:`S_LEN], SgnBits[1], X[`S_LEN-2:`H_LEN], SgnBits[0], X[`H_LEN-2:0]}; + end endmodule diff --git a/src/generic/arrs.sv b/src/generic/arrs.sv index 0bb30c96a..5a9cf21f0 100644 --- a/src/generic/arrs.sv +++ b/src/generic/arrs.sv @@ -30,13 +30,13 @@ `include "wally-config.vh" module arrs( - input logic clk, - input logic areset, + input logic clk, + input logic areset, output logic reset ); - logic metaStable; - logic resetB; + logic metaStable; + logic resetB; always_ff @(posedge clk , posedge areset) begin if (areset) begin diff --git a/src/generic/clockgater.sv b/src/generic/clockgater.sv index 55f02cff5..c09f98f2c 100644 --- a/src/generic/clockgater.sv +++ b/src/generic/clockgater.sv @@ -27,9 +27,9 @@ `include "wally-config.vh" module clockgater ( - input logic E, - input logic SE, - input logic CLK, + input logic E, + input logic SE, + input logic CLK, output logic ECLK ); @@ -39,10 +39,10 @@ module clockgater ( // VERY IMPORTANT. // This part functionally models a clock gater, but does not necessarily meet the timing constrains a real standard cell would. // Do not use this in synthesis! - logic enable_q; + logic enable_q; always_latch begin if(~CLK) begin - enable_q <= E | SE; + enable_q <= E | SE; end end assign ECLK = enable_q & CLK; diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index f3c98873e..8905cc551 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -49,39 +49,39 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) ( // *************************************************************************** // TRUE SRAM macro // *************************************************************************** - if ((`USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray + if ((`USE_SRAM == 1) & (WIDTH == 128) & (DEPTH == 64)) begin // Cache data subarray genvar index; - // 64 x 128-bit SRAM - logic [WIDTH-1:0] BitWriteMask; - for (index=0; index < WIDTH; index++) - assign BitWriteMask[index] = bwe[index/8]; + // 64 x 128-bit SRAM + logic [WIDTH-1:0] BitWriteMask; + for (index=0; index < WIDTH; index++) + assign BitWriteMask[index] = bwe[index/8]; ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we), - .A(addr), .D(din), - .BWEB(~BitWriteMask), .Q(dout)); + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); end else if ((`USE_SRAM == 1) & (WIDTH == 44) & (DEPTH == 64)) begin // RV64 cache tag - genvar index; - // 64 x 44-bit SRAM - logic [WIDTH-1:0] BitWriteMask; - for (index=0; index < WIDTH; index++) - assign BitWriteMask[index] = bwe[index/8]; - ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), - .A(addr), .D(din), - .BWEB(~BitWriteMask), .Q(dout)); + genvar index; + // 64 x 44-bit SRAM + logic [WIDTH-1:0] BitWriteMask; + for (index=0; index < WIDTH; index++) + assign BitWriteMask[index] = bwe[index/8]; + ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); end else if ((`USE_SRAM == 1) & (WIDTH == 22) & (DEPTH == 64)) begin // RV32 cache tag - genvar index; - // 64 x 22-bit SRAM - logic [WIDTH-1:0] BitWriteMask; - for (index=0; index < WIDTH; index++) - assign BitWriteMask[index] = bwe[index/8]; - ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), - .A(addr), .D(din), - .BWEB(~BitWriteMask), .Q(dout)); + genvar index; + // 64 x 22-bit SRAM + logic [WIDTH-1:0] BitWriteMask; + for (index=0; index < WIDTH; index++) + assign BitWriteMask[index] = bwe[index/8]; + ram1p1rwbe_64x22 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we), + .A(addr), .D(din), + .BWEB(~BitWriteMask), .Q(dout)); - // *************************************************************************** - // READ first SRAM model - // *************************************************************************** + // *************************************************************************** + // READ first SRAM model + // *************************************************************************** end else begin: ram integer i; @@ -91,19 +91,18 @@ module ram1p1rwbe #(parameter DEPTH=64, WIDTH=44) ( assign dout = RAM[addrd]; /* // Read - always_ff @(posedge clk) - if(ce) dout <= #1 mem[addr]; */ - + always_ff @(posedge clk) + if(ce) dout <= #1 mem[addr]; */ // Write divided into part for bytes and part for extra msbs - // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff. - // Therefore these always blocks use the older always @(posedge clk) + // Questa sim version 2022.3_2 does not allow multiple drivers for RAM when using always_ff. + // Therefore these always blocks use the older always @(posedge clk) if(WIDTH >= 8) always @(posedge clk) if (ce & we) for(i = 0; i < WIDTH/8; i++) if(bwe[i]) RAM[addr][i*8 +: 8] <= #1 din[i*8 +: 8]; - + if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 always @(posedge clk) if (ce & we & bwe[WIDTH/8]) diff --git a/src/generic/mem/ram1p1rwbe_64x128.sv b/src/generic/mem/ram1p1rwbe_64x128.sv index 84a3e74f9..55b1d75b0 100755 --- a/src/generic/mem/ram1p1rwbe_64x128.sv +++ b/src/generic/mem/ram1p1rwbe_64x128.sv @@ -26,7 +26,7 @@ module ram1p1rwbe_64x128( input logic CLK, - input logic CEB, + input logic CEB, input logic WEB, input logic [5:0] A, input logic [127:0] D, diff --git a/src/generic/mem/ram1p1rwbe_64x22.sv b/src/generic/mem/ram1p1rwbe_64x22.sv index 8e0f56306..5e7a4c5cf 100755 --- a/src/generic/mem/ram1p1rwbe_64x22.sv +++ b/src/generic/mem/ram1p1rwbe_64x22.sv @@ -26,7 +26,7 @@ module ram1p1rwbe_64x22( input logic CLK, - input logic CEB, + input logic CEB, input logic WEB, input logic [5:0] A, input logic [21:0] D, diff --git a/src/generic/mem/ram1p1rwbe_64x44.sv b/src/generic/mem/ram1p1rwbe_64x44.sv index 89730a42b..a2c2c81fa 100644 --- a/src/generic/mem/ram1p1rwbe_64x44.sv +++ b/src/generic/mem/ram1p1rwbe_64x44.sv @@ -26,7 +26,7 @@ module ram1p1rwbe_64x44( input logic CLK, - input logic CEB, + input logic CEB, input logic WEB, input logic [5:0] A, input logic [43:0] D, diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index cefd5ab9f..4c72095b6 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -44,96 +44,94 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68) ( output logic [WIDTH-1:0] rd1 ); - logic [WIDTH-1:0] mem[DEPTH-1:0]; - localparam SRAMWIDTH = 32; - localparam SRAMNUMSETS = SRAMWIDTH/WIDTH; + logic [WIDTH-1:0] mem[DEPTH-1:0]; + localparam SRAMWIDTH = 32; + localparam SRAMNUMSETS = SRAMWIDTH/WIDTH; // *************************************************************************** // TRUE Smem macro // *************************************************************************** - if ((`USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin - - ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), - .CEBA(~ce1), .CEBB(~ce2), - .WEBA('0), .WEBB(~we2), - .AA(ra1), .AB(wa2), - .DA('0), - .DB(wd2), - .BWEBA('0), .BWEBB('1), - .QA(rd1), - .QB()); + if ((`USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin + + ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1), .AB(wa2), + .DA('0), + .DB(wd2), + .BWEBA('0), .BWEBB('1), + .QA(rd1), + .QB()); - end else if ((`USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin - - ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), - .CEBA(~ce1), .CEBB(~ce2), - .WEBA('0), .WEBB(~we2), - .AA(ra1), .AB(wa2), - .DA('0), - .DB(wd2), - .BWEBA('0), .BWEBB('1), - .QA(rd1), - .QB()); + end else if ((`USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin + + ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1), .AB(wa2), + .DA('0), + .DB(wd2), + .BWEBA('0), .BWEBB('1), + .QA(rd1), + .QB()); - end else if ((`USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin + end else if ((`USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin - logic [SRAMWIDTH-1:0] SRAMReadData; - logic [SRAMWIDTH-1:0] SRAMWriteData; - logic [SRAMWIDTH-1:0] RD1Sets[SRAMNUMSETS-1:0]; - logic [SRAMNUMSETS-1:0] SRAMBitMaskPre; - logic [SRAMWIDTH-1:0] SRAMBitMask; - logic [$clog2(DEPTH)-1:0] RA1Q; - - - onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre); - genvar index; - for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux - assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)]; - assign SRAMWriteData[index*2+1:index*2] = wd2; - assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}}; - end - flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q); - assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]]; - ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk), - .CEBA(~ce1), .CEBB(~ce2), - .WEBA('0), .WEBB(~we2), - .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), - .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), - .DA('0), - .DB(SRAMWriteData), - .BWEBA('0), .BWEBB(SRAMBitMask), - .QA(SRAMReadData), - .QB()); + logic [SRAMWIDTH-1:0] SRAMReadData; + logic [SRAMWIDTH-1:0] SRAMWriteData; + logic [SRAMWIDTH-1:0] RD1Sets[SRAMNUMSETS-1:0]; + logic [SRAMNUMSETS-1:0] SRAMBitMaskPre; + logic [SRAMWIDTH-1:0] SRAMBitMask; + logic [$clog2(DEPTH)-1:0] RA1Q; + + onehotdecoder #($clog2(SRAMNUMSETS)) oh1(wa2[$clog2(SRAMNUMSETS)-1:0], SRAMBitMaskPre); + genvar index; + for (index = 0; index < SRAMNUMSETS; index++) begin:readdatalinesetsmux + assign RD1Sets[index] = SRAMReadData[(index*WIDTH)+WIDTH-1 : (index*WIDTH)]; + assign SRAMWriteData[index*2+1:index*2] = wd2; + assign SRAMBitMask[index*2+1:index*2] = {2{SRAMBitMaskPre[index]}}; + end + flopen #($clog2(DEPTH)) mem_reg1 (clk, ce1, ra1, RA1Q); + assign rd1 = RD1Sets[RA1Q[$clog2(SRAMWIDTH)-1:0]]; + ram2p1r1wbe_64x32 memory2(.CLKA(clk), .CLKB(clk), + .CEBA(~ce1), .CEBB(~ce2), + .WEBA('0), .WEBB(~we2), + .AA(ra1[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), + .AB(wa2[$clog2(DEPTH)-1:$clog2(SRAMNUMSETS)]), + .DA('0), + .DB(SRAMWriteData), + .BWEBA('0), .BWEBB(SRAMBitMask), + .QA(SRAMReadData), + .QB()); - end else begin - - // *************************************************************************** - // READ first SRAM model - // *************************************************************************** - integer i; - + end else begin + + // *************************************************************************** + // READ first SRAM model + // *************************************************************************** + integer i; + // Read logic [$clog2(DEPTH)-1:0] ra1d; flopen #($clog2(DEPTH)) adrreg(clk, ce1, ra1, ra1d); assign rd1 = mem[ra1d]; -/* // Read - always_ff @(posedge clk) - if(ce1) rd1 <= #1 mem[ra1]; */ - - // Write divided into part for bytes and part for extra msbs - if(WIDTH >= 8) - always @(posedge clk) - if (ce2 & we2) - for(i = 0; i < WIDTH/8; i++) - if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; - - if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 - always @(posedge clk) - if (ce2 & we2 & bwe2[WIDTH/8]) - mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8]; - + /* // Read + always_ff @(posedge clk) + if(ce1) rd1 <= #1 mem[ra1]; */ + + // Write divided into part for bytes and part for extra msbs + if(WIDTH >= 8) + always @(posedge clk) + if (ce2 & we2) + for(i = 0; i < WIDTH/8; i++) + if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8]; + + if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8 + always @(posedge clk) + if (ce2 & we2 & bwe2[WIDTH/8]) + mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8]; end - + endmodule diff --git a/src/generic/mem/ram2p1r1wbe_1024x36.sv b/src/generic/mem/ram2p1r1wbe_1024x36.sv index b6b501f27..302277ed0 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x36.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x36.sv @@ -27,8 +27,8 @@ module ram2p1r1wbe_1024x36( input logic CLKA, input logic CLKB, - input logic CEBA, - input logic CEBB, + input logic CEBA, + input logic CEBB, input logic WEBA, input logic WEBB, input logic [9:0] AA, @@ -43,12 +43,12 @@ module ram2p1r1wbe_1024x36( // replace "generic1024x36RAM" with "TSDN..1024X36.." module from your memory vendor //generic1024x36RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); // use part of a larger RAM to avoid generating more flavors of RAM logic [67:0] QAfull, QBfull; TSDN28HPCPA1024X68M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - .AA, .AB, .DA({32'b0, DA[35:0]}), .DB({32'b0, DB[35:0]}), - .BWEBA({32'b0, BWEBA[35:0]}), .BWEBB({32'b0, BWEBB[35:0]}), .QA(QAfull), .QB(QBfull)); + .AA, .AB, .DA({32'b0, DA[35:0]}), .DB({32'b0, DB[35:0]}), + .BWEBA({32'b0, BWEBA[35:0]}), .BWEBB({32'b0, BWEBB[35:0]}), .QA(QAfull), .QB(QBfull)); assign QA = QAfull[35:0]; assign QB = QBfull[35:0]; diff --git a/src/generic/mem/ram2p1r1wbe_1024x68.sv b/src/generic/mem/ram2p1r1wbe_1024x68.sv index 108530bee..6da7e06d6 100755 --- a/src/generic/mem/ram2p1r1wbe_1024x68.sv +++ b/src/generic/mem/ram2p1r1wbe_1024x68.sv @@ -27,8 +27,8 @@ module ram2p1r1wbe_1024x68( input logic CLKA, input logic CLKB, - input logic CEBA, - input logic CEBB, + input logic CEBA, + input logic CEBB, input logic WEBA, input logic WEBB, input logic [9:0] AA, @@ -43,8 +43,8 @@ module ram2p1r1wbe_1024x68( // replace "generic1024x68RAM" with "TSDN..1024X68.." module from your memory vendor //generic1024x68RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); TSDN28HPCPA1024X68M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_128x64.sv b/src/generic/mem/ram2p1r1wbe_128x64.sv index 49d2631ee..e181fdd07 100644 --- a/src/generic/mem/ram2p1r1wbe_128x64.sv +++ b/src/generic/mem/ram2p1r1wbe_128x64.sv @@ -27,8 +27,8 @@ module ram2p1r1wbe_128x64( input logic CLKA, input logic CLKB, - input logic CEBA, - input logic CEBB, + input logic CEBA, + input logic CEBB, input logic WEBA, input logic WEBB, input logic [6:0] AA, @@ -43,8 +43,8 @@ module ram2p1r1wbe_128x64( // replace "generic128x64RAM" with "TSDN..128X64.." module from your memory vendor TSDN28HPCPA128X64M4FW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); // generic128x64RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, -// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); +// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_512x64.sv b/src/generic/mem/ram2p1r1wbe_512x64.sv index 14fbea75c..442eff90d 100644 --- a/src/generic/mem/ram2p1r1wbe_512x64.sv +++ b/src/generic/mem/ram2p1r1wbe_512x64.sv @@ -27,8 +27,8 @@ module ram2p1r1wbe_2048x64( input logic CLKA, input logic CLKB, - input logic CEBA, - input logic CEBB, + input logic CEBA, + input logic CEBB, input logic WEBA, input logic WEBB, input logic [8:0] AA, @@ -43,8 +43,8 @@ module ram2p1r1wbe_2048x64( // replace "generic2048x64RAM" with "TSDN..2048X64.." module from your memory vendor TSDN28HPCPA2048X64MMFW sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); // generic2048x64RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, -// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); +// .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/src/generic/mem/ram2p1r1wbe_64x32.sv b/src/generic/mem/ram2p1r1wbe_64x32.sv index e551099f4..4236bb3f6 100755 --- a/src/generic/mem/ram2p1r1wbe_64x32.sv +++ b/src/generic/mem/ram2p1r1wbe_64x32.sv @@ -27,8 +27,8 @@ module ram2p1r1wbe_64x32( input logic CLKA, input logic CLKB, - input logic CEBA, - input logic CEBB, + input logic CEBA, + input logic CEBB, input logic WEBA, input logic WEBB, input logic [5:0] AA, @@ -43,7 +43,7 @@ module ram2p1r1wbe_64x32( // replace "generic64x32RAM" with "TSDN..64X32.." module from your memory vendor //generic64x32RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + // .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); TSDN28HPCPA64X32M4MW sramIP(.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB, - .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); + .AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB); endmodule diff --git a/src/generic/mem/rom1p1r.sv b/src/generic/mem/rom1p1r.sv index 6930bc0db..ef9c6da37 100644 --- a/src/generic/mem/rom1p1r.sv +++ b/src/generic/mem/rom1p1r.sv @@ -28,8 +28,8 @@ `include "wally-config.vh" module rom1p1r #(parameter ADDR_WIDTH = 8, - parameter DATA_WIDTH = 32, - parameter PRELOAD_ENABLED = 0) + parameter DATA_WIDTH = 32, + parameter PRELOAD_ENABLED = 0) (input logic clk, input logic ce, input logic [ADDR_WIDTH-1:0] addr, @@ -37,7 +37,7 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, ); // Core Memory - logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; + logic [DATA_WIDTH-1:0] ROM [(2**ADDR_WIDTH)-1:0]; /* if ((`USE_SRAM == 1) & (ADDR_WDITH == 7) & (DATA_WIDTH == 64)) begin rom1p1r_128x64 rom1 (.CLK(clk), .CEB(~ce), .A(addr[6:0]), .Q(dout)); @@ -46,55 +46,55 @@ module rom1p1r #(parameter ADDR_WIDTH = 8, end else begin */ always @ (posedge clk) begin - if(ce) dout <= ROM[addr]; + if(ce) dout <= ROM[addr]; end // for FPGA, initialize with zero-stage bootloader if(PRELOAD_ENABLED) initial begin - ROM[0] = 64'h9581819300002197; - ROM[1] = 64'h4281420141014081; - ROM[2] = 64'h4481440143814301; - ROM[3] = 64'h4681460145814501; - ROM[4] = 64'h4881480147814701; - ROM[5] = 64'h4a814a0149814901; - ROM[6] = 64'h4c814c014b814b01; - ROM[7] = 64'h4e814e014d814d01; - ROM[8] = 64'h0110011b4f814f01; - ROM[9] = 64'h059b45011161016e; - ROM[10] = 64'h0004063705fe0010; - ROM[11] = 64'h05a000ef8006061b; - ROM[12] = 64'h0ff003930000100f; - ROM[13] = 64'h4e952e3110060e37; - ROM[14] = 64'hc602829b0053f2b7; - ROM[15] = 64'h2023fe02dfe312fd; - ROM[16] = 64'h829b0053f2b7007e; - ROM[17] = 64'hfe02dfe312fdc602; - ROM[18] = 64'h4de31efd000e2023; - ROM[19] = 64'h059bf1402573fdd0; - ROM[20] = 64'h0000061705e20870; - ROM[21] = 64'h0010029b01260613; - ROM[22] = 64'h11010002806702fe; - ROM[23] = 64'h84b2842ae426e822; - ROM[24] = 64'h892ee04aec064511; - ROM[25] = 64'h06e000ef07e000ef; - ROM[26] = 64'h979334fd02905563; - ROM[27] = 64'h07930177d4930204; - ROM[28] = 64'h4089093394be2004; - ROM[29] = 64'h04138522008905b3; - ROM[30] = 64'h19e3014000ef2004; - ROM[31] = 64'h64a2644260e2fe94; - ROM[32] = 64'h6749808261056902; - ROM[33] = 64'hdfed8b8510472783; - ROM[34] = 64'h2423479110a73823; - ROM[35] = 64'h10472783674910f7; - ROM[36] = 64'h20058693ffed8b89; - ROM[37] = 64'h05a1118737836749; - ROM[38] = 64'hfed59be3fef5bc23; - ROM[39] = 64'h1047278367498082; - ROM[40] = 64'h47858082dfed8b85; - ROM[41] = 64'h40a7853b4015551b; - ROM[42] = 64'h808210a7a02367c9; + ROM[0] = 64'h9581819300002197; + ROM[1] = 64'h4281420141014081; + ROM[2] = 64'h4481440143814301; + ROM[3] = 64'h4681460145814501; + ROM[4] = 64'h4881480147814701; + ROM[5] = 64'h4a814a0149814901; + ROM[6] = 64'h4c814c014b814b01; + ROM[7] = 64'h4e814e014d814d01; + ROM[8] = 64'h0110011b4f814f01; + ROM[9] = 64'h059b45011161016e; + ROM[10] = 64'h0004063705fe0010; + ROM[11] = 64'h05a000ef8006061b; + ROM[12] = 64'h0ff003930000100f; + ROM[13] = 64'h4e952e3110060e37; + ROM[14] = 64'hc602829b0053f2b7; + ROM[15] = 64'h2023fe02dfe312fd; + ROM[16] = 64'h829b0053f2b7007e; + ROM[17] = 64'hfe02dfe312fdc602; + ROM[18] = 64'h4de31efd000e2023; + ROM[19] = 64'h059bf1402573fdd0; + ROM[20] = 64'h0000061705e20870; + ROM[21] = 64'h0010029b01260613; + ROM[22] = 64'h11010002806702fe; + ROM[23] = 64'h84b2842ae426e822; + ROM[24] = 64'h892ee04aec064511; + ROM[25] = 64'h06e000ef07e000ef; + ROM[26] = 64'h979334fd02905563; + ROM[27] = 64'h07930177d4930204; + ROM[28] = 64'h4089093394be2004; + ROM[29] = 64'h04138522008905b3; + ROM[30] = 64'h19e3014000ef2004; + ROM[31] = 64'h64a2644260e2fe94; + ROM[32] = 64'h6749808261056902; + ROM[33] = 64'hdfed8b8510472783; + ROM[34] = 64'h2423479110a73823; + ROM[35] = 64'h10472783674910f7; + ROM[36] = 64'h20058693ffed8b89; + ROM[37] = 64'h05a1118737836749; + ROM[38] = 64'hfed59be3fef5bc23; + ROM[39] = 64'h1047278367498082; + ROM[40] = 64'h47858082dfed8b85; + ROM[41] = 64'h40a7853b4015551b; + ROM[42] = 64'h808210a7a02367c9; end endmodule diff --git a/src/generic/mem/rom1p1r_128x32.sv b/src/generic/mem/rom1p1r_128x32.sv index bc16a76dc..ea5b92054 100755 --- a/src/generic/mem/rom1p1r_128x32.sv +++ b/src/generic/mem/rom1p1r_128x32.sv @@ -26,7 +26,7 @@ module rom1p1r_128x32( input logic CLK, - input logic CEB, + input logic CEB, input logic [6:0] A, output logic [31:0] Q ); diff --git a/src/generic/mem/rom1p1r_128x64.sv b/src/generic/mem/rom1p1r_128x64.sv index 3c7ea4842..6712d10fa 100755 --- a/src/generic/mem/rom1p1r_128x64.sv +++ b/src/generic/mem/rom1p1r_128x64.sv @@ -25,14 +25,14 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module rom1p1r_128x64( - input logic CLK, - input logic CEB, + input logic CLK, + input logic CEB, input logic [6:0] A, output logic [63:0] Q ); // replace "generic64x128RAM" with "TS3N..64X128.." module from your memory vendor -ts3n28hpcpa128x64m8m romIP (.CLK, .CEB, .A, .Q); + ts3n28hpcpa128x64m8m romIP (.CLK, .CEB, .A, .Q); // generic64x128ROM romIP (.CLK, .CEB, .A, .Q); endmodule diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index b436fda46..90d031a14 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -30,7 +30,7 @@ `include "wally-config.vh" module bmuctrl( - input logic clk, reset, + input logic clk, reset, // Decode stage control signals input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage @@ -43,7 +43,7 @@ module bmuctrl( output logic BSubArithD, // TRUE if ext, clr, andn, orn, xnor instruction in Decode Stage output logic IllegalBitmanipInstrD, // Indicates if it is unrecognized B instruction in Decode Stage // Execute stage control signals - input logic StallE, FlushE, // Stall, flush Execute stage + input logic StallE, FlushE, // Stall, flush Execute stage output logic [2:0] ALUSelectD, // ALU select output logic [1:0] BSelectE, // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding output logic [2:0] ZBBSelectE, // ZBB mux select signal @@ -66,7 +66,7 @@ module bmuctrl( `define BMUCTRLW 17 - logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals + logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals // Extract fields assign OpD = InstrD[6:0]; @@ -180,4 +180,4 @@ module bmuctrl( // BMU Execute stage pipieline control register flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {BSelectD, ZBBSelectD, BRegWriteD, BComparatorSignedD, BALUControlD}, {BSelectE, ZBBSelectE, BRegWriteE, BComparatorSignedE, BALUControlE}); -endmodule \ No newline at end of file +endmodule diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 21811b49a..da99a48f6 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -31,7 +31,7 @@ module controller( - input logic clk, reset, + input logic clk, reset, // Decode stage control signals input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage @@ -41,11 +41,11 @@ module controller( output logic JumpD, // Jump instruction output logic BranchD, // Branch instruction // Execute stage control signals - input logic StallE, FlushE, // Stall, flush Execute stage + input logic StallE, FlushE, // Stall, flush Execute stage input logic [1:0] FlagsE, // Comparison flags ({eq, lt}) input logic FWriteIntE, // Write integer register, coming from FPU controller output logic PCSrcE, // Select signal to choose next PC (for datapath and Hazard unit) - output logic ALUSrcAE, ALUSrcBE, // ALU operands + output logic ALUSrcAE, ALUSrcBE, // ALU operands output logic ALUResultSrcE, // Selects result to pass on to Memory stage output logic [2:0] ALUSelectE, // ALU mux select signal output logic MemReadE, CSRReadE, // Instruction reads memory, reads a CSR (needed for Hazard unit) @@ -74,7 +74,7 @@ module controller( output logic FWriteIntM, // FPU controller writes integer register file // Writeback stage control signals input logic StallW, FlushW, // Stall, flush Writeback stage - output logic RegWriteW, IntDivW, // Instruction writes a register, is an integer divide + output logic RegWriteW, IntDivW, // Instruction writes a register, is an integer divide output logic [2:0] ResultSrcW, // Select source of result to write back to register file // Stall during CSRs output logic CSRWriteFenceM, // CSR write or fence instruction; needs to flush the following instructions @@ -89,16 +89,16 @@ module controller( `define CTRLW 23 // pipelined control signals - logic RegWriteD, RegWriteE; // RegWrite (register will be written) + logic RegWriteD, RegWriteE; // RegWrite (register will be written) logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file logic [1:0] MemRWD, MemRWE; // Store (write to memory) - logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) - logic BaseW64D; // W64 for Base instructions specifically - logic BaseRegWriteD; // Indicates if Base instruction register write instruction - logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu + logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3) + logic BaseW64D; // W64 for Base instructions specifically + logic BaseRegWriteD; // Indicates if Base instruction register write instruction + logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu logic BaseALUSrcBD; // Base instruction ALU B source select signal logic [2:0] ALUControlD; // Determines ALU operation - logic ALUSrcAD, ALUSrcBD; // ALU inputs + logic ALUSrcAD, ALUSrcBD; // ALU inputs logic ALUResultSrcD, W64D, MDUD; // ALU result, is RV64 W-type, is multiply/divide instruction logic CSRZeroSrcD; // Ignore setting and clearing zeros to CSR logic CSRReadD; // CSR read instruction @@ -115,7 +115,7 @@ module controller( logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; - logic BranchFlagE; // Branch flag to use (chosen between eq or lt) + logic BranchFlagE; // Branch flag to use (chosen between eq or lt) logic IEURegWriteE; // Register write logic BRegWriteE; // Register write from BMU controller in Execute Stage logic IllegalERegAdrD; // RV32E attempts to write upper 16 registers @@ -146,29 +146,29 @@ module controller( logic Funct7ZeroD, Funct7b5D, IShiftD, INoShiftD; logic Funct7ShiftZeroD, Funct7Shiftb5D; - assign Funct7ZeroD = (Funct7D == 7'b0000000); // most R-type instructions - assign Funct7b5D = (Funct7D == 7'b0100000); // srai, sub + assign Funct7ZeroD = (Funct7D == 7'b0000000); // most R-type instructions + assign Funct7b5D = (Funct7D == 7'b0100000); // srai, sub assign Funct7ShiftZeroD = (`XLEN==64) ? (Funct7D[6:1] == 6'b000000) : Funct7ZeroD; assign Funct7Shiftb5D = (`XLEN==64) ? (Funct7D[6:1] == 6'b010000) : Funct7b5D; - assign IShiftD = (Funct3D == 3'b001 & Funct7ShiftZeroD) | (Funct3D == 3'b101 & (Funct7ShiftZeroD | Funct7Shiftb5D)); // slli, srli, srai, or w forms - assign INoShiftD = ((Funct3D != 3'b001) & (Funct3D != 3'b101)); - assign IFunctD = IShiftD | INoShiftD; - assign RFunctD = ((Funct3D == 3'b000 | Funct3D == 3'b101) & Funct7b5D) | Funct7ZeroD; - assign MFunctD = (Funct7D == 7'b0000001) & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv - assign LFunctD = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | Funct3D == 3'b100 | Funct3D == 3'b101 | - ((`XLEN == 64) & (Funct3D == 3'b011 | Funct3D == 3'b110)); - assign SFunctD = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | - ((`XLEN == 64) & (Funct3D == 3'b011)); - assign BFunctD = (Funct3D[2:1] != 2'b01); // legal branches - assign JFunctD = (Funct3D == 3'b000); + assign IShiftD = (Funct3D == 3'b001 & Funct7ShiftZeroD) | (Funct3D == 3'b101 & (Funct7ShiftZeroD | Funct7Shiftb5D)); // slli, srli, srai, or w forms + assign INoShiftD = ((Funct3D != 3'b001) & (Funct3D != 3'b101)); + assign IFunctD = IShiftD | INoShiftD; + assign RFunctD = ((Funct3D == 3'b000 | Funct3D == 3'b101) & Funct7b5D) | Funct7ZeroD; + assign MFunctD = (Funct7D == 7'b0000001) & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv + assign LFunctD = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | Funct3D == 3'b100 | Funct3D == 3'b101 | + ((`XLEN == 64) & (Funct3D == 3'b011 | Funct3D == 3'b110)); + assign SFunctD = Funct3D == 3'b000 | Funct3D == 3'b001 | Funct3D == 3'b010 | + ((`XLEN == 64) & (Funct3D == 3'b011)); + assign BFunctD = (Funct3D[2:1] != 2'b01); // legal branches + assign JFunctD = (Funct3D == 3'b000); end else begin:legalcheck2 - assign IFunctD = 1; // Don't bother to separate out shift decoding - assign RFunctD = ~Funct7D[0]; // Not a multiply - assign MFunctD = Funct7D[0] & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv - assign LFunctD = 1; // don't bother to check Funct3 for loads - assign SFunctD = 1; // don't bother to check Funct3 for stores - assign BFunctD = 1; // don't bother to check Funct3 for branches - assign JFunctD = 1; // don't bother to check Funct3 for jumps + assign IFunctD = 1; // Don't bother to separate out shift decoding + assign RFunctD = ~Funct7D[0]; // Not a multiply + assign MFunctD = Funct7D[0] & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])); // muldiv + assign LFunctD = 1; // don't bother to check Funct3 for loads + assign SFunctD = 1; // don't bother to check Funct3 for stores + assign BFunctD = 1; // don't bother to check Funct3 for branches + assign JFunctD = 1; // don't bother to check Funct3 for jumps end // Main Instruction Decoder @@ -182,7 +182,7 @@ module controller( 7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported 7'b0001111: if (`ZIFENCEI_SUPPORTED) ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence - else + else ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0; // fence treated as nop 7'b0010011: if (IFunctD) ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU @@ -337,4 +337,4 @@ module controller( // the synchronous DTIM cannot read immediately after write // a cache cannot read or write immediately after a write assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE_SUPPORTED)) | (|AtomicD)); -endmodule \ No newline at end of file +endmodule diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index a6fb1fdcd..a48b39402 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -108,7 +108,7 @@ module datapath ( flopenrc #(5) Rs1EReg(clk, reset, FlushE, ~StallE, Rs1D, Rs1E); flopenrc #(5) Rs2EReg(clk, reset, FlushE, ~StallE, Rs2D, Rs2E); flopenrc #(5) RdEReg(clk, reset, FlushE, ~StallE, RdD, RdE); - + mux3 #(`XLEN) faemux(R1E, ResultW, IFResultM, ForwardAE, ForwardedSrcAE); mux3 #(`XLEN) fbemux(R2E, ResultW, IFResultM, ForwardBE, ForwardedSrcBE); comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); @@ -121,7 +121,7 @@ module datapath ( // Memory stage pipeline register flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM); flopenrc #(`XLEN) IEUResultMReg(clk, reset, FlushM, ~StallM, IEUResultE, IEUResultM); - flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM); + flopenrc #(5) RdMReg(clk, reset, FlushM, ~StallM, RdE, RdM); flopenrc #(`XLEN) WriteDataMReg(clk, reset, FlushM, ~StallM, ForwardedSrcBE, WriteDataM); // Writeback stage pipeline register and logic diff --git a/src/ieu/forward.sv b/src/ieu/forward.sv index 8bfaa51c6..62cc5ea4f 100644 --- a/src/ieu/forward.sv +++ b/src/ieu/forward.sv @@ -34,7 +34,7 @@ module forward( input logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, RdE, RdM, RdW, // Source and destination registers input logic MemReadE, MDUE, CSRReadE, // Execute stage instruction is a load (MemReadE), divide (MDUE), or CSR read (CSRReadE) input logic RegWriteM, RegWriteW, // Instruction in Memory or Writeback stage writes register file - input logic FCvtIntE, // FPU convert float to int + input logic FCvtIntE, // FPU convert float to int input logic SCE, // Store Conditional instruction // Forwarding controls output logic [1:0] ForwardAE, ForwardBE, // Select signals for forwarding multiplexers diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index 0fdba9e8a..d5b3e8f40 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -29,27 +29,27 @@ `include "wally-config.vh" module ieu ( - input logic clk, reset, + input logic clk, reset, // Decode stage signals - input logic [31:0] InstrD, // Instruction - input logic IllegalIEUFPUInstrD, // Illegal instruction - output logic IllegalBaseInstrD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers + input logic [31:0] InstrD, // Instruction + input logic IllegalIEUFPUInstrD, // Illegal instruction + output logic IllegalBaseInstrD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers // Execute stage signals input logic [`XLEN-1:0] PCE, // PC input logic [`XLEN-1:0] PCLinkE, // PC + 4 - output logic PCSrcE, // Select next PC (between PC+4 and IEUAdrE) - input logic FWriteIntE, FCvtIntE, // FPU writes to integer register file, FPU converts float to int + output logic PCSrcE, // Select next PC (between PC+4 and IEUAdrE) + input logic FWriteIntE, FCvtIntE, // FPU writes to integer register file, FPU converts float to int output logic [`XLEN-1:0] IEUAdrE, // Memory address - output logic IntDivE, W64E, // Integer divide, RV64 W-type instruction - output logic [2:0] Funct3E, // Funct3 instruction field + output logic IntDivE, W64E, // Integer divide, RV64 W-type instruction + output logic [2:0] Funct3E, // Funct3 instruction field output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU src inputs before the mux choosing between them and PCE to put in srcA/B output logic [4:0] RdE, // Destination register // Memory stage signals - input logic SquashSCW, // Squash store conditional, from LSU - output logic [1:0] MemRWM, // Read/write control goes to LSU - output logic [1:0] AtomicM, // Atomic control goes to LSU + input logic SquashSCW, // Squash store conditional, from LSU + output logic [1:0] MemRWM, // Read/write control goes to LSU + output logic [1:0] AtomicM, // Atomic control goes to LSU output logic [`XLEN-1:0] WriteDataM, // Write data to LSU - output logic [2:0] Funct3M, // Funct3 (size and signedness) to LSU + output logic [2:0] Funct3M, // Funct3 (size and signedness) to LSU output logic [`XLEN-1:0] SrcAM, // ALU SrcA to Privileged unit and FPU output logic [4:0] RdM, // Destination register input logic [`XLEN-1:0] FIntResM, // Integer result from FPU (fmv, fclass, fcmp) @@ -66,12 +66,12 @@ module ieu ( output logic [4:0] RdW, // Destination register input logic [`XLEN-1:0] ReadDataW, // LSU's read data // Hazard unit signals - input logic StallD, StallE, StallM, StallW, // Stall signals from hazard unit - input logic FlushD, FlushE, FlushM, FlushW, // Flush signals - output logic FCvtIntStallD, LoadStallD, // Stall causes from IEU to hazard unit + input logic StallD, StallE, StallM, StallW, // Stall signals from hazard unit + input logic FlushD, FlushE, FlushM, FlushW, // Flush signals + output logic FCvtIntStallD, LoadStallD, // Stall causes from IEU to hazard unit output logic MDUStallD, CSRRdStallD, StoreStallD, - output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction - output logic CSRWriteFenceM // CSR write or fence instruction needs to flush subsequent instructions + output logic CSRReadM, CSRWriteM, PrivilegedM,// CSR read, CSR write, is privileged instruction + output logic CSRWriteFenceM // CSR write or fence instruction needs to flush subsequent instructions ); logic [2:0] ImmSrcD; // Select type of immediate extension diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv index cc0439c08..a4ee1cc3e 100644 --- a/src/ieu/regfile.sv +++ b/src/ieu/regfile.sv @@ -52,7 +52,7 @@ module regfile ( always_ff @(negedge clk) if (reset) for(i=1; i